Upon detecting the ID for the ESMT F50D1G41LB chip, the fifth byte
returned is always 0x00 instead of the expected JEDEC continuation code
of 0x7f. This causes detection to fail:
[ 0.304399] spi-nand spi0.0: unknown raw ID c8117f7f00
[ 0.508943] spi-nand: probe of spi0.0 failed with error -524
So let's revert back to the 4 byte ID code for this chip
specifically.
Fixes: 4bd14b2fd8a8 ("mtd: spinand: esmt: Extend IDs to 5 bytes")
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://github.com/openwrt/openwrt/pull/19004
Signed-off-by: Robert Marko <robimarko@gmail.com>
The qca8k dsa switch can use either an external or internal mdio bus.
This depends on whether the mdio node is defined under the switch node
itself and, as such, the internal_mdio_mask is populated with its
internal phys. Upon registering the internal mdio bus, the
internal_mdio_bus of the dsa switch is assigned to this bus.
When an external mdio bus is used, it is left unassigned, though its id
is used to create the device names of the leds.
This leads to the leds being named '(efault):00:green:lan' and so on as
the internal_mdio_bus is null. So let's fix this by adding a null check
and use the devicename of the external bus instead when an external bus
is configured.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19004
Signed-off-by: Robert Marko <robimarko@gmail.com>
The resets in the GCC of the uniphy found in the IPQ5018 SoC are
incorrect which broke the ability to shift between 1G and 2.5G link
speeds. So let's correct the resets based on below two downstream
commits.
In a seperate and prequisite PR to the QCA-SSDK repo, logic has been
implemented to select the right reset based on the link setup so fixed
link scenarios don't break.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18774
Signed-off-by: Robert Marko <robimarko@gmail.com>
With completely carving out GE PHY out of the QCA-SSDK, the named clock
references to the GE PHY RX and TX clocks are no longer needed.
So, let's revert to using the DT indices as per the upstream GCC driver.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18774
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use latest patches sent upstream for review for IPQ5018 GE PHY support:
- Move enablement of the LDO controller to the mdio-ipq4019 driver away
from the CMN PLL driver
- Remove the different patches to add CDT, MSE, AZ, and DAC support they
are all contained in the upstreamed driver.
Accordingly, also set the right property in the DTS for Linksys SPNMX56
to set the right DAC values to accommodate for the short cable length.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18774
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use upstreamed v6.16 patches for IPQ5018 tsens support.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18884
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use upstreamed v6.16 patch for IPQ5018 TCSR support and setting the
download mode.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18884
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use upstreamed patches for IPQ5018 PCIe support, including patches for
phy and controller drivers and dts nodes.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18884
Signed-off-by: Robert Marko <robimarko@gmail.com>
There are NAND IC-s that define 1-bit ECC as the minimal strength,
however that is unsupported by QPIC-SNAND as it only supports 4 or 8 bit
ECC.
Since most of these chips also support 4-bit ECC just fine, instead of
erroring out if 1-bit ECC is requested lets instead default to 4-bit ECC.
Fixes: 01b72ce61e ("qualcommax: ipq50xx: remove ECC user config from board files")
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18795
Signed-off-by: Robert Marko <robimarko@gmail.com>
It seems that kernel cleaned up its kernels so we need to include
<linux/of_platform.h> for of_platform_device_create().
Link: https://github.com/openwrt/openwrt/pull/18795
Signed-off-by: Robert Marko <robimarko@gmail.com>
Using devm_clk_get_enabled() allows simplification of the driver and
dropping of the .remove OP as well.
Link: https://github.com/openwrt/openwrt/pull/18795
Signed-off-by: Robert Marko <robimarko@gmail.com>
6.12 PWM core introduced a bunch of incompatible changes, namely removal
of manual module owner assignment, complete PWM struct allocation and usage
refactor, etc.
So, update the driver to follow other drivers in 6.12 so it compiles.
Link: https://github.com/openwrt/openwrt/pull/18795
Signed-off-by: Robert Marko <robimarko@gmail.com>
Refresh 6.12 patches, those that failed automatic refresh were refreshed
manually.
DT bindings patches that failed were dropped as we dont use them in practice.
Link: https://github.com/openwrt/openwrt/pull/18795
Signed-off-by: Robert Marko <robimarko@gmail.com>
This is an automatically generated commit.
When doing `git bisect`, consider `git bisect --skip`.
Link: https://github.com/openwrt/openwrt/pull/18795
Signed-off-by: Robert Marko <robimarko@gmail.com>
