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qualcommax: ipq50xx: remove named clock references for GE PHY

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With completely carving out GE PHY out of the QCA-SSDK, the named clock
references to the GE PHY RX and TX clocks are no longer needed.
So, let's revert to using the DT indices as per the upstream GCC driver.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18774
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
George Moussalem 2025-05-30 12:00:20 +04:00 committed by Robert Marko
parent 13bd352c37
commit e53592d0f6
1 changed files with 3 additions and 25 deletions
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28
target/linux/qualcommax/patches-6.12/0722-clk-gcc-ipq5018-refer-to-ge-phy-rx-and-tx-clk-providers-by-name.patch → target/linux/qualcommax/patches-6.12/0722-clk-qcom-gcc-ipq5018-refer-to-uniphy-rx-and-tx-clk-providers-by-name.patch
View file

@ -1,10 +1,10 @@
From ce9e56a436e486690097cfbdda2d0c11b60db4c2 Mon Sep 17 00:00:00 2001
From: Ziyang Huang <hzyitc@outlook.com>
Date: Sun, 8 Sep 2024 16:40:12 +0800
Subject: [PATCH] clk: gcc-ipq5018: refer to GE PHY rx and tx clk providers by name
Subject: [PATCH] clk: gcc-ipq5018: refer to UNIPHY rx and tx clk providers by name
QCA-SSDK does not register the output clocks of the onboard GE Phy and
uniphy so the GCC and DTS can't reference them by their index.
QCA-SSDK does not register the output clocks of the onboard uniphy so the
GCC and DTS can't reference them by their index.
The SSDK references them by name, so let's change the GCC driver
accordingly.
@ -16,28 +16,6 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
--- a/drivers/clk/qcom/gcc-ipq5018.c
+++ b/drivers/clk/qcom/gcc-ipq5018.c
@@ -336,8 +336,8 @@ static const struct parent_map gcc_xo_gp
static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = {
{ .index = DT_XO },
- { .index = DT_GEPHY_RX_CLK },
- { .index = DT_GEPHY_TX_CLK },
+ { .name = "gephy_gcc_rx", .index = -1 },
+ { .name = "gephy_gcc_tx", .index = -1 },
{ .hw = &ubi32_pll.clkr.hw },
{ .hw = &gpll0.clkr.hw },
};
@@ -352,8 +352,8 @@ static const struct parent_map gcc_xo_ge
static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = {
{ .index = DT_XO },
- { .index = DT_GEPHY_TX_CLK },
- { .index = DT_GEPHY_RX_CLK },
+ { .name = "gephy_gcc_tx", .index = -1 },
+ { .name = "gephy_gcc_rx", .index = -1 },
{ .hw = &ubi32_pll.clkr.hw },
{ .hw = &gpll0.clkr.hw },
};
@@ -368,8 +368,8 @@ static const struct parent_map gcc_xo_ge
static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {