qualcommax: ipq50xx: backport upstreamed patches for IPQ5018 PCIe support
Use upstreamed patches for IPQ5018 PCIe support, including patches for phy and controller drivers and dts nodes. Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/18884 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
George Moussalem
Robert Marko
parent
54c7538476
commit
08ff2807cf
12 changed files with 55 additions and 234 deletions
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@ -1,16 +1,23 @@
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From: Varadarajan Narayanan <quic_varada@quicinc.com>
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Date: Thu, 2 Jan 2025 17:00:16 +0530
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From 74badb8b0b146668cc6c03eb58e2a814f9463d02 Mon Sep 17 00:00:00 2001
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From: Nitheesh Sekar <quic_nsekar@quicinc.com>
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Date: Thu, 20 Feb 2025 15:12:46 +0530
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Subject: [PATCH] phy: qcom: Introduce PCIe UNIPHY 28LP driver
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From: Nitheesh Sekar <quic_nsekar@quicinc.com>
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Add Qualcomm PCIe UNIPHY 28LP driver support present
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in Qualcomm IPQ5332 SoC and the phy init sequence.
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Add Qualcomm PCIe UNIPHY 28LP driver support present in Qualcomm IPQ5332
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SoC and the phy init sequence.
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
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Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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Link: https://lore.kernel.org/r/20250220094251.230936-3-quic_varada@quicinc.com
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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drivers/phy/qualcomm/Kconfig | 12 +
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drivers/phy/qualcomm/Makefile | 1 +
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.../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 286 ++++++++++++++++++
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3 files changed, 299 insertions(+)
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create mode 100644 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
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--- a/drivers/phy/qualcomm/Kconfig
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+++ b/drivers/phy/qualcomm/Kconfig
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@@ -154,6 +154,18 @@ config PHY_QCOM_M31_USB
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@ -44,7 +51,7 @@ Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
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--- /dev/null
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+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
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@@ -0,0 +1,285 @@
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@@ -0,0 +1,286 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (c) 2025, The Linux Foundation. All rights reserved.
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@ -63,6 +70,7 @@ Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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+#include <linux/platform_device.h>
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+#include <linux/regmap.h>
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+#include <linux/reset.h>
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+#include <linux/units.h>
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+
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+#define RST_ASSERT_DELAY_MIN_US 100
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+#define RST_ASSERT_DELAY_MAX_US 150
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@ -89,8 +97,6 @@ Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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+#define PHY_CFG_EIOS_DTCT_REG 0x3e4
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+#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8
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+
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+#define PHY_MODE_FIXED 0x1
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+
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+enum qcom_uniphy_pcie_type {
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+ PHY_TYPE_PCIE = 1,
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+ PHY_TYPE_PCIE_GEN2,
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@ -141,7 +147,7 @@ Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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+ .phy_type = PHY_TYPE_PCIE_GEN3,
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+ .init_seq = ipq5332_regs,
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+ .init_seq_num = ARRAY_SIZE(ipq5332_regs),
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+ .pipe_clk_rate = 250000000,
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+ .pipe_clk_rate = 250 * MEGA,
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+};
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+
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+static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy)
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@ -200,6 +206,7 @@ Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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+ usleep_range(CLK_EN_DELAY_MIN_US, CLK_EN_DELAY_MAX_US);
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+
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+ qcom_uniphy_pcie_init(phy);
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+
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+ return 0;
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+}
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+
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@ -292,8 +299,9 @@ Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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+ if (!phy->data)
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+ return -EINVAL;
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+
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+ phy->lanes = 1;
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+ ret = of_property_read_u32(dev->of_node, "num-lanes", &phy->lanes);
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+ ret = of_property_read_u32(dev_of_node(dev), "num-lanes", &phy->lanes);
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+ if (ret)
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+ return dev_err_probe(dev, ret, "Couldn't read num-lanes\n");
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+
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+ ret = qcom_uniphy_pcie_get_resources(pdev, phy);
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+ if (ret < 0)
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@ -1,15 +1,24 @@
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From: George Moussalem <george.moussalem@outlook.com>
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Date: Tue, 07 Jan 2025 17:34:13 +0400
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Subject: [PATCH] phy: qualcomm: qcom-uniphy-pcie 28lp add support for IPQ5018
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From dfc820d2f8a8ea90bbc02269b5362e3678e58cac Mon Sep 17 00:00:00 2001
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From: Nitheesh Sekar <quic_nsekar@quicinc.com>
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Date: Wed, 26 Mar 2025 12:10:56 +0400
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Subject: [PATCH] phy: qualcomm: qcom-uniphy-pcie 28LP add support for IPQ5018
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The Qualcomm UNIPHY PCIe PHY 28lp is found on both IPQ5332 and IPQ5018.
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The Qualcomm UNIPHY PCIe PHY 28LP is found on both IPQ5332 and IPQ5018.
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Adding the PHY init sequence, pipe clock rate, and compatible for IPQ5018.
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Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
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Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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Link: https://lore.kernel.org/r/20250326-ipq5018-pcie-v7-2-e1828fef06c9@outlook.com
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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.../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 45 +++++++++++++++++++
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1 file changed, 45 insertions(+)
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--- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
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+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
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@@ -76,6 +76,40 @@ struct qcom_uniphy_pcie {
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@@ -75,6 +75,40 @@ struct qcom_uniphy_pcie {
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#define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy)
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@ -50,7 +59,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = {
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{
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.offset = PHY_CFG_PLLCFG,
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@@ -89,6 +123,14 @@ static const struct qcom_uniphy_pcie_reg
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@@ -88,6 +122,14 @@ static const struct qcom_uniphy_pcie_reg
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},
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};
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@ -59,7 +68,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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+ .phy_type = PHY_TYPE_PCIE_GEN2,
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+ .init_seq = ipq5018_regs,
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+ .init_seq_num = ARRAY_SIZE(ipq5018_regs),
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+ .pipe_clk_rate = 125000000,
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+ .pipe_clk_rate = 125 * MEGA,
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+};
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+
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static const struct qcom_uniphy_pcie_data ipq5332_data = {
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@ -1,95 +1,7 @@
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From patchwork Sat Apr 26 08:47:20 2025
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Date: Sat, 26 Apr 2025 12:47:20 +0400
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Subject: [PATCH v9 1/2] arm64: dts: qcom: ipq5018: Add PCIe related nodes
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Precedence: bulk
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References: <20250426-ipq5018-pcie-v9-0-1f0dca6c205b@outlook.com>
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In-Reply-To: <20250426-ipq5018-pcie-v9-0-1f0dca6c205b@outlook.com>
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To: Vinod Koul <vkoul@kernel.org>,
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Kishon Vijay Abraham I <kishon@kernel.org>, Rob Herring <robh@kernel.org>,
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Krzysztof Kozlowski <krzk+dt@kernel.org>,
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Conor Dooley <conor+dt@kernel.org>,
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Nitheesh Sekar <quic_nsekar@quicinc.com>,
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Varadarajan Narayanan <quic_varada@quicinc.com>,
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Bjorn Helgaas <bhelgaas@google.com>,
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Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy?=
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=?utf-8?q?=C5=84ski?= <kw@linux.com>,
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Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
|
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Bjorn Andersson <andersson@kernel.org>,
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Konrad Dybcio <konradybcio@kernel.org>,
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Praveenkumar I <quic_ipkumar@quicinc.com>
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Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
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devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
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linux-pci@vger.kernel.org, George Moussalem <george.moussalem@outlook.com>,
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20250317100029.881286-1-quic_varada@quicinc.com,
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20250317100029.881286-2-quic_varada@quicinc.com,
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Sricharan R <quic_srichara@quicinc.com>,
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Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
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Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
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From 18a5bf00a02ca54d51266b861518f2844c4f08d7 Mon Sep 17 00:00:00 2001
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From: Nitheesh Sekar <quic_nsekar@quicinc.com>
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Date: Wed, 14 May 2025 09:52:13 +0400
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Subject: [PATCH] arm64: dts: qcom: ipq5018: Add PCIe related nodes
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Add phy and controller nodes for a 2-lane Gen2 and
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a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
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@ -103,14 +15,16 @@ Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
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Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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Link: https://lore.kernel.org/r/20250514-ipq5018-pcie-v10-1-5b42a8eff7ea@outlook.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 238 +++++++++++++++++++++++++++++++++-
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1 file changed, 236 insertions(+), 2 deletions(-)
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 240 +++++++++++++++++++++++++-
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1 file changed, 238 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -258,6 +258,40 @@
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#thermal-sensor-cells = <1>;
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@@ -147,6 +147,40 @@
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status = "disabled";
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};
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+ pcie1_phy: phy@7e000 {
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@ -150,7 +64,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5018-tlmm";
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reg = <0x01000000 0x300000>;
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@@ -281,8 +315,8 @@
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@@ -170,8 +204,8 @@
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reg = <0x01800000 0x80000>;
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clocks = <&xo_board_clk>,
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<&sleep_clk>,
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@ -161,7 +75,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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<0>,
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<0>,
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<0>,
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@@ -498,6 +532,208 @@
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@@ -387,6 +421,208 @@
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status = "disabled";
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};
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};
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@ -369,4 +283,4 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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+ };
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};
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thermal-zones {
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timer {
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@ -15,7 +15,7 @@ Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -147,6 +147,117 @@
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@@ -181,6 +181,117 @@
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status = "disabled";
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};
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@ -133,7 +133,7 @@ Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
|
|||
tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,ipq5018-tlmm";
|
||||
reg = <0x01000000 0x300000>;
|
||||
@@ -388,6 +499,64 @@
|
||||
@@ -624,6 +735,64 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,85 +0,0 @@
|
|||
From: Varadarajan Narayanan <quic_varada@quicinc.com>
|
||||
Date: Thu, 2 Jan 2025 17:00:15 +0530
|
||||
Subject: [PATCH] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
|
||||
|
||||
From: Nitheesh Sekar <quic_nsekar@quicinc.com>
|
||||
|
||||
Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332.
|
||||
|
||||
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
|
||||
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
|
||||
---
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
|
||||
@@ -0,0 +1,71 @@
|
||||
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
+%YAML 1.2
|
||||
+---
|
||||
+$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml#
|
||||
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
+
|
||||
+title: Qualcomm UNIPHY PCIe 28LP PHY
|
||||
+
|
||||
+maintainers:
|
||||
+ - Nitheesh Sekar <quic_nsekar@quicinc.com>
|
||||
+ - Varadarajan Narayanan <quic_varada@quicinc.com>
|
||||
+
|
||||
+description:
|
||||
+ PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC
|
||||
+
|
||||
+properties:
|
||||
+ compatible:
|
||||
+ enum:
|
||||
+ - qcom,ipq5332-uniphy-pcie-phy
|
||||
+
|
||||
+ reg:
|
||||
+ maxItems: 1
|
||||
+
|
||||
+ clocks:
|
||||
+ items:
|
||||
+ - description: pcie pipe clock
|
||||
+ - description: pcie ahb clock
|
||||
+
|
||||
+ resets:
|
||||
+ items:
|
||||
+ - description: phy reset
|
||||
+ - description: ahb reset
|
||||
+ - description: cfg reset
|
||||
+
|
||||
+ "#phy-cells":
|
||||
+ const: 0
|
||||
+
|
||||
+ "#clock-cells":
|
||||
+ const: 0
|
||||
+
|
||||
+ num-lanes: true
|
||||
+
|
||||
+required:
|
||||
+ - compatible
|
||||
+ - reg
|
||||
+ - clocks
|
||||
+ - resets
|
||||
+ - "#phy-cells"
|
||||
+ - "#clock-cells"
|
||||
+
|
||||
+additionalProperties: false
|
||||
+
|
||||
+examples:
|
||||
+ - |
|
||||
+ #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
|
||||
+
|
||||
+ pcie0_phy: phy@4b0000 {
|
||||
+ compatible = "qcom,ipq5332-uniphy-pcie-phy";
|
||||
+ reg = <0x004b0000 0x800>;
|
||||
+
|
||||
+ clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
|
||||
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
|
||||
+
|
||||
+ resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
|
||||
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
|
||||
+ <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
|
||||
+
|
||||
+ #clock-cells = <0>;
|
||||
+
|
||||
+ #phy-cells = <0>;
|
||||
+ };
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
From: George Moussalem <george.moussalem@outlook.com>
|
||||
Date: Tue, 07 Jan 2025 17:34:13 +0400
|
||||
Subject: [PATCH] phy: qualcomm: qcom-uniphy-pcie add IPQ5018 compatible
|
||||
|
||||
The Qualcomm UNIPHY PCIe PHY 28lp part of the IPQ5332 SoC is also present on
|
||||
the IPQ5018 SoC, so adding the compatible for IPQ5018.
|
||||
|
||||
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
||||
---
|
||||
--- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
|
||||
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
|
||||
@@ -11,11 +11,12 @@ maintainers:
|
||||
- Varadarajan Narayanan <quic_varada@quicinc.com>
|
||||
|
||||
description:
|
||||
- PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC
|
||||
+ PCIe and USB combo PHY found in Qualcomm IPQ5018 and IPQ5332 SoCs
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
+ - qcom,ipq5018-uniphy-pcie-phy
|
||||
- qcom,ipq5332-uniphy-pcie-phy
|
||||
|
||||
reg:
|
||||
|
|
@ -9,7 +9,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|||
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -293,6 +293,30 @@
|
||||
status = "disabled";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
+ cryptobam: dma-controller@704000 {
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|||
---
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -220,6 +220,14 @@
|
||||
@@ -254,6 +254,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
|
|||
sleep_clk: sleep-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
@@ -148,6 +154,19 @@
|
||||
@@ -182,6 +188,19 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -154,6 +154,30 @@
|
||||
@@ -188,6 +188,30 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|||
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -164,6 +164,21 @@
|
||||
@@ -198,6 +198,21 @@
|
||||
clock-names = "gcc_mdio_ahb_clk";
|
||||
|
||||
status = "disabled";
|
||||
|
|
|
|||
Loading…
Reference in a new issue