RTL83xx devices have two types of receive interrupts for each of its
8 rings. One for packet received and another for ring overflow. When
the switch is flooded with incoming packets the receive handler will
disable the packet receive notification but still keeps the overflow
notification enabled. While the receive path "slowly" processes the
received packets each new packet triggers the overflow IRQ again. The
device becomes unresponsive and eventually produces messages like:
[18441.709764] rcu: Stack dump where RCU GP kthread last ran:
[18441.727892] Sending NMI from CPU 1 to CPUs 0:
[18441.742300] NMI backtrace for cpu 0 skipped: idling at 0x8080e994
[18415.251700] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[18415.271350] rcu: 0-...!: (0 ticks this GP) idle=d740/0/0x0 ...
[18415.303046] rcu: (detected by 1, t=6004 jiffies, g=230925, ...
[18415.326095] Sending NMI from CPU 1 to CPUs 0:
[18415.340540] NMI backtrace for cpu 0
Fix this issue by always disabling receive and overflow interrupts at
the same time.
Test with hping3 --udp -p 5021 -d 1400 --flood 192.168.2.72
Before (3sec run):
[183260.324846] rtl838x-eth 1b00a300.ethernet eth0: RX buffer overrun: status 0x101, mask: 0x7ffeff
[183260.340524] rtl838x-eth 1b00a300.ethernet eth0: RX buffer overrun: status 0x1, mask: 0x7ffeff
[183260.345799] net_ratelimit: 489997 callbacks suppressed
After (3 sec run):
[ 373.981479] rtl838x-eth 1b00a300.ethernet eth0: rx ring overrun: status 0x101, mask: 0x7fffff
[ 374.031118] rtl838x-eth 1b00a300.ethernet eth0: rx ring overrun: status 0x101, mask: 0x7fffff
[ 377.919996] net_ratelimit: 34 callbacks suppressed
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19365
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The current implementation has several issues:
- it uses the hacky phy_port* macros
- it uses SoC dependent raw pages
- it disables/enables SoC dependent polling
Get rid of these dependencies and access the mdio bus the normal way.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19372
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
In rtl931x_led_init, the number of leds per port is not properly set. It
currently uses a hardcoded value of 1 which seems to be taken initially
from a specific device. This hardcoded value assumes any port always has
exactly two leds.
The RTL930x variant - rtl930x_led_init - does a better job at this. So
take it and use it for RTL931x too with the corresponding register.
While at it, rename the function to a proper naming scheme.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19241
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The operating mode of a SerDes must be aligned with the attached PHY or
SFP module. That does not only require to change the protocol (e.g. SGMII,
10Gbase-R, ...) but also the speed (e.g. 1.25G). For this the SerDes must
be re-initialized properly.
- It must be taken into power down
- The PLL speed must be set
- Maybe the CMU (clock management unit) must be resetted
- The new mode must be set
- The state machine must be resetted
- The power must be reactivated
Until now this sequence is bugged. First the driver relies on a clean
setup from U-Boot (rtk network on) and second trying to to change mode
and PLL speeds does not work at all. And not to forget: Currently two
adjacent SerDes cannot drive SGMII/HSGMII at the same time. Fix this by
taking care about the right SerDes/PLL/CMU command init order.
P.S. This code is inspired by the work of Jan Hofmann, who tried to
enable parallel SGMII/HSGMII mode. The only missing bit was a proper CMU
reset sequence.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19220
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL931x devices have an other register that describes the
current RAM configuration. Enhance the identification routine.
Tested on LGS352C (RTL9311).
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19284
Signed-off-by: Robert Marko <robimarko@gmail.com>
Until now the rt-loader only works on U-Boot driven devices where the
environment (e.g. coprocessor) is usually setup properly. Devices like
the ZyXEL GS1920 series use BootBase as start environment and skip
some of the basic initialization steps. rt-loader will fail in these
cases. Take care about the CP0 registers.
Additionally enhance the documentation of the printf implementation.
It was optimized during the different revisions of the initial PR.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19253
Signed-off-by: Robert Marko <robimarko@gmail.com>
There are too many supported Realtek devices so avoid activating the
rt loader recipe in the default builds. Just start with the LGS310C.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18397
Signed-off-by: Robert Marko <robimarko@gmail.com>
To make use of the new rt-loader provide the needed recipes.
This has been tested with the following devices:
- rtl838x Linksys LGS310: initramfs & flash
- rtl930x Zyxel XGS1210: initramfs
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18397
Signed-off-by: Robert Marko <robimarko@gmail.com>
The bootloader of many Realtek switches only supports gzipped kernel images.
With limited flash space that might get critical in future versions. For better
compression allow support for compressed images. For this a new loader was
developed. Several ideas have been taken over from the existing lzma loader
but this has been enhanced to make integration simpler. What is new:
- Loader is position independent. No need to define load addresses
- Loader identifies device memory on its own
- Loader uses "official" upstream kernel lzma uncompress
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/lib/decompress_unlzma.c
- Loader uses "official" UNMODIFIED nanoprintg that is used by several
bare metal projects. https://github.com/charlesnicholson/nanoprintf
Compiled the loader ist just under 12KiB and during boot it will show:
rt-loader
Found RTL8380M (chip id 6275C) with 256MB
Relocate 2924240 bytes from 0x80100000 to 0x8fce0000
Extract kernel with 2900144 bytes from 0x8fce521c to 0x80100000...
Extracted kernel size is 9814907 bytes
Booting kernel from 0x80100000 ...
[ 0.000000] Linux version 6.12.33 ...
[ 0.000000] RTL838X model is 83806800
...
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18397
Signed-off-by: Robert Marko <robimarko@gmail.com>
During setup the mdio driver decides the polling mode of the 4 smi
busses depending on the DTS phy settings. This works as follows:
- set polling to c45 if at least one phy is ethernet-phy-ieee802.3-c45
- set polling to c22 if all phys are ethernet-phy-ieee802.3-c22
On RTL930x it is not possible to switch to c22 if uboot has set c45
before. Fix this by overwriting the bitfield properly. While we are
here:
- Sort variables according to kernel style (inverse christmas tree)
- Initialize fields properly with = { 0 }
- Use GENMASK() for better readability
- Make use of RTMDIO_MAX_SMI_BUS
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19161
Signed-off-by: Robert Marko <robimarko@gmail.com>
Until now the timer management on the RTL931x devices depends
on the MIPS default timer. Looking at the clock progress on
these devices one can see that it is totally off. It is running
at half the required speed (e.g. if 1 minute passes the date
command shows that according to the timers only 30 seconds have
elapsed). This is a mix from wrong DTS and bad startup code.
This is not only a cosmetic issue but has effects on every
delay operation inside the kernel. Switch RTL931x to the proven
Otto timer.
Tested on LGS352C based on RTL9311.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19205
Signed-off-by: Robert Marko <robimarko@gmail.com>
The Otto timer is very helpful on the RTL931x devices.
Include it into the builds.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19205
Signed-off-by: Robert Marko <robimarko@gmail.com>
Upstream has gained support for forced affinity settings in the MIPS
GIC interrupt controller. This is needed to enable the Otto timer on
the RTL931x platform. See
https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/
commit/?id=2250db8628a0d8293ad2e0671138b848a185fba1
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19205
Signed-off-by: Robert Marko <robimarko@gmail.com>
Remove all files etc. for 6.6 because 6.12 is default now.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19139
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use Linux 6.12 as default for all subtargets.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19139
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. For
this device it is only a substitution of the existing DTS configuration.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. For
this device it is only a substitution of the existing DTS configuration.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. For
this device it is only a substitution of the existing DTS configuration.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. For
this device it is only a substitution of the existing DTS configuration.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. With
this change the driver now knows that ports 24/26 are driven by serdes
4/5.
For the RTL838x devices this is currently only an additional information
for the mdio bus. It is not evaluated further because everything is
hardcoded.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. With
this change the driver now knows that ports 24/26 are driven by serdes
4/5.
For the RTL838x devices this is currently only an additional information
for the mdio bus. It is not evaluated further because everything is
hardcoded.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. With
this change the driver now knows that ports 24/26 are driven by serdes
4/5.
For the RTL838x devices this is currently only an additional information
for the mdio bus. It is not evaluated further because everything is
hardcoded.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. With
this change the driver now knows that ports 24/26 are driven by serdes
4/5.
For the RTL838x devices this is currently only an additional information
for the mdio bus. It is not evaluated further because everything is
hardcoded.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. With
this change the driver now knows that ports 24/26 are driven by serdes
4/5.
For the RTL838x devices this is currently only an additional information
for the mdio bus. It is not evaluated further because everything is
hardcoded.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. With
this change the driver now knows that ports 24/26 are driven by serdes
4/5.
For the RTL838x devices this is currently only an additional information
for the mdio bus. It is not evaluated further because everything is
hardcoded.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. With
this change the driver now knows that ports 24/26 are driven by serdes
4/5.
For the RTL838x devices this is currently only an additional information
for the mdio bus. It is not evaluated further because everything is
hardcoded.
REMARK! The original commit c829bc1f2c ("realtek: Add support for
Netgear S350 series switches GS308T and GS310TP") says that the SFP
ports are untested. Looking at device internal pictures from
https://techinfodepot.shoutwiki.com/wiki/Netgear_GS310TP there are no
external phys for the SFP ports. So fix port description.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. With
this change the driver now knows that ports 24/26 are driven by serdes
4/5.
For the RTL838x devices this is currently only an additional information
for the mdio bus. It is not evaluated further because everything is
hardcoded.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. With
this change the driver now knows that ports 24/26 are driven by serdes
4/5.
For the RTL838x devices this is currently only an additional information
for the mdio bus. It is not evaluated further because everything is
hardcoded.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. With
this change the driver now knows that ports 24/26 are driven by serdes
4/5.
For the RTL838x devices this is currently only an additional information
for the mdio bus. It is not evaluated further because everything is
hardcoded.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. With
this change the driver now knows that ports 24/26 are driven by serdes
4/5.
For the RTL838x devices this is currently only an additional information
for the mdio bus. It is not evaluated further because everything is
hardcoded.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Until now only the RTL930x devices make use of the following notation.
phy8: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c22";
phy-is-integrated;
reg = <8>;
sds = <3>;
};
This indicates that the link is driven by a serdes directly without
external phy. As the devices have multiple serdes it must be clarified
what serdes is responsible for that port.
Nevertheless all other devices have the same requirements. E.g. RTL838x
usually drives port 24 from serdes 4 and port 26 from serdes 5. All this
currently works because the driver has a lot of hardcoded port/serdes
mapping.
Make the situation better by adding dts helpers that can describe the
topology as needed.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18851
Signed-off-by: Robert Marko <robimarko@gmail.com>
Run this script:
./scripts/kconfig-reorder.sh
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Link: https://github.com/openwrt/openwrt/pull/19200
Signed-off-by: Robert Marko <robimarko@gmail.com>
This allows the SFPs to work without manually switching port type.
Signed-off-by: Joe Holden <jwh@zorins.us>
Link: https://github.com/openwrt/openwrt/pull/18914
Signed-off-by: Robert Marko <robimarko@gmail.com>
The 4 sfp ports on the RTL8214FC are actually wired to the gpio expander instead of internal.
Relatively minor changes to the dts are required, simply overriding some of the properties
inherited from rtl8393_hpe_1920.dtsi.
The speed is reported as 100/full and the media type is incorrect, but the ports pass traffic
just fine.
Signed-off-by: Joe Holden <jwh@zorins.us>
Link: https://github.com/openwrt/openwrt/pull/18914
Signed-off-by: Robert Marko <robimarko@gmail.com>
The SMP environment is prepared well for the RTL93X. Now describe the
power cluster controller in the DTS. Tested on RTL9311 based Linksys
LGS352C.
Without patch:
root@OpenWrt:~# dmesg | grep CPU
[ 0.140425] CPU1 revision is: 0001a120 (MIPS interAptiv (multi))
[ 0.191952] Synchronize counters for CPU 1: done.
[ 1.232191] CPU2: failed to start
[ 1.237863] No online CPU in core 1 to start CPU3
[ 2.273784] CPU3: failed to start
[ 2.277589] smp: Brought up 1 node, 2 CPUs
root@OpenWrt:~# cat /proc/cpuinfo | grep -E "model|proc"
processor : 0
cpu model : MIPS interAptiv (multi) V2.0
processor : 1
cpu model : MIPS interAptiv (multi) V2.0
With patch:
root@OpenWrt:~# dmesg | grep CPU
[ 0.000000] CPU0 revision is: 0001a120 (MIPS interAptiv (multi))
[ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[ 0.000000] Failed to get CPU clock: -2
[ 0.000000] CPU frequency from device tree: 1000MHz
[ 0.133360] smp: Bringing up secondary CPUs ...
[ 0.140418] CPU1 revision is: 0001a120 (MIPS interAptiv (multi))
[ 0.191950] Synchronize counters for CPU 1: done.
[ 0.230103] CPU2 revision is: 0001a120 (MIPS interAptiv (multi))
[ 0.289220] Synchronize counters for CPU 2: done.
[ 0.326189] CPU3 revision is: 0001a120 (MIPS interAptiv (multi))
[ 0.378861] Synchronize counters for CPU 3: done.
[ 0.413829] smp: Brought up 1 node, 4 CPUs
processor : 0
cpu model : MIPS interAptiv (multi) V2.0
processor : 1
cpu model : MIPS interAptiv (multi) V2.0
processor : 2
cpu model : MIPS interAptiv (multi) V2.0
processor : 3
cpu model : MIPS interAptiv (multi) V2.0
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19110
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The switchcore node is the central location that describes the Realtek switch
register addresses starting at 0x1b000000. It will be used by current and
future regmap enabled device drivers. The upstream MDIO driver already makes
use of it by calling syscon_node_to_regmap(dev->parent->of_node);
In the current DTS base we have 3 issues that should be fixed:
- rtl838x.dtsi has a length of 0x20000 instead of 0x10000
- rtl839x.dtsi has a length of 0x20000 instead of 0x10000
- rtl931x.dtsi has no switchcore node at all
Align these mismatches with the "good" RTL930x template.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18642
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The drivers for I2C bus and mux for RTL931x have an incorrectly defined
SDA0 pin number, causing an error with correct pin numbers specified in
the device tree.
Using the `show tech-support board` on the vendor firmware of a Netgear
MS510TXM shows the correct pin numbers but they don't work with the
drivers. So fix this.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19171
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport accepted BCM5325 patches from net-next.
These patches will be merged in the v6.17 kernel window.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
From now on both SFP ports can be used without manual intervention.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18737
Signed-off-by: Robert Marko <robimarko@gmail.com>
Currently only RTL83xx devices are known with shared SCL pins.
So activate the driver only for those targets.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18737
Signed-off-by: Robert Marko <robimarko@gmail.com>
Some Realtek switches have been designed with I2C busses that share a
single SCL line. The clock line is used for 2 or more busses. This cannot
be used with the standard i2c-gpio driver that relies on distinct SDA
and SCL pairs.
Provide a derived i2c-gpio-shared driver that can be used instead. This
driver can handle up to 4 busses with only a single clock line.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18737
Signed-off-by: Robert Marko <robimarko@gmail.com>
The Zyxel XGS1210-12 Switch is a 10 + 2 port multi-GBit switch with
8 x 1000BaseT, 2 x 10/100/1000/2500BaseT Ethernet ports and
2 SFP+ module slot.
Hardware:
- RTL9302B SoC
- Macronix MX25L12833F (16MB flash)
- Nanja NT5CC64M16GP-1 (128MB DDR3 SDRAM)
- RTL8231 GPIO extender to control the port LEDs
- RTL8218D 8x Gigabit PHY
- RTL8226 2x 10m/100m/1/2.5 Gigabit PHY
- SFP+ 2x 10GBit slot
Power is supplied via a 12V 1.5A standard barrel connector. At the
right side behind the grid is UART serial connector. A Serial
header can be connected to from the outside of the switch trough
the airvents with a standard 2.54mm header.
Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial
connection is via 115200 baud, 8N1.
A reset button is accessble through a hole in the front panel
At the time of this commit, all ethernet ports work under OpenWrt,
including the various NBaseT modes, SFP+ slots are supported with i2c bus.
Installation
--------------
* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* Navigate to 'Management' in the OEM web interface and click on 'Firmware upgrade'
to the left.
* Upload the OpenWrt initramfs image, and wait till the switch reboots.
* Connect to the device through serial and change the U-boot boot command.
> fw_setenv bootcmd 'rtk network on; boota'
* Reboot, scp the sysupgrade image to /tmp, verify the checksum and flash it:
> sysupgrade openwrt-realtek-rtl930x-Zyxel_xgs1210-12-squashfs-sysupgrade.bin
* Upon reboot, you have a functional OpenWrt installation. Leave the bootcmd
value as is - without 'rtk network on' the switch will fail to initialise
the network.
Debug
------------
* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* A tftp server is requiered, tftpd-hpa works well.
* Power the device, at U-Boot start rapidly hit Esc key to stop autoboot
* Enable network:
> rtk network on
* Change ip address (default is 192.168.1.1):
> setenv ipaddr 192.168.1.6
* Download initramfs:
> tftpboot 0x84f00000 192.168.1.111:openwrt-realtek-rtl930x-Zyxel_xgs1210-12-initramfs-kernel.bin
* Boot loaded file:
> bootm 0x84f00000
This prodecudre also apply to the sock firmware with the file XGS1210-12_V2.00(ABTY.1)C0.bix.
More information can be found on the page of XGS1250-12 as they share the same base.
Signed-off-by: Nicolas BERTRAND <nicolasbertrand89@gmail.com>
[fixed white space error]
Signed-off-by: Paul Spooren <mail@aparcar.org>
The TP-Link TL-ST1008F is an 8-port multi-gig switch with 8x SFP+ ports
which support 1G/2.5G/10G speeds. Out of the box it is an unmanaged
switch but with RTL9303 and sufficient RAM + Flash it easily can run as
a managed Linux switch.
Hardware:
- Realtek RTL9303 Switch SoC
- Winbond 25Q256JVFQ (32MB flash)
- Samsung K4B4G1646E-BYMA (512MB DDR3 SDRAM)
- TCA9534 GPIO extender to control the port LEDs
- 8x SFP+ 1/2.5/10G slot
- Serial: 3V3 logic, 115200 8N1
- 5-pin JTAG
- physical tri-state switch (used by stock firmware for port speed
config)
- 24-LED port speed matrix
- robust full-metal case
Power is supplied via a 12V 2A standard barrel connector.
There are THT holes on the PCB for serial console next to the flash chip
and JTAG pads. Serial uses 3V3 logic and standard 115200-8N1 config.
Pinout is labeled on the PCB.
All ports/connectors and LEDs are on the back, only Power LED is on the
front.
Hints before flashing
----------------------
* It is recommended to backup the stock flash contents before proceeding.
Backup can be done from U-Boot (with memory display), from OpenWrt
initramfs or probably with SPI flash programmer.
There is no stock recovery functionality.
* Use a small image for RAM boot or first flash. Since you need to use
ymodem, this is really slow and takes time.
* This does not keep the dual-partition layout for firmware to have more
space available for a single OpenWrt installation.
Initial flashing
----------------------
The stock U-boot has broken networking thus no TFTP available. Serial
transfer only.
1. Open device and connect serial as per layout and settings
(recommended to use picocom, ymodem not working with minicom)
2. Connect power to device and press Esc when prompted to enter
the U-Boot console.
3. Boot initramfs
* in the U-Boot console:
loady 0x82000000 (load OpenWrt image via ymodem)
CTRL-A CTRL-S <initramfs.bin> (specify initramfs image for
picocom to upload)
bootm 0x82000000 (boot initramfs from RAM)
(Just to be on the safe side, backup your flash now while RAM-booted)
4. Connect network to your device
5. Upload the sysupgrade image (e.g. with scp)
6. Do sysupgrade
There's no need to adjust the bootcmd in U-Boot. Networking is running
fine once the realtek driver initialized everything in OpenWrt. No
functional difference with running 'rtk network on' within U-Boot
before. Running this even fails and returns with an error.
Return to stock
------------------
This only works if you did a backup of the flash before flashing
OpenWrt. Stock dump then can be flashed from within U-Boot or OpenWrt.
There is no vendor firmware image because this is an unmanaged switch!
CAUTION: Make sure to not overwrite the U-Boot partition(s). If you do
not have a flash programmer, you may not be able to debrick
your device then.
Co-authored-by: Balázs Triszka <balika011@gmail.com>
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Only 2 devices use leading zeroes to pad interface names,
align the remaining ones so that it is consistent.
Signed-off-by: Joe Holden <jwh@zorins.us>
Link: https://github.com/openwrt/openwrt/pull/18913
Signed-off-by: Robert Marko <robimarko@gmail.com>
Three different code paths for the same phy model. Now the bus
is prepared to handle c45 (mmd) read/writes correctly. Remove
the custom implementations and let generic kernel functions do
their best. To achieve this
- disable the PHY-mode EEE in rtl821x_config_init() as upstream does
- provide mmd read/write functions that avoid EEE via c45 over c22
While chaning the phy_driver functions sort them alphabetically.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
rtl8214fc_media_is_fibre() will need to be run when bus lock is held.
Split the function into two versions.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
As the mdio bus has been hardened and can now handle c45 requests
the DSA driver must honor that as well. For this
- add proper upstreamed bus read_c45 and write_c45 functions
- take over the disabled port mask from upstream bus
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
