Ovidiu Panait 84488fc693 microblaze: cache: introduce Kconfig options for icache/dcache sizes ... Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for instruction and data caches sizes, respectively: CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE Also, get rid of the hardcoded value in icache_disable(). Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/g)		2022-06-24 14:16:00 +02:00
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bootscripts	xilinx: Add sd boot command script for reference	2019-10-08 09:11:13 +02:00
common	xilinx: fru: Replace spaces with \0 in detected revision	2022-06-06 09:32:26 +02:00
microblaze-generic	microblaze: cache: introduce Kconfig options for icache/dcache sizes	2022-06-24 14:16:00 +02:00
versal	arm64: versal: Add support to load an app at EL1	2022-06-24 14:11:05 +02:00
zynq	capsule: board: Add information needed for capsule updates	2022-04-15 10:43:18 +02:00
zynqmp	arm64: zynqmp: zynqmp-sm-k26-revA: Fix DP PLL configuration	2022-05-18 13:17:54 +02:00
zynqmp_r5	.mailmap: Start to use new amd.com email address	2022-04-19 14:51:11 -04:00
Kconfig	xilinx: Kconfig: add XILINX_OF_BOARD_DTB_ADDR default value for microblaze	2022-01-05 10:22:03 +01:00