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arm64: zynqmp: zynqmp-sm-k26-revA: Fix DP PLL configuration

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This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som.

The Linux DP driver expects the DP to be using the following PLL config:
  - DP video PLL should use the VPLL (0x0)
  - DP audio PLL should use the RPLL (0x3)
  - DP system time clock PLL should use RPLL (0x3)

Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.
Register 0xFD1A007C configures the DP system time clock PLL.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com
This commit is contained in:
Neal Frager 2022-05-16 16:02:19 +02:00 committed by Michal Simek
parent e9869f474c
commit 6be41ea4e6
1 changed files with 3 additions and 0 deletions
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3
board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c
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@ -74,6 +74,9 @@ static unsigned long psu_clock_init_data(void)
psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000A00U);
psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01013803U);
psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);