Merge branch '2021-07-09-arm-updates'

- Assorted ARM platform updates

arch/arm/cpu/armv8/cache.S

@@ -188,27 +188,24 @@ ENDPROC(__asm_invalidate_icache_all)
 .popsection
 
 .pushsection .text.__asm_invalidate_l3_dcache, "ax"
-ENTRY(__asm_invalidate_l3_dcache)
+WEAK(__asm_invalidate_l3_dcache)
 	mov	x0, #0			/* return status as success */
 	ret
 ENDPROC(__asm_invalidate_l3_dcache)
-	.weak	__asm_invalidate_l3_dcache
 .popsection
 
 .pushsection .text.__asm_flush_l3_dcache, "ax"
-ENTRY(__asm_flush_l3_dcache)
+WEAK(__asm_flush_l3_dcache)
 	mov	x0, #0			/* return status as success */
 	ret
 ENDPROC(__asm_flush_l3_dcache)
-	.weak	__asm_flush_l3_dcache
 .popsection
 
 .pushsection .text.__asm_invalidate_l3_icache, "ax"
-ENTRY(__asm_invalidate_l3_icache)
+WEAK(__asm_invalidate_l3_icache)
 	mov	x0, #0			/* return status as success */
 	ret
 ENDPROC(__asm_invalidate_l3_icache)
-	.weak	__asm_invalidate_l3_icache
 .popsection
 
 /*

arch/arm/cpu/armv8/start.S

@@ -132,7 +132,9 @@ pie_fixup_done:
 	msr	cntfrq_el0, x0			/* Initialize CNTFRQ */
 #endif
 	b	0f
-2:	set_vbar	vbar_el2, x0
+2:	mrs	x1, hcr_el2
+	tbnz	x1, #34, 1f			/* HCR_EL2.E2H */
+	set_vbar vbar_el2, x0
 	mov	x0, #0x33ff
 	msr	cptr_el2, x0			/* Enable FP/SIMD */
 	b	0f

arch/arm/lib/bootm.c

@@ -43,6 +43,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct tag *params;
 
+#ifndef CONFIG_ARM64
 static ulong get_sp(void)
 {
 	ulong ret;
@@ -86,6 +87,7 @@ void arch_lmb_reserve(struct lmb *lmb)
 		break;
 	}
 }
+#endif
 
 __weak void board_quiesce_devices(void)
 {

arch/arm/lib/cache-cp15.c

@@ -93,12 +93,6 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
 	mmu_page_table_flush(startpt, stoppt);
 }
 
-void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
-				     enum dcache_option option)
-{
-	mmu_set_region_dcache_behaviour_phys(start, start, size, option);
-}
-
 __weak void dram_bank_mmu_setup(int bank)
 {
 	struct bd_info *bd = gd->bd;
@@ -311,6 +305,12 @@ int dcache_status(void)
 {
 	return 0;					/* always off */
 }
+
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+				     enum dcache_option option)
+{
+}
+
 #else
 void dcache_enable(void)
 {
@@ -326,4 +326,10 @@ int dcache_status(void)
 {
 	return (get_cr() & CR_C) != 0;
 }
+
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+				     enum dcache_option option)
+{
+	mmu_set_region_dcache_behaviour_phys(start, start, size, option);
+}
 #endif