From bfb798461af42ac628e22cbf5a0576fa156e8787 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Wed, 10 Feb 2021 20:14:55 +0100 Subject: [PATCH 1/4] armv8: Handle EL2 Host mode On implementations that support VHE, the layout of the CPTR_EL2 register depends on whether HCR_EL2.E2H is set. If the bit is set, CPTR_EL2 uses the same layout as CPACR_EL1 and can in fact be accessed through that register. In that case, jump to the EL1 code to enable access to the FP/SIMD registers. This allows U-Boot to run on systems that pass control to U-Boot in EL2 with EL2 Host mode enabled such as machines using Apple's M1 SoC. Signed-off-by: Mark Kettenis Acked-by: Marc Zyngier --- arch/arm/cpu/armv8/start.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 662449156b..9e9c6140cd 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -132,11 +132,13 @@ pie_fixup_done: msr cntfrq_el0, x0 /* Initialize CNTFRQ */ #endif b 0f -2: set_vbar vbar_el2, x0 +2: mrs x1, hcr_el2 + tbnz x1, #34, 1f /* HCR_EL2.E2H */ + set_vbar vbar_el2, x0 mov x0, #0x33ff msr cptr_el2, x0 /* Enable FP/SIMD */ b 0f -1: set_vbar vbar_el1, x0 +1: set_vbar vbar_el1, x0 mov x0, #3 << 20 msr cpacr_el1, x0 /* Enable FP/SIMD */ 0: From ee0fbf4ef766f8d6a5a2d35906dfa2e3987f6f66 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 24 Feb 2021 13:48:42 +0100 Subject: [PATCH 2/4] arch: cache: cp15: Add mmu_set_region_dcache_behaviour() when SYS_DCACHE_OFF is enable Fix following compilation issue when SYS_DCACHE_OFF is enable: drivers/misc/scmi_agent.c:128: undefined reference to `mmu_set_region_dcache_behaviour' when SYS_DCACHE_OFF is enable, mmu_set_region_dcache_behaviour() must be defined. Signed-off-by: Patrice Chotard Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/lib/cache-cp15.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index aab1bf4360..0893915b30 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -93,12 +93,6 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, mmu_page_table_flush(startpt, stoppt); } -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, - enum dcache_option option) -{ - mmu_set_region_dcache_behaviour_phys(start, start, size, option); -} - __weak void dram_bank_mmu_setup(int bank) { struct bd_info *bd = gd->bd; @@ -311,6 +305,12 @@ int dcache_status(void) { return 0; /* always off */ } + +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ +} + #else void dcache_enable(void) { @@ -326,4 +326,10 @@ int dcache_status(void) { return (get_cr() & CR_C) != 0; } + +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ + mmu_set_region_dcache_behaviour_phys(start, start, size, option); +} #endif From 2359fa7a87848626bcbd3399e92c657595880cd7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 29 May 2021 13:34:32 +0200 Subject: [PATCH 3/4] arm: bootm: Disable LMB reservation for command line and board info on arm64 On arm64, board info is not applicable and kernel command line patched into the DT, so the LMB reservation here makes no sense anymore. On legacy arm32, this might still be necessary on systems which do not use DT or use legacy ATAGS. Disable this LMB reservation on arm64. This also permits Linux DT to specify reserved memory node at address close to the end of DRAM bank, i.e. overlaping with U-Boot location. Since after boot, U-Boot will be no more, this is OK. Signed-off-by: Marek Vasut Cc: Hai Pham Cc: Simon Goldschmidt Cc: Stephen Warren Cc: Tom Rini --- arch/arm/lib/bootm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index f60ee3a7e6..23b99a541c 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -43,6 +43,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct tag *params; +#ifndef CONFIG_ARM64 static ulong get_sp(void) { ulong ret; @@ -86,6 +87,7 @@ void arch_lmb_reserve(struct lmb *lmb) break; } } +#endif __weak void board_quiesce_devices(void) { From f7b845bfe0621d04f5f32caa14a5aaca799c904e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 29 Jun 2021 19:33:04 -0400 Subject: [PATCH 4/4] arm: armv8: Fix warning about redeclaring global functions as weak As seen with clang-12: warning: __asm_invalidate_l3_dcache changed binding to STB_WEAK As we indeed use ENTRY and then declare the function weak manually. Use the WEAK declarative from instead. Signed-off-by: Tom Rini --- arch/arm/cpu/armv8/cache.S | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 443d94c262..e04907dd8c 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -188,27 +188,24 @@ ENDPROC(__asm_invalidate_icache_all) .popsection .pushsection .text.__asm_invalidate_l3_dcache, "ax" -ENTRY(__asm_invalidate_l3_dcache) +WEAK(__asm_invalidate_l3_dcache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_invalidate_l3_dcache) - .weak __asm_invalidate_l3_dcache .popsection .pushsection .text.__asm_flush_l3_dcache, "ax" -ENTRY(__asm_flush_l3_dcache) +WEAK(__asm_flush_l3_dcache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_flush_l3_dcache) - .weak __asm_flush_l3_dcache .popsection .pushsection .text.__asm_invalidate_l3_icache, "ax" -ENTRY(__asm_invalidate_l3_icache) +WEAK(__asm_invalidate_l3_icache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_invalidate_l3_icache) - .weak __asm_invalidate_l3_icache .popsection /*