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nxp: Finish migration of SYS_FSL_SRDS_[12] to Kconfig

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As this is used on both ARM and PowerPC platforms, this needs to be
listed in arch/Kconfig.nxp and match how they're currently used by
select'ing them under the required PowerPC ARCH_xxx options.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2023-01-10 11:19:42 -05:00
parent 89c90cadf3
commit a84fa1bef4
5 changed files with 18 additions and 29 deletions
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9
arch/Kconfig.nxp
View file

@ -286,4 +286,13 @@ config HAS_FSL_DR_USB
config SYS_DPAA_FMAN config SYS_DPAA_FMAN
bool bool
config SYS_FSL_SRDS_1
bool
config SYS_FSL_SRDS_2
bool
config SYS_HAS_SERDES
bool
endmenu endmenu

9
arch/arm/cpu/armv7/ls102xa/Kconfig
View file

@ -93,15 +93,6 @@ config SYS_FSL_ERRATUM_A010315
config SYS_FSL_HAS_CCI400 config SYS_FSL_HAS_CCI400
bool bool
config SYS_FSL_SRDS_1
bool
config SYS_FSL_SRDS_2
bool
config SYS_HAS_SERDES
bool
config SYS_FSL_ERRATUM_A008407 config SYS_FSL_ERRATUM_A008407
bool bool

9
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View file

@ -567,18 +567,9 @@ config SYS_DP_DDR_BASE_PHY
DDR controller uses this value as the base address for binding. DDR controller uses this value as the base address for binding.
It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
config SYS_FSL_SRDS_1
bool
config SYS_FSL_SRDS_2
bool
config SYS_NXP_SRDS_3 config SYS_NXP_SRDS_3
bool bool
config SYS_HAS_SERDES
bool
config FSL_TZASC_1 config FSL_TZASC_1
bool bool

12
arch/powerpc/cpu/mpc85xx/Kconfig
View file

@ -313,6 +313,8 @@ config ARCH_B4860
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SRDS_1
select SYS_FSL_SRDS_2
select SYS_FSL_SRIO_LIODN select SYS_FSL_SRIO_LIODN
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB1_PHY_ENABLE select SYS_FSL_USB1_PHY_ENABLE
@ -780,6 +782,7 @@ config ARCH_T1024
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SINGLE_SOURCE_CLK select SYS_FSL_SINGLE_SOURCE_CLK
select SYS_FSL_SRDS_1
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC select FSL_IFC
@ -813,6 +816,7 @@ config ARCH_T1040
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SINGLE_SOURCE_CLK select SYS_FSL_SINGLE_SOURCE_CLK
select SYS_FSL_SRDS_1
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC select FSL_IFC
@ -845,6 +849,7 @@ config ARCH_T1042
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SINGLE_SOURCE_CLK select SYS_FSL_SINGLE_SOURCE_CLK
select SYS_FSL_SRDS_1
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC select FSL_IFC
@ -880,6 +885,8 @@ config ARCH_T2080
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SRDS_1
select SYS_FSL_SRDS_2
select SYS_FSL_SRIO_LIODN select SYS_FSL_SRIO_LIODN
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE select SYS_FSL_USB_DUAL_PHY_ENABLE
@ -921,6 +928,8 @@ config ARCH_T4240
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
select SYS_FSL_SEC_BE select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SRDS_1
select SYS_FSL_SRDS_2
select SYS_FSL_SRIO_LIODN select SYS_FSL_SRIO_LIODN
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE select SYS_FSL_USB_DUAL_PHY_ENABLE
@ -1198,9 +1207,6 @@ config SYS_FSL_ERRATUM_SRIO_A004034
config SYS_FSL_ERRATUM_USB14 config SYS_FSL_ERRATUM_USB14
bool bool
config SYS_HAS_SERDES
bool
config SYS_P4080_ERRATUM_CPU22 config SYS_P4080_ERRATUM_CPU22
bool bool

8
arch/powerpc/include/asm/config_mpc85xx.h
View file

@ -96,8 +96,6 @@
#define CFG_SYS_NUM_FM2_DTSEC 8 #define CFG_SYS_NUM_FM2_DTSEC 8
#define CFG_SYS_NUM_FM2_10GEC 1 #define CFG_SYS_NUM_FM2_10GEC 1
#endif #endif
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CFG_SYS_FSL_SRDS_3 #define CFG_SYS_FSL_SRDS_3
#define CFG_SYS_FSL_SRDS_4 #define CFG_SYS_FSL_SRDS_4
#define CFG_SYS_NUM_FMAN 2 #define CFG_SYS_NUM_FMAN 2
@ -110,8 +108,6 @@
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_FM1_CLK 0 #define CFG_SYS_FM1_CLK 0
#define CFG_SYS_FM_MURAM_SIZE 0x60000 #define CFG_SYS_FM_MURAM_SIZE 0x60000
@ -131,7 +127,6 @@
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 5 #define CFG_SYS_NUM_FM1_DTSEC 5
#define CFG_PME_PLAT_CLK_DIV 2 #define CFG_PME_PLAT_CLK_DIV 2
@ -146,7 +141,6 @@
#elif defined(CONFIG_ARCH_T1024) #elif defined(CONFIG_ARCH_T1024)
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 4 #define CFG_SYS_NUM_FM1_DTSEC 4
#define CFG_SYS_NUM_FM1_10GEC 1 #define CFG_SYS_NUM_FM1_10GEC 1
@ -161,11 +155,9 @@
#elif defined(CONFIG_ARCH_T2080) #elif defined(CONFIG_ARCH_T2080)
#define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
#if defined(CONFIG_ARCH_T2080) #if defined(CONFIG_ARCH_T2080)
#define CFG_SYS_NUM_FM1_DTSEC 8 #define CFG_SYS_NUM_FM1_DTSEC 8
#define CFG_SYS_NUM_FM1_10GEC 4 #define CFG_SYS_NUM_FM1_10GEC 4
#define CONFIG_SYS_FSL_SRDS_2
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5