nxp: Finish migration of SYS_FSL_IFC_BANK_COUNT to Kconfig
As this is used on both ARM and PowerPC platforms, this needs to be asked in arch/Kconfig.nxp. Set the PowerPC defaults based on arch/powerpc/include/asm/config_mpc85xx.h and remove the default set in drivers/mtd/nand/raw/fsl_ifc_nand.c Signed-off-by: Tom Rini <trini@konsulko.com>
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5 changed files with 14 additions and 29 deletions
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@ -256,6 +256,20 @@ config SYS_FSL_ESDHC_BE
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config SYS_FSL_IFC_BE
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bool
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
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ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
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ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
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ARCH_T2080 || ARCH_C29X || ARCH_P1010 || ARCH_BSC9131 || \
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ARCH_BSC9132
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default 3 if ARCH_BSC9131 || ARCH_BSC9132
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default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
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ARCH_B4420 || ARCH_P1010
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default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
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ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || \
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ARCH_T1024 || ARCH_T2080 || ARCH_C29X
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config FSL_QIXIS
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bool "Enable QIXIS support"
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depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
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@ -102,10 +102,6 @@ config SYS_FSL_SRDS_2
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config SYS_HAS_SERDES
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bool
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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default 8
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config SYS_FSL_ERRATUM_A008407
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bool
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@ -525,13 +525,6 @@ config SYS_CCI400_OFFSET
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Offset for CCI400 base
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CCI400 base addr = CCSRBAR + CCI400_OFFSET
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
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default 4 if ARCH_LS1043A
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default 4 if ARCH_LS1046A
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default 8 if ARCH_LS2080A || ARCH_LS1088A
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config SYS_FSL_HAS_CCI400
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bool
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@ -16,9 +16,6 @@
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#elif defined(CONFIG_ARCH_P1010)
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
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#elif defined(CONFIG_ARCH_P1021)
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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@ -85,11 +82,6 @@
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#define CFG_SYS_FM_MURAM_SIZE 0x28000
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#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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#elif defined(CONFIG_ARCH_BSC9131)
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
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#elif defined(CONFIG_ARCH_BSC9132)
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
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#elif defined(CONFIG_ARCH_T4240)
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#ifdef CONFIG_ARCH_T4240
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@ -110,7 +102,6 @@
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#define CFG_SYS_FSL_SRDS_4
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#define CFG_SYS_NUM_FMAN 2
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#define CFG_SYS_PME_CLK 0
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CFG_SYS_FM1_CLK 3
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#define CFG_SYS_FM2_CLK 3
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#define CFG_SYS_FM_MURAM_SIZE 0x60000
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@ -123,7 +114,6 @@
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#define CONFIG_SYS_FSL_SRDS_2
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#define CFG_SYS_NUM_FMAN 1
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#define CFG_SYS_FM1_CLK 0
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
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#define CFG_SYS_FM_MURAM_SIZE 0x60000
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#ifdef CONFIG_ARCH_B4860
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@ -146,7 +136,6 @@
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#define CFG_SYS_NUM_FM1_DTSEC 5
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#define CFG_PME_PLAT_CLK_DIV 2
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#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CFG_FM_PLAT_CLK_DIV 1
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#define CFG_SYS_FM1_CLK CFG_FM_PLAT_CLK_DIV
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#define CFG_SYS_FM_MURAM_SIZE 0x30000
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@ -161,7 +150,6 @@
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#define CFG_SYS_NUM_FMAN 1
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#define CFG_SYS_NUM_FM1_DTSEC 4
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#define CFG_SYS_NUM_FM1_10GEC 1
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CFG_SYS_FM1_CLK 0
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#define CFG_QBMAN_CLK_DIV 1
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#define CFG_SYS_FM_MURAM_SIZE 0x30000
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@ -185,13 +173,11 @@
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#define CFG_PME_PLAT_CLK_DIV 1
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#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV
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#define CFG_SYS_FM1_CLK 0
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CFG_SYS_FM_MURAM_SIZE 0x28000
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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#elif defined(CONFIG_ARCH_C29X)
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
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#endif
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@ -20,10 +20,6 @@
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#include <linux/errno.h>
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#include <fsl_ifc.h>
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#ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
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#endif
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#define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT
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#define ERR_BYTE 0xFF /* Value returned for read bytes
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when read failed */
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