13a6e0620f
Use the new INTERNAL_PHY_SDS() helper to describe the SFP ports. With this change the driver now knows that ports 24/26 are driven by serdes 4/5. For the RTL838x devices this is currently only an additional information for the mdio bus. It is not evaluated further because everything is hardcoded. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/18851 Signed-off-by: Robert Marko <robimarko@gmail.com>
145 lines
3 KiB
Text
145 lines
3 KiB
Text
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl838x.dtsi"
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#include "rtl83xx_d-link_dgs-1210_common.dtsi"
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#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
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/ {
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compatible = "d-link,dgs-1210-26", "realtek,rtl838x-soc";
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model = "D-Link DGS-1210-26";
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/* Left SFP slot, port 25 */
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i2c0: i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp0: sfp-p25 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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};
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/* Right SFP slot, port 26 */
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i2c1: i2c-gpio-1 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp1: sfp-p26 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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EXTERNAL_PHY(0)
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EXTERNAL_PHY(1)
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EXTERNAL_PHY(2)
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EXTERNAL_PHY(3)
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EXTERNAL_PHY(4)
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EXTERNAL_PHY(5)
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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EXTERNAL_PHY(16)
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EXTERNAL_PHY(17)
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EXTERNAL_PHY(18)
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EXTERNAL_PHY(19)
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EXTERNAL_PHY(20)
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EXTERNAL_PHY(21)
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EXTERNAL_PHY(22)
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EXTERNAL_PHY(23)
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INTERNAL_PHY_SDS(24, 4)
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INTERNAL_PHY_SDS(26, 5)
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(0, 1, qsgmii)
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SWITCH_PORT(1, 2, qsgmii)
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SWITCH_PORT(2, 3, qsgmii)
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SWITCH_PORT(3, 4, qsgmii)
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SWITCH_PORT(4, 5, qsgmii)
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SWITCH_PORT(5, 6, qsgmii)
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SWITCH_PORT(6, 7, qsgmii)
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SWITCH_PORT(7, 8, qsgmii)
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SWITCH_PORT(8, 9, internal)
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SWITCH_PORT(9, 10, internal)
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SWITCH_PORT(10, 11, internal)
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SWITCH_PORT(11, 12, internal)
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SWITCH_PORT(12, 13, internal)
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SWITCH_PORT(13, 14, internal)
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SWITCH_PORT(14, 15, internal)
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SWITCH_PORT(15, 16, internal)
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SWITCH_PORT(16, 17, qsgmii)
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SWITCH_PORT(17, 18, qsgmii)
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SWITCH_PORT(18, 19, qsgmii)
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SWITCH_PORT(19, 20, qsgmii)
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SWITCH_PORT(20, 21, qsgmii)
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SWITCH_PORT(21, 22, qsgmii)
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SWITCH_PORT(22, 23, qsgmii)
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SWITCH_PORT(23, 24, qsgmii)
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port@24 {
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reg = <24>;
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label = "lan25";
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp0>;
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};
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port@26 {
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reg = <26>;
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label = "lan26";
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp1>;
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};
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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