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Merge branch 'openwrt:master' into master

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This commit is contained in:
Hayzam Sherif 2023-08-10 18:23:43 +05:30 committed by GitHub
commit f6bb9cf4cf
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GPG key ID: 4AEE18F83AFDEB23
139 changed files with 7376 additions and 676 deletions
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6
.github/workflows/kernel.yml vendored
View file

@ -35,6 +35,8 @@ jobs:
packages: read packages: read
actions: write actions: write
secrets: secrets:
s3_access_key: ${{ secrets.GCS_S3_ACCESS_KEY }} ccache_s3_endpoint: ${{ secrets.CCACHE_S3_ENDPOINT }}
s3_secret_key: ${{ secrets.GCS_S3_SECRET_KEY }} ccache_s3_bucket: ${{ secrets.CCACHE_S3_BUCKET }}
ccache_s3_access_key: ${{ secrets.CCACHE_S3_ACCESS_KEY }}
ccache_s3_secret_key: ${{ secrets.CCACHE_S3_SECRET_KEY }}
uses: openwrt/actions-shared-workflows/.github/workflows/kernel.yml@main uses: openwrt/actions-shared-workflows/.github/workflows/kernel.yml@main

6
.github/workflows/packages.yml vendored
View file

@ -35,6 +35,8 @@ jobs:
packages: read packages: read
actions: write actions: write
secrets: secrets:
s3_access_key: ${{ secrets.GCS_S3_ACCESS_KEY }} ccache_s3_endpoint: ${{ secrets.CCACHE_S3_ENDPOINT }}
s3_secret_key: ${{ secrets.GCS_S3_SECRET_KEY }} ccache_s3_bucket: ${{ secrets.CCACHE_S3_BUCKET }}
ccache_s3_access_key: ${{ secrets.CCACHE_S3_ACCESS_KEY }}
ccache_s3_secret_key: ${{ secrets.CCACHE_S3_SECRET_KEY }}
uses: openwrt/actions-shared-workflows/.github/workflows/packages.yml@main uses: openwrt/actions-shared-workflows/.github/workflows/packages.yml@main

4
include/kernel-5.15
View file

@ -1,2 +1,2 @@
LINUX_VERSION-5.15 = .123 LINUX_VERSION-5.15 = .125
LINUX_KERNEL_HASH-5.15.123 = 2de69544a12e6a059163c58fc901c13bcf22e8cac39c66b56f8fbb633399bf93 LINUX_KERNEL_HASH-5.15.125 = 150f3846b76cd23a6135f49cef71372bade5a06e851cb4f8558df8b862d8fec7

4
include/kernel-6.1
View file

@ -1,2 +1,2 @@
LINUX_VERSION-6.1 = .42 LINUX_VERSION-6.1 = .44
LINUX_KERNEL_HASH-6.1.42 = aaf8261b551c8b76b81eab8780b446e88cea4d551ae517ac3a9b2dbdbd381ed3 LINUX_KERNEL_HASH-6.1.44 = 2e51d41fe11d082ae167cee05772bb07ca7f19448d2b46772d8ca2db7673a1a5

18
package/kernel/linux/modules/netdevices.mk
View file

@ -308,6 +308,24 @@ endef
$(eval $(call KernelPackage,phy-marvell)) $(eval $(call KernelPackage,phy-marvell))
define KernelPackage/phy-marvell-10g
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Marvell 10 Gigabit Ethernet PHY driver
KCONFIG:=CONFIG_MARVELL_10G_PHY
DEPENDS:=+kmod-libphy
FILES:=$(LINUX_DIR)/drivers/net/phy/marvell10g.ko
AUTOLOAD:=$(call AutoLoad,18,marvell10g)
endef
define KernelPackage/phy-marvell/description
Supports Marvell 10 Gigabit Ethernet PHYs:
* 88E2110
* 88E2111
* 88x3310
* 88x3340
endef
$(eval $(call KernelPackage,phy-marvell-10g))
define KernelPackage/phy-realtek define KernelPackage/phy-realtek
SUBMENU:=$(NETWORK_DEVICES_MENU) SUBMENU:=$(NETWORK_DEVICES_MENU)

3
package/kernel/linux/modules/netsupport.mk
View file

@ -93,8 +93,7 @@ define KernelPackage/vxlan
+IPV6:kmod-udptunnel6 +IPV6:kmod-udptunnel6
KCONFIG:=CONFIG_VXLAN KCONFIG:=CONFIG_VXLAN
FILES:= \ FILES:= \
$(LINUX_DIR)/drivers/net/vxlan.ko@lt5.18 \ $(LINUX_DIR)/drivers/net/vxlan/vxlan.ko
$(LINUX_DIR)/drivers/net/vxlan/vxlan.ko@ge5.18
AUTOLOAD:=$(call AutoLoad,13,vxlan) AUTOLOAD:=$(call AutoLoad,13,vxlan)
endef endef

13
package/kernel/mac80211/files/lib/netifd/wireless/mac80211.sh
View file

@ -765,7 +765,7 @@ mac80211_prepare_iw_htmode() {
mac80211_add_mesh_params() { mac80211_add_mesh_params() {
for var in $MP_CONFIG_INT $MP_CONFIG_BOOL $MP_CONFIG_STRING; do for var in $MP_CONFIG_INT $MP_CONFIG_BOOL $MP_CONFIG_STRING; do
eval "mp_val=\"\$var\"" eval "mp_val=\"\$$var\""
[ -n "$mp_val" ] && json_add_string "$var" "$mp_val" [ -n "$mp_val" ] && json_add_string "$var" "$mp_val"
done done
} }
@ -1089,14 +1089,18 @@ drv_mac80211_setup() {
json_get_values scan_list scan_list json_get_values scan_list scan_list
json_select .. json_select ..
json_select data && {
json_get_var prev_rxantenna rxantenna
json_get_var prev_txantenna txantenna
json_select ..
}
find_phy || { find_phy || {
echo "Could not find PHY for device '$1'" echo "Could not find PHY for device '$1'"
wireless_set_retry 0 wireless_set_retry 0
return 1 return 1
} }
wireless_set_data phy="$phy"
local wdev local wdev
local cwdev local cwdev
local found local found
@ -1130,6 +1134,9 @@ drv_mac80211_setup() {
[ "$txantenna" = "all" ] && txantenna=0xffffffff [ "$txantenna" = "all" ] && txantenna=0xffffffff
[ "$rxantenna" = "all" ] && rxantenna=0xffffffff [ "$rxantenna" = "all" ] && rxantenna=0xffffffff
[ "$rxantenna" = "$prev_rxantenna" -a "$txantenna" = "$prev_txantenna" ] || mac80211_reset_config "$phy"
wireless_set_data phy="$phy" txantenna="$txantenna" rxantenna="$rxantenna"
iw phy "$phy" set antenna $txantenna $rxantenna >/dev/null 2>&1 iw phy "$phy" set antenna $txantenna $rxantenna >/dev/null 2>&1
iw phy "$phy" set antenna_gain $antenna_gain >/dev/null 2>&1 iw phy "$phy" set antenna_gain $antenna_gain >/dev/null 2>&1
iw phy "$phy" set distance "$distance" >/dev/null 2>&1 iw phy "$phy" set distance "$distance" >/dev/null 2>&1

6
package/libs/openssl/Makefile
View file

@ -8,8 +8,8 @@
include $(TOPDIR)/rules.mk include $(TOPDIR)/rules.mk
PKG_NAME:=openssl PKG_NAME:=openssl
PKG_VERSION:=3.0.9 PKG_VERSION:=3.0.10
PKG_RELEASE:=3 PKG_RELEASE:=1
PKG_BUILD_FLAGS:=no-mips16 gc-sections no-lto PKG_BUILD_FLAGS:=no-mips16 gc-sections no-lto
PKG_BUILD_PARALLEL:=1 PKG_BUILD_PARALLEL:=1
@ -24,7 +24,7 @@ PKG_SOURCE_URL:= \
ftp://ftp.pca.dfn.de/pub/tools/net/openssl/source/ \ ftp://ftp.pca.dfn.de/pub/tools/net/openssl/source/ \
ftp://ftp.pca.dfn.de/pub/tools/net/openssl/source/old/$(PKG_BASE)/ ftp://ftp.pca.dfn.de/pub/tools/net/openssl/source/old/$(PKG_BASE)/
PKG_HASH:=eb1ab04781474360f77c318ab89d8c5a03abc38e63d65a603cabbf1b00a1dc90 PKG_HASH:=1761d4f5b13a1028b9b6f3d4b8e17feb0cedc9370f6afe61d7193d2cdce83323
PKG_LICENSE:=Apache-2.0 PKG_LICENSE:=Apache-2.0
PKG_LICENSE_FILES:=LICENSE PKG_LICENSE_FILES:=LICENSE

2
package/libs/openssl/patches/100-Configure-afalg-support.patch
View file

@ -10,7 +10,7 @@ Signed-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>
--- a/Configure --- a/Configure
+++ b/Configure +++ b/Configure
@@ -1677,7 +1677,9 @@ $config{CFLAGS} = [ map { $_ eq '--ossl- @@ -1674,7 +1674,9 @@ $config{CFLAGS} = [ map { $_ eq '--ossl-
unless ($disabled{afalgeng}) { unless ($disabled{afalgeng}) {
$config{afalgeng}=""; $config{afalgeng}="";

2
package/network/services/hostapd/files/common.uc
View file

@ -34,7 +34,7 @@ function find_reusable_wdev(phyidx)
if (!__phy_is_fullmac(phyidx)) if (!__phy_is_fullmac(phyidx))
return null; return null;
data = nl80211.request( let data = nl80211.request(
nl80211.const.NL80211_CMD_GET_INTERFACE, nl80211.const.NL80211_CMD_GET_INTERFACE,
nl80211.const.NLM_F_DUMP, nl80211.const.NLM_F_DUMP,
{ wiphy: phyidx }); { wiphy: phyidx });

3
package/network/services/hostapd/files/hostapd.uc
View file

@ -117,6 +117,9 @@ function iface_reload_config(phy, config, old_config)
if (is_equal(old_config.bss, config.bss)) if (is_equal(old_config.bss, config.bss))
return true; return true;
if (!old_config.bss || !old_config.bss[0])
return false;
if (config.bss[0].ifname != old_config.bss[0].ifname) if (config.bss[0].ifname != old_config.bss[0].ifname)
return false; return false;

7
package/network/services/hostapd/files/wdev.uc
View file

@ -1,7 +1,7 @@
#!/usr/bin/env ucode #!/usr/bin/env ucode
'use strict'; 'use strict';
import { vlist_new, is_equal, wdev_create, wdev_remove } from "/usr/share/hostap/common.uc"; import { vlist_new, is_equal, wdev_create, wdev_remove } from "/usr/share/hostap/common.uc";
import { readfile, writefile, basename, glob } from "fs"; import { readfile, writefile, basename, readlink, glob } from "fs";
let keep_devices = {}; let keep_devices = {};
let phy = shift(ARGV); let phy = shift(ARGV);
@ -46,7 +46,7 @@ function iface_start(wdev)
push(cmd, key, wdev[key]); push(cmd, key, wdev[key]);
system(cmd); system(cmd);
} else if (wdev.mode == "mesh") { } else if (wdev.mode == "mesh") {
let cmd = [ "iw", "dev", ifname, "mesh", "join", ssid, "freq", wdev.freq, wdev.htmode ]; let cmd = [ "iw", "dev", ifname, "mesh", "join", wdev.ssid, "freq", wdev.freq, wdev.htmode ];
for (let key in [ "beacon-interval", "mcast-rate" ]) for (let key in [ "beacon-interval", "mcast-rate" ])
if (wdev[key]) if (wdev[key])
push(cmd, key, wdev[key]); push(cmd, key, wdev[key]);
@ -106,6 +106,9 @@ function add_existing(phy, config)
if (config[wdev]) if (config[wdev])
continue; continue;
if (basename(readlink(`/sys/class/net/${wdev}/phy80211`)) != phy)
continue;
if (trim(readfile(`/sys/class/net/${wdev}/operstate`)) == "down") if (trim(readfile(`/sys/class/net/${wdev}/operstate`)) == "down")
config[wdev] = {}; config[wdev] = {};
} }

103
package/network/services/hostapd/patches/180-BSS-coloring-fix-CCA-with-multiple-BSS.patch Normal file
View file

@ -0,0 +1,103 @@
From: Felix Fietkau <nbd@nbd.name>
Date: Mon, 7 Aug 2023 21:55:57 +0200
Subject: [PATCH] BSS coloring: fix CCA with multiple BSS
Pass bss->ctx instead of drv->ctx in order to avoid multiple reports for
the first bss. The first report would otherwise clear hapd->cca_color and
subsequent reports would cause the iface bss color to be set to 0.
In order to avoid any issues with cancellations, only overwrite the color
based on hapd->cca_color if it was actually set.
Fixes: 33c4dd26cd11 ("BSS coloring: Handle the collision and CCA events coming from the kernel")
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
--- a/src/ap/drv_callbacks.c
+++ b/src/ap/drv_callbacks.c
@@ -2260,7 +2260,8 @@ void wpa_supplicant_event(void *ctx, enu
case EVENT_CCA_NOTIFY:
wpa_printf(MSG_DEBUG, "CCA finished on on %s",
hapd->conf->iface);
- hapd->iface->conf->he_op.he_bss_color = hapd->cca_color;
+ if (hapd->cca_color)
+ hapd->iface->conf->he_op.he_bss_color = hapd->cca_color;
hostapd_cleanup_cca_params(hapd);
break;
#endif /* CONFIG_IEEE80211AX */
--- a/src/drivers/driver_nl80211_event.c
+++ b/src/drivers/driver_nl80211_event.c
@@ -3653,7 +3653,7 @@ static void nl80211_assoc_comeback(struc
#ifdef CONFIG_IEEE80211AX
-static void nl80211_obss_color_collision(struct wpa_driver_nl80211_data *drv,
+static void nl80211_obss_color_collision(struct i802_bss *bss,
struct nlattr *tb[])
{
union wpa_event_data data;
@@ -3667,37 +3667,37 @@ static void nl80211_obss_color_collision
wpa_printf(MSG_DEBUG, "nl80211: BSS color collision - bitmap %08llx",
(long long unsigned int) data.bss_color_collision.bitmap);
- wpa_supplicant_event(drv->ctx, EVENT_BSS_COLOR_COLLISION, &data);
+ wpa_supplicant_event(bss->ctx, EVENT_BSS_COLOR_COLLISION, &data);
}
static void
-nl80211_color_change_announcement_started(struct wpa_driver_nl80211_data *drv)
+nl80211_color_change_announcement_started(struct i802_bss *bss)
{
union wpa_event_data data = {};
wpa_printf(MSG_DEBUG, "nl80211: CCA started");
- wpa_supplicant_event(drv->ctx, EVENT_CCA_STARTED_NOTIFY, &data);
+ wpa_supplicant_event(bss->ctx, EVENT_CCA_STARTED_NOTIFY, &data);
}
static void
-nl80211_color_change_announcement_aborted(struct wpa_driver_nl80211_data *drv)
+nl80211_color_change_announcement_aborted(struct i802_bss *bss)
{
union wpa_event_data data = {};
wpa_printf(MSG_DEBUG, "nl80211: CCA aborted");
- wpa_supplicant_event(drv->ctx, EVENT_CCA_ABORTED_NOTIFY, &data);
+ wpa_supplicant_event(bss->ctx, EVENT_CCA_ABORTED_NOTIFY, &data);
}
static void
-nl80211_color_change_announcement_completed(struct wpa_driver_nl80211_data *drv)
+nl80211_color_change_announcement_completed(struct i802_bss *bss)
{
union wpa_event_data data = {};
wpa_printf(MSG_DEBUG, "nl80211: CCA completed");
- wpa_supplicant_event(drv->ctx, EVENT_CCA_NOTIFY, &data);
+ wpa_supplicant_event(bss->ctx, EVENT_CCA_NOTIFY, &data);
}
#endif /* CONFIG_IEEE80211AX */
@@ -3957,16 +3957,16 @@ static void do_process_drv_event(struct
break;
#ifdef CONFIG_IEEE80211AX
case NL80211_CMD_OBSS_COLOR_COLLISION:
- nl80211_obss_color_collision(drv, tb);
+ nl80211_obss_color_collision(bss, tb);
break;
case NL80211_CMD_COLOR_CHANGE_STARTED:
- nl80211_color_change_announcement_started(drv);
+ nl80211_color_change_announcement_started(bss);
break;
case NL80211_CMD_COLOR_CHANGE_ABORTED:
- nl80211_color_change_announcement_aborted(drv);
+ nl80211_color_change_announcement_aborted(bss);
break;
case NL80211_CMD_COLOR_CHANGE_COMPLETED:
- nl80211_color_change_announcement_completed(drv);
+ nl80211_color_change_announcement_completed(bss);
break;
#endif /* CONFIG_IEEE80211AX */
default:

2
package/network/services/hostapd/patches/200-multicall.patch
View file

@ -189,7 +189,7 @@
{ {
struct hostapd_data *hapd = ctx; struct hostapd_data *hapd = ctx;
#ifndef CONFIG_NO_STDOUT_DEBUG #ifndef CONFIG_NO_STDOUT_DEBUG
@@ -2271,7 +2271,7 @@ void wpa_supplicant_event(void *ctx, enu @@ -2272,7 +2272,7 @@ void wpa_supplicant_event(void *ctx, enu
} }

2
package/network/utils/xdp-tools/Makefile
View file

@ -94,7 +94,7 @@ MAKE_VARS += \
define Build/Configure define Build/Configure
$(call Build/Configure/Default) $(call Build/Configure/Default)
echo "BPF_CFLAGS += -I$(BPF_HEADERS_DIR)/tools/lib" >> $(PKG_BUILD_DIR)/config.mk echo "BPF_CFLAGS += -I$(BPF_HEADERS_DIR)/tools/lib -fno-stack-protector" >> $(PKG_BUILD_DIR)/config.mk
endef endef
define Build/InstallDev define Build/InstallDev

2
target/linux/airoha/patches-5.15/0001-add-airoha-platform.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm/Kconfig --- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig +++ b/arch/arm/Kconfig
@@ -571,6 +571,18 @@ config ARCH_VIRT @@ -572,6 +572,18 @@ config ARCH_VIRT
select HAVE_ARM_ARCH_TIMER select HAVE_ARM_ARCH_TIMER
select ARCH_SUPPORTS_BIG_ENDIAN select ARCH_SUPPORTS_BIG_ENDIAN

2
target/linux/armsr/patches-6.1/221-armsr-disable_gc_sections_armv7.patch
View file

@ -13,7 +13,7 @@ Signed-off-by: Mathew McBride <matt@traverse.com.au>
--- a/arch/arm/Kconfig --- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig +++ b/arch/arm/Kconfig
@@ -123,7 +123,6 @@ config ARM @@ -124,7 +124,6 @@ config ARM
select HAVE_VIRT_CPU_ACCOUNTING_GEN select HAVE_VIRT_CPU_ACCOUNTING_GEN
select IRQ_FORCED_THREADING select IRQ_FORCED_THREADING
select LOCK_MM_AND_FIND_VMA select LOCK_MM_AND_FIND_VMA

2
target/linux/ath25/patches-5.15/107-ar5312_gpio.patch
View file

@ -202,7 +202,7 @@
+subsys_initcall(ar5312_gpio_init); +subsys_initcall(ar5312_gpio_init);
--- a/arch/mips/Kconfig --- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig +++ b/arch/mips/Kconfig
@@ -231,6 +231,7 @@ config ATH25 @@ -232,6 +232,7 @@ config ATH25
select CEVT_R4K select CEVT_R4K
select CSRC_R4K select CSRC_R4K
select DMA_NONCOHERENT select DMA_NONCOHERENT

2
target/linux/ath79/patches-5.15/0032-MIPS-ath79-sanitize-symbols.patch
View file

@ -15,7 +15,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
--- a/arch/mips/Kconfig --- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig +++ b/arch/mips/Kconfig
@@ -257,6 +257,8 @@ config ATH79 @@ -258,6 +258,8 @@ config ATH79
select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_MIPS16 select SYS_SUPPORTS_MIPS16
select SYS_SUPPORTS_ZBOOT_UART_PROM select SYS_SUPPORTS_ZBOOT_UART_PROM

4
target/linux/ath79/patches-5.15/910-unaligned_access_hacks.patch
View file

@ -654,7 +654,7 @@ SVN-Revision: 35130
return false; return false;
return true; return true;
@@ -750,13 +754,13 @@ static inline void ipv6_addr_set_v4mappe @@ -746,13 +750,13 @@ static inline void ipv6_addr_set_v4mappe
*/ */
static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen) static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen)
{ {
@ -670,7 +670,7 @@ SVN-Revision: 35130
if (xb) if (xb)
return i * 32 + 31 - __fls(ntohl(xb)); return i * 32 + 31 - __fls(ntohl(xb));
} }
@@ -950,17 +954,18 @@ static inline u32 ip6_multipath_hash_fie @@ -946,17 +950,18 @@ static inline u32 ip6_multipath_hash_fie
static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass, static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass,
__be32 flowlabel) __be32 flowlabel)
{ {

2
target/linux/bcm27xx/patches-6.1/950-0327-usb-xhci-workaround-for-bogus-SET_DEQ_PENDING-endpoi.patch
View file

@ -26,7 +26,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
--- a/drivers/usb/host/xhci-ring.c --- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c
@@ -697,9 +697,9 @@ deq_found: @@ -674,9 +674,9 @@ deq_found:
} }
if ((ep->ep_state & SET_DEQ_PENDING)) { if ((ep->ep_state & SET_DEQ_PENDING)) {

14
target/linux/bcm27xx/patches-6.1/950-0359-xhci-quirks-add-link-TRB-quirk-for-VL805.patch
View file

@ -22,17 +22,21 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
--- a/drivers/usb/host/xhci-pci.c --- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c
@@ -296,6 +296,7 @@ static void xhci_pci_quirks(struct devic @@ -293,8 +293,10 @@ static void xhci_pci_quirks(struct devic
if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) { pdev->device == 0x3432)
xhci->quirks |= XHCI_BROKEN_STREAMS;
- if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483)
+ if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
xhci->quirks |= XHCI_LPM_SUPPORT; xhci->quirks |= XHCI_LPM_SUPPORT;
xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
+ xhci->quirks |= XHCI_AVOID_DQ_ON_LINK; + xhci->quirks |= XHCI_AVOID_DQ_ON_LINK;
} + }
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
--- a/drivers/usb/host/xhci-ring.c --- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c
@@ -687,6 +687,15 @@ static int xhci_move_dequeue_past_td(str @@ -664,6 +664,15 @@ static int xhci_move_dequeue_past_td(str
} while (!cycle_found || !td_last_trb_found); } while (!cycle_found || !td_last_trb_found);
deq_found: deq_found:

4
target/linux/bcm27xx/patches-6.1/950-0361-xhci-refactor-out-TRBS_PER_SEGMENT-define-in-runtime.patch
View file

@ -204,7 +204,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
xhci_err(xhci, "Tried to move enqueue past ring segment\n"); xhci_err(xhci, "Tried to move enqueue past ring segment\n");
return; return;
} }
@@ -3123,7 +3126,7 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd @@ -3100,7 +3103,7 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd
* that clears the EHB. * that clears the EHB.
*/ */
while (xhci_handle_event(xhci) > 0) { while (xhci_handle_event(xhci) > 0) {
@ -213,7 +213,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
continue; continue;
xhci_update_erst_dequeue(xhci, event_ring_deq); xhci_update_erst_dequeue(xhci, event_ring_deq);
event_ring_deq = xhci->event_ring->dequeue; event_ring_deq = xhci->event_ring->dequeue;
@@ -3265,7 +3268,8 @@ static int prepare_ring(struct xhci_hcd @@ -3242,7 +3245,8 @@ static int prepare_ring(struct xhci_hcd
} }
} }

4
target/linux/bcm27xx/patches-6.1/950-0362-usb-xhci-add-VLI_TRB_CACHE_BUG-quirk.patch
View file

@ -53,9 +53,9 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
cycle_state, type, max_packet, flags); cycle_state, type, max_packet, flags);
--- a/drivers/usb/host/xhci-pci.c --- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c
@@ -297,6 +297,7 @@ static void xhci_pci_quirks(struct devic @@ -296,6 +296,7 @@ static void xhci_pci_quirks(struct devic
if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
xhci->quirks |= XHCI_LPM_SUPPORT; xhci->quirks |= XHCI_LPM_SUPPORT;
xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
xhci->quirks |= XHCI_AVOID_DQ_ON_LINK; xhci->quirks |= XHCI_AVOID_DQ_ON_LINK;
+ xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG; + xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG;
} }

10
target/linux/bcm27xx/patches-6.1/950-0390-usb-xhci-add-a-quirk-for-Superspeed-bulk-OUT-transfe.patch
View file

@ -26,8 +26,8 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
--- a/drivers/usb/host/xhci-pci.c --- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c
@@ -298,6 +298,7 @@ static void xhci_pci_quirks(struct devic @@ -297,6 +297,7 @@ static void xhci_pci_quirks(struct devic
xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS; xhci->quirks |= XHCI_LPM_SUPPORT;
xhci->quirks |= XHCI_AVOID_DQ_ON_LINK; xhci->quirks |= XHCI_AVOID_DQ_ON_LINK;
xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG; xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG;
+ xhci->quirks |= XHCI_VLI_SS_BULK_OUT_BUG; + xhci->quirks |= XHCI_VLI_SS_BULK_OUT_BUG;
@ -36,7 +36,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
--- a/drivers/usb/host/xhci-ring.c --- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c
@@ -3578,14 +3578,15 @@ int xhci_queue_bulk_tx(struct xhci_hcd * @@ -3555,14 +3555,15 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
unsigned int num_trbs; unsigned int num_trbs;
unsigned int start_cycle, num_sgs = 0; unsigned int start_cycle, num_sgs = 0;
unsigned int enqd_len, block_len, trb_buff_len, full_len; unsigned int enqd_len, block_len, trb_buff_len, full_len;
@ -54,7 +54,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
full_len = urb->transfer_buffer_length; full_len = urb->transfer_buffer_length;
/* If we have scatter/gather list, we use it. */ /* If we have scatter/gather list, we use it. */
if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) { if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
@@ -3622,6 +3623,17 @@ int xhci_queue_bulk_tx(struct xhci_hcd * @@ -3599,6 +3600,17 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
start_cycle = ring->cycle_state; start_cycle = ring->cycle_state;
send_addr = addr; send_addr = addr;
@ -72,7 +72,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
/* Queue the TRBs, even if they are zero-length */ /* Queue the TRBs, even if they are zero-length */
for (enqd_len = 0; first_trb || enqd_len < full_len; for (enqd_len = 0; first_trb || enqd_len < full_len;
enqd_len += trb_buff_len) { enqd_len += trb_buff_len) {
@@ -3634,6 +3646,11 @@ int xhci_queue_bulk_tx(struct xhci_hcd * @@ -3611,6 +3623,11 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
if (enqd_len + trb_buff_len > full_len) if (enqd_len + trb_buff_len > full_len)
trb_buff_len = full_len - enqd_len; trb_buff_len = full_len - enqd_len;

6
target/linux/bcm27xx/patches-6.1/950-0392-usb-xhci-rework-XHCI_VLI_SS_BULK_OUT_BUG-quirk.patch
View file

@ -13,7 +13,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
--- a/drivers/usb/host/xhci-ring.c --- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c
@@ -3578,7 +3578,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd * @@ -3555,7 +3555,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
unsigned int num_trbs; unsigned int num_trbs;
unsigned int start_cycle, num_sgs = 0; unsigned int start_cycle, num_sgs = 0;
unsigned int enqd_len, block_len, trb_buff_len, full_len; unsigned int enqd_len, block_len, trb_buff_len, full_len;
@ -22,7 +22,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
u32 field, length_field, remainder, maxpacket; u32 field, length_field, remainder, maxpacket;
u64 addr, send_addr; u64 addr, send_addr;
@@ -3624,14 +3624,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd * @@ -3601,14 +3601,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
send_addr = addr; send_addr = addr;
if (xhci->quirks & XHCI_VLI_SS_BULK_OUT_BUG && if (xhci->quirks & XHCI_VLI_SS_BULK_OUT_BUG &&
@ -40,7 +40,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
} }
/* Queue the TRBs, even if they are zero-length */ /* Queue the TRBs, even if they are zero-length */
@@ -3646,7 +3641,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd * @@ -3623,7 +3618,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
if (enqd_len + trb_buff_len > full_len) if (enqd_len + trb_buff_len > full_len)
trb_buff_len = full_len - enqd_len; trb_buff_len = full_len - enqd_len;

8
target/linux/bcm27xx/patches-6.1/950-0438-usb-xhci-account-for-num_trbs_free-when-invalidating.patch
View file

@ -31,7 +31,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
--- a/drivers/usb/host/xhci-ring.c --- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c
@@ -1035,11 +1035,13 @@ static int xhci_invalidate_cancelled_tds @@ -1012,11 +1012,13 @@ static int xhci_invalidate_cancelled_tds
td->urb->stream_id, td->urb, td->urb->stream_id, td->urb,
cached_td->urb->stream_id, cached_td->urb); cached_td->urb->stream_id, cached_td->urb);
cached_td = td; cached_td = td;
@ -45,7 +45,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
} }
} }
@@ -1287,10 +1289,7 @@ static void update_ring_for_set_deq_comp @@ -1264,10 +1266,7 @@ static void update_ring_for_set_deq_comp
unsigned int ep_index) unsigned int ep_index)
{ {
union xhci_trb *dequeue_temp; union xhci_trb *dequeue_temp;
@ -56,7 +56,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
dequeue_temp = ep_ring->dequeue; dequeue_temp = ep_ring->dequeue;
/* If we get two back-to-back stalls, and the first stalled transfer /* If we get two back-to-back stalls, and the first stalled transfer
@@ -1305,8 +1304,6 @@ static void update_ring_for_set_deq_comp @@ -1282,8 +1281,6 @@ static void update_ring_for_set_deq_comp
} }
while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
@ -65,7 +65,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
ep_ring->dequeue++; ep_ring->dequeue++;
if (trb_is_link(ep_ring->dequeue)) { if (trb_is_link(ep_ring->dequeue)) {
if (ep_ring->dequeue == if (ep_ring->dequeue ==
@@ -1316,15 +1313,10 @@ static void update_ring_for_set_deq_comp @@ -1293,15 +1290,10 @@ static void update_ring_for_set_deq_comp
ep_ring->dequeue = ep_ring->deq_seg->trbs; ep_ring->dequeue = ep_ring->deq_seg->trbs;
} }
if (ep_ring->dequeue == dequeue_temp) { if (ep_ring->dequeue == dequeue_temp) {

8
target/linux/bcm27xx/patches-6.1/950-0469-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch
View file

@ -30,7 +30,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
--- a/drivers/usb/host/xhci-pci.c --- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c
@@ -299,6 +299,7 @@ static void xhci_pci_quirks(struct devic @@ -298,6 +298,7 @@ static void xhci_pci_quirks(struct devic
xhci->quirks |= XHCI_AVOID_DQ_ON_LINK; xhci->quirks |= XHCI_AVOID_DQ_ON_LINK;
xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG; xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG;
xhci->quirks |= XHCI_VLI_SS_BULK_OUT_BUG; xhci->quirks |= XHCI_VLI_SS_BULK_OUT_BUG;
@ -40,7 +40,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
--- a/drivers/usb/host/xhci-ring.c --- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c
@@ -3555,6 +3555,48 @@ static int xhci_align_td(struct xhci_hcd @@ -3532,6 +3532,48 @@ static int xhci_align_td(struct xhci_hcd
return 1; return 1;
} }
@ -89,7 +89,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
/* This is very similar to what ehci-q.c qtd_fill() does */ /* This is very similar to what ehci-q.c qtd_fill() does */
int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
struct urb *urb, int slot_id, unsigned int ep_index) struct urb *urb, int slot_id, unsigned int ep_index)
@@ -3723,6 +3765,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd * @@ -3700,6 +3742,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
} }
check_trb_math(urb, enqd_len); check_trb_math(urb, enqd_len);
@ -98,7 +98,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
start_cycle, start_trb); start_cycle, start_trb);
return 0; return 0;
@@ -3858,6 +3902,8 @@ int xhci_queue_ctrl_tx(struct xhci_hcd * @@ -3835,6 +3879,8 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
/* Event on completion */ /* Event on completion */
field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);

2
target/linux/bcm27xx/patches-6.1/950-0520-xhci-constrain-XHCI_VLI_HUB_TT_QUIRK-to-old-firmware.patch
View file

@ -41,7 +41,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
{ {
struct pci_dev *pdev = to_pci_dev(dev); struct pci_dev *pdev = to_pci_dev(dev);
@@ -299,7 +311,8 @@ static void xhci_pci_quirks(struct devic @@ -298,7 +310,8 @@ static void xhci_pci_quirks(struct devic
xhci->quirks |= XHCI_AVOID_DQ_ON_LINK; xhci->quirks |= XHCI_AVOID_DQ_ON_LINK;
xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG; xhci->quirks |= XHCI_VLI_TRB_CACHE_BUG;
xhci->quirks |= XHCI_VLI_SS_BULK_OUT_BUG; xhci->quirks |= XHCI_VLI_SS_BULK_OUT_BUG;

2
target/linux/bcm63xx/patches-5.15/322-MIPS-BCM63XX-switch-to-IRQ_DOMAIN.patch
View file

@ -14,7 +14,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
--- a/arch/mips/Kconfig --- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig +++ b/arch/mips/Kconfig
@@ -332,6 +332,9 @@ config BCM63XX @@ -333,6 +333,9 @@ config BCM63XX
select SYNC_R4K select SYNC_R4K
select DMA_NONCOHERENT select DMA_NONCOHERENT
select IRQ_MIPS_CPU select IRQ_MIPS_CPU

2
target/linux/bmips/patches-5.15/202-mips-bmips-tweak-Kconfig-options.patch
View file

@ -13,7 +13,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
--- a/arch/mips/Kconfig --- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig +++ b/arch/mips/Kconfig
@@ -275,25 +275,20 @@ config BMIPS_GENERIC @@ -276,25 +276,20 @@ config BMIPS_GENERIC
select SYNC_R4K select SYNC_R4K
select COMMON_CLK select COMMON_CLK
select BCM6345_L1_IRQ select BCM6345_L1_IRQ

2
target/linux/bmips/patches-5.15/600-mips-bmips-add-pci-support.patch
View file

@ -14,7 +14,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
--- a/arch/mips/Kconfig --- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig +++ b/arch/mips/Kconfig
@@ -275,6 +275,7 @@ config BMIPS_GENERIC @@ -276,6 +276,7 @@ config BMIPS_GENERIC
select SYNC_R4K select SYNC_R4K
select COMMON_CLK select COMMON_CLK
select BCM6345_L1_IRQ select BCM6345_L1_IRQ

4
target/linux/bmips/patches-6.1/202-mips-bmips-tweak-Kconfig-options.patch
View file

@ -13,7 +13,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
--- a/arch/mips/Kconfig --- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig +++ b/arch/mips/Kconfig
@@ -274,19 +274,13 @@ config BMIPS_GENERIC @@ -275,19 +275,13 @@ config BMIPS_GENERIC
select SYNC_R4K select SYNC_R4K
select COMMON_CLK select COMMON_CLK
select BCM6345_L1_IRQ select BCM6345_L1_IRQ
@ -33,7 +33,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
select SWAP_IO_SPACE select SWAP_IO_SPACE
select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
@@ -296,6 +290,7 @@ config BMIPS_GENERIC @@ -297,6 +291,7 @@ config BMIPS_GENERIC
select HAVE_PCI select HAVE_PCI
select PCI_DRIVERS_GENERIC select PCI_DRIVERS_GENERIC
select FW_CFE select FW_CFE

2
target/linux/bmips/patches-6.1/600-mips-bmips-add-pci-support.patch
View file

@ -14,7 +14,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
--- a/arch/mips/Kconfig --- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig +++ b/arch/mips/Kconfig
@@ -288,7 +288,6 @@ config BMIPS_GENERIC @@ -289,7 +289,6 @@ config BMIPS_GENERIC
select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
select HARDIRQS_SW_RESEND select HARDIRQS_SW_RESEND
select HAVE_PCI select HAVE_PCI

4
target/linux/generic/backport-5.15/020-v6.1-02-mm-x86-add-CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG.patch
View file

@ -73,7 +73,7 @@ Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
--- a/arch/Kconfig --- a/arch/Kconfig
+++ b/arch/Kconfig +++ b/arch/Kconfig
@@ -1295,6 +1295,14 @@ config ARCH_HAS_ELFCORE_COMPAT @@ -1298,6 +1298,14 @@ config ARCH_HAS_ELFCORE_COMPAT
config ARCH_HAS_PARANOID_L1D_FLUSH config ARCH_HAS_PARANOID_L1D_FLUSH
bool bool
@ -90,7 +90,7 @@ Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
source "scripts/gcc-plugins/Kconfig" source "scripts/gcc-plugins/Kconfig"
--- a/arch/x86/Kconfig --- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig +++ b/arch/x86/Kconfig
@@ -84,6 +84,7 @@ config X86 @@ -85,6 +85,7 @@ config X86
select ARCH_HAS_PMEM_API if X86_64 select ARCH_HAS_PMEM_API if X86_64
select ARCH_HAS_PTE_DEVMAP if X86_64 select ARCH_HAS_PTE_DEVMAP if X86_64
select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_PTE_SPECIAL

2
target/linux/generic/backport-5.15/020-v6.1-08-mm-multi-gen-LRU-support-page-table-walks.patch
View file

@ -398,7 +398,7 @@ Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
mmdrop(mm); mmdrop(mm);
} }
@@ -2622,6 +2624,13 @@ pid_t kernel_clone(struct kernel_clone_a @@ -2617,6 +2619,13 @@ pid_t kernel_clone(struct kernel_clone_a
get_task_struct(p); get_task_struct(p);
} }

4
target/linux/generic/backport-5.15/050-v5.16-05-mips-bpf-Enable-eBPF-JITs.patch
View file

@ -24,7 +24,7 @@ Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
L: bpf@vger.kernel.org L: bpf@vger.kernel.org
--- a/arch/mips/Kconfig --- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig +++ b/arch/mips/Kconfig
@@ -57,7 +57,6 @@ config MIPS @@ -58,7 +58,6 @@ config MIPS
select HAVE_ARCH_TRACEHOOK select HAVE_ARCH_TRACEHOOK
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
select HAVE_ASM_MODVERSIONS select HAVE_ASM_MODVERSIONS
@ -32,7 +32,7 @@ Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
select HAVE_CONTEXT_TRACKING select HAVE_CONTEXT_TRACKING
select HAVE_TIF_NOHZ select HAVE_TIF_NOHZ
select HAVE_C_RECORDMCOUNT select HAVE_C_RECORDMCOUNT
@@ -65,7 +64,10 @@ config MIPS @@ -66,7 +65,10 @@ config MIPS
select HAVE_DEBUG_STACKOVERFLOW select HAVE_DEBUG_STACKOVERFLOW
select HAVE_DMA_CONTIGUOUS select HAVE_DMA_CONTIGUOUS
select HAVE_DYNAMIC_FTRACE select HAVE_DYNAMIC_FTRACE

2
target/linux/generic/backport-5.15/707-v6.3-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
View file

@ -32,7 +32,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
--- a/MAINTAINERS --- a/MAINTAINERS
+++ b/MAINTAINERS +++ b/MAINTAINERS
@@ -11782,6 +11782,14 @@ L: netdev@vger.kernel.org @@ -11783,6 +11783,14 @@ L: netdev@vger.kernel.org
S: Maintained S: Maintained
F: drivers/net/ethernet/mediatek/ F: drivers/net/ethernet/mediatek/

2
target/linux/generic/backport-5.15/790-v6.4-0011-net-dsa-mt7530-introduce-separate-MDIO-driver.patch
View file

@ -25,7 +25,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
--- a/MAINTAINERS --- a/MAINTAINERS
+++ b/MAINTAINERS +++ b/MAINTAINERS
@@ -11894,6 +11894,7 @@ M: Landen Chao <Landen.Chao@mediatek.com @@ -11895,6 +11895,7 @@ M: Landen Chao <Landen.Chao@mediatek.com
M: DENG Qingfang <dqfext@gmail.com> M: DENG Qingfang <dqfext@gmail.com>
L: netdev@vger.kernel.org L: netdev@vger.kernel.org
S: Maintained S: Maintained

2
target/linux/generic/backport-5.15/790-v6.4-0013-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch
View file

@ -28,7 +28,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
--- a/MAINTAINERS --- a/MAINTAINERS
+++ b/MAINTAINERS +++ b/MAINTAINERS
@@ -11892,9 +11892,11 @@ MEDIATEK SWITCH DRIVER @@ -11893,9 +11893,11 @@ MEDIATEK SWITCH DRIVER
M: Sean Wang <sean.wang@mediatek.com> M: Sean Wang <sean.wang@mediatek.com>
M: Landen Chao <Landen.Chao@mediatek.com> M: Landen Chao <Landen.Chao@mediatek.com>
M: DENG Qingfang <dqfext@gmail.com> M: DENG Qingfang <dqfext@gmail.com>

2
target/linux/generic/backport-5.15/791-v6.2-01-net-phy-Add-driver-for-Motorcomm-yt8521-gigabit-ethernet.patch
View file

@ -21,7 +21,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
--- a/MAINTAINERS --- a/MAINTAINERS
+++ b/MAINTAINERS +++ b/MAINTAINERS
@@ -12693,6 +12693,7 @@ F: include/uapi/linux/meye.h @@ -12694,6 +12694,7 @@ F: include/uapi/linux/meye.h
MOTORCOMM PHY DRIVER MOTORCOMM PHY DRIVER
M: Peter Geis <pgwipeout@gmail.com> M: Peter Geis <pgwipeout@gmail.com>

2
target/linux/generic/backport-5.15/804-v5.18-0009-nvmem-Add-driver-for-OCOTP-in-Sunplus-SP7021.patch
View file

@ -19,7 +19,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
--- a/MAINTAINERS --- a/MAINTAINERS
+++ b/MAINTAINERS +++ b/MAINTAINERS
@@ -17958,6 +17958,11 @@ L: netdev@vger.kernel.org @@ -17959,6 +17959,11 @@ L: netdev@vger.kernel.org
S: Maintained S: Maintained
F: drivers/net/ethernet/dlink/sundance.c F: drivers/net/ethernet/dlink/sundance.c

2
target/linux/generic/backport-5.15/806-v6.0-0001-nvmem-microchip-otpc-add-support.patch
View file

@ -57,7 +57,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
--- a/MAINTAINERS --- a/MAINTAINERS
+++ b/MAINTAINERS +++ b/MAINTAINERS
@@ -12357,6 +12357,14 @@ S: Supported @@ -12358,6 +12358,14 @@ S: Supported
F: Documentation/devicetree/bindings/mtd/atmel-nand.txt F: Documentation/devicetree/bindings/mtd/atmel-nand.txt
F: drivers/mtd/nand/raw/atmel/* F: drivers/mtd/nand/raw/atmel/*

1
target/linux/generic/config-6.1
View file

@ -181,6 +181,7 @@ CONFIG_ALLOW_DEV_COREDUMP=y
# CONFIG_AMD_XGBE_HAVE_ECC is not set # CONFIG_AMD_XGBE_HAVE_ECC is not set
# CONFIG_AMIGA_PARTITION is not set # CONFIG_AMIGA_PARTITION is not set
# CONFIG_AMILO_RFKILL is not set # CONFIG_AMILO_RFKILL is not set
# CONFIG_AMPERE_ERRATUM_AC03_CPU_38 is not set
# CONFIG_AMT is not set # CONFIG_AMT is not set
# CONFIG_ANDROID is not set # CONFIG_ANDROID is not set
# CONFIG_ANDROID_BINDER_IPC is not set # CONFIG_ANDROID_BINDER_IPC is not set

2
target/linux/generic/hack-5.15/220-arm-gc_sections.patch
View file

@ -12,7 +12,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
--- ---
--- a/arch/arm/Kconfig --- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig +++ b/arch/arm/Kconfig
@@ -117,6 +117,7 @@ config ARM @@ -118,6 +118,7 @@ config ARM
select HAVE_UID16 select HAVE_UID16
select HAVE_VIRT_CPU_ACCOUNTING_GEN select HAVE_VIRT_CPU_ACCOUNTING_GEN
select IRQ_FORCED_THREADING select IRQ_FORCED_THREADING

2
target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch
View file

@ -29,7 +29,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
#define QUECTEL_VENDOR_ID 0x2c7c #define QUECTEL_VENDOR_ID 0x2c7c
/* These Quectel products use Quectel's vendor ID */ /* These Quectel products use Quectel's vendor ID */
@@ -1177,6 +1179,11 @@ static const struct usb_device_id option @@ -1179,6 +1181,11 @@ static const struct usb_device_id option
.driver_info = ZLP }, .driver_info = ZLP },
{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96), { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
.driver_info = RSVD(4) }, .driver_info = RSVD(4) },

2
target/linux/generic/hack-6.1/220-arm-gc_sections.patch
View file

@ -12,7 +12,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
--- ---
--- a/arch/arm/Kconfig --- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig +++ b/arch/arm/Kconfig
@@ -123,6 +123,7 @@ config ARM @@ -124,6 +124,7 @@ config ARM
select HAVE_VIRT_CPU_ACCOUNTING_GEN select HAVE_VIRT_CPU_ACCOUNTING_GEN
select IRQ_FORCED_THREADING select IRQ_FORCED_THREADING
select LOCK_MM_AND_FIND_VMA select LOCK_MM_AND_FIND_VMA

2
target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch
View file

@ -29,7 +29,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
#define QUECTEL_VENDOR_ID 0x2c7c #define QUECTEL_VENDOR_ID 0x2c7c
/* These Quectel products use Quectel's vendor ID */ /* These Quectel products use Quectel's vendor ID */
@@ -1177,6 +1179,11 @@ static const struct usb_device_id option @@ -1179,6 +1181,11 @@ static const struct usb_device_id option
.driver_info = ZLP }, .driver_info = ZLP },
{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96), { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
.driver_info = RSVD(4) }, .driver_info = RSVD(4) },

4
target/linux/generic/pending-5.15/300-mips_expose_boot_raw.patch
View file

@ -9,7 +9,7 @@ Acked-by: Rob Landley <rob@landley.net>
--- ---
--- a/arch/mips/Kconfig --- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig +++ b/arch/mips/Kconfig
@@ -1101,9 +1101,6 @@ config FW_ARC @@ -1102,9 +1102,6 @@ config FW_ARC
config ARCH_MAY_HAVE_PC_FDC config ARCH_MAY_HAVE_PC_FDC
bool bool
@ -19,7 +19,7 @@ Acked-by: Rob Landley <rob@landley.net>
config CEVT_BCM1480 config CEVT_BCM1480
bool bool
@@ -3183,6 +3180,18 @@ choice @@ -3184,6 +3181,18 @@ choice
bool "Extend builtin kernel arguments with bootloader arguments" bool "Extend builtin kernel arguments with bootloader arguments"
endchoice endchoice

4
target/linux/generic/pending-5.15/351-irqchip-bcm-6345-l1-request-memory-region.patch
View file

@ -91,7 +91,7 @@ Acked-by: Florian Fainelli <f.fainelli@gmail.com>
--- a/drivers/irqchip/irq-bcm6345-l1.c --- a/drivers/irqchip/irq-bcm6345-l1.c
+++ b/drivers/irqchip/irq-bcm6345-l1.c +++ b/drivers/irqchip/irq-bcm6345-l1.c
@@ -261,6 +261,9 @@ static int __init bcm6345_l1_init_one(st @@ -257,6 +257,9 @@ static int __init bcm6345_l1_init_one(st
if (!cpu->map_base) if (!cpu->map_base)
return -ENOMEM; return -ENOMEM;
@ -101,7 +101,7 @@ Acked-by: Florian Fainelli <f.fainelli@gmail.com>
for (i = 0; i < n_words; i++) { for (i = 0; i < n_words; i++) {
cpu->enable_cache[i] = 0; cpu->enable_cache[i] = 0;
__raw_writel(0, cpu->map_base + reg_enable(intc, i)); __raw_writel(0, cpu->map_base + reg_enable(intc, i));
@@ -339,8 +342,7 @@ static int __init bcm6345_l1_of_init(str @@ -335,8 +338,7 @@ static int __init bcm6345_l1_of_init(str
for_each_cpu(idx, &intc->cpumask) { for_each_cpu(idx, &intc->cpumask) {
struct bcm6345_l1_cpu *cpu = intc->cpus[idx]; struct bcm6345_l1_cpu *cpu = intc->cpus[idx];

4
target/linux/generic/pending-5.15/920-mangle_bootargs.patch
View file

@ -31,7 +31,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
help help
--- a/init/main.c --- a/init/main.c
+++ b/init/main.c +++ b/init/main.c
@@ -616,6 +616,29 @@ static inline void setup_nr_cpu_ids(void @@ -614,6 +614,29 @@ static inline void setup_nr_cpu_ids(void
static inline void smp_prepare_cpus(unsigned int maxcpus) { } static inline void smp_prepare_cpus(unsigned int maxcpus) { }
#endif #endif
@ -61,7 +61,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
/* /*
* We need to store the untouched command line for future reference. * We need to store the untouched command line for future reference.
* We also need to store the touched command line since the parameter * We also need to store the touched command line since the parameter
@@ -956,6 +979,7 @@ asmlinkage __visible void __init __no_sa @@ -953,6 +976,7 @@ asmlinkage __visible void __init __no_sa
pr_notice("%s", linux_banner); pr_notice("%s", linux_banner);
early_security_init(); early_security_init();
setup_arch(&command_line); setup_arch(&command_line);

4
target/linux/generic/pending-6.1/300-mips_expose_boot_raw.patch
View file

@ -9,7 +9,7 @@ Acked-by: Rob Landley <rob@landley.net>
--- ---
--- a/arch/mips/Kconfig --- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig +++ b/arch/mips/Kconfig
@@ -1034,9 +1034,6 @@ config FW_ARC @@ -1035,9 +1035,6 @@ config FW_ARC
config ARCH_MAY_HAVE_PC_FDC config ARCH_MAY_HAVE_PC_FDC
bool bool
@ -19,7 +19,7 @@ Acked-by: Rob Landley <rob@landley.net>
config CEVT_BCM1480 config CEVT_BCM1480
bool bool
@@ -3091,6 +3088,18 @@ choice @@ -3092,6 +3089,18 @@ choice
bool "Extend builtin kernel arguments with bootloader arguments" bool "Extend builtin kernel arguments with bootloader arguments"
endchoice endchoice

4
target/linux/generic/pending-6.1/351-irqchip-bcm-6345-l1-request-memory-region.patch
View file

@ -91,7 +91,7 @@ Acked-by: Florian Fainelli <f.fainelli@gmail.com>
--- a/drivers/irqchip/irq-bcm6345-l1.c --- a/drivers/irqchip/irq-bcm6345-l1.c
+++ b/drivers/irqchip/irq-bcm6345-l1.c +++ b/drivers/irqchip/irq-bcm6345-l1.c
@@ -257,6 +257,9 @@ static int __init bcm6345_l1_init_one(st @@ -253,6 +253,9 @@ static int __init bcm6345_l1_init_one(st
if (!cpu->map_base) if (!cpu->map_base)
return -ENOMEM; return -ENOMEM;
@ -101,7 +101,7 @@ Acked-by: Florian Fainelli <f.fainelli@gmail.com>
for (i = 0; i < n_words; i++) { for (i = 0; i < n_words; i++) {
cpu->enable_cache[i] = 0; cpu->enable_cache[i] = 0;
__raw_writel(0, cpu->map_base + reg_enable(intc, i)); __raw_writel(0, cpu->map_base + reg_enable(intc, i));
@@ -335,8 +338,7 @@ static int __init bcm6345_l1_of_init(str @@ -331,8 +334,7 @@ static int __init bcm6345_l1_of_init(str
for_each_cpu(idx, &intc->cpumask) { for_each_cpu(idx, &intc->cpumask) {
struct bcm6345_l1_cpu *cpu = intc->cpus[idx]; struct bcm6345_l1_cpu *cpu = intc->cpus[idx];

4
target/linux/generic/pending-6.1/920-mangle_bootargs.patch
View file

@ -31,7 +31,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
help help
--- a/init/main.c --- a/init/main.c
+++ b/init/main.c +++ b/init/main.c
@@ -609,6 +609,29 @@ static inline void setup_nr_cpu_ids(void @@ -607,6 +607,29 @@ static inline void setup_nr_cpu_ids(void
static inline void smp_prepare_cpus(unsigned int maxcpus) { } static inline void smp_prepare_cpus(unsigned int maxcpus) { }
#endif #endif
@ -61,7 +61,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
/* /*
* We need to store the untouched command line for future reference. * We need to store the untouched command line for future reference.
* We also need to store the touched command line since the parameter * We also need to store the touched command line since the parameter
@@ -957,6 +980,7 @@ asmlinkage __visible void __init __no_sa @@ -954,6 +977,7 @@ asmlinkage __visible void __init __no_sa
pr_notice("%s", linux_banner); pr_notice("%s", linux_banner);
early_security_init(); early_security_init();
setup_arch(&command_line); setup_arch(&command_line);

4
target/linux/ipq806x/patches-6.1/0060-ARM-mach-qcom-fix-support-for-ipq806x.patch
View file

@ -21,7 +21,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
--- a/arch/arm/Kconfig --- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig +++ b/arch/arm/Kconfig
@@ -284,6 +284,7 @@ config PHYS_OFFSET @@ -285,6 +285,7 @@ config PHYS_OFFSET
default 0x30000000 if ARCH_S3C24XX default 0x30000000 if ARCH_S3C24XX
default 0xa0000000 if ARCH_IOP32X || ARCH_PXA default 0xa0000000 if ARCH_IOP32X || ARCH_PXA
default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
@ -29,7 +29,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
default 0 default 0
help help
Please provide the physical address corresponding to the Please provide the physical address corresponding to the
@@ -1703,7 +1704,7 @@ config CRASH_DUMP @@ -1704,7 +1705,7 @@ config CRASH_DUMP
config AUTO_ZRELADDR config AUTO_ZRELADDR
bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM

6
target/linux/ipq806x/patches-6.1/0067-generic-Mangle-bootloader-s-kernel-arguments.patch
View file

@ -22,7 +22,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
--- a/arch/arm/Kconfig --- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig +++ b/arch/arm/Kconfig
@@ -1587,6 +1587,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN @@ -1588,6 +1588,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
The command-line arguments provided by the boot loader will be The command-line arguments provided by the boot loader will be
appended to the the device tree bootargs property. appended to the the device tree bootargs property.
@ -248,7 +248,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
} }
--- a/init/main.c --- a/init/main.c
+++ b/init/main.c +++ b/init/main.c
@@ -114,6 +114,10 @@ @@ -112,6 +112,10 @@
#include <kunit/test.h> #include <kunit/test.h>
@ -259,7 +259,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
static int kernel_init(void *); static int kernel_init(void *);
extern void init_IRQ(void); extern void init_IRQ(void);
@@ -994,6 +998,18 @@ asmlinkage __visible void __init __no_sa @@ -991,6 +995,18 @@ asmlinkage __visible void __init __no_sa
pr_notice("Kernel command line: %s\n", saved_command_line); pr_notice("Kernel command line: %s\n", saved_command_line);
/* parameters may set static keys */ /* parameters may set static keys */
jump_label_init(); jump_label_init();

2
target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm/Kconfig --- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig +++ b/arch/arm/Kconfig
@@ -1600,6 +1600,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL @@ -1601,6 +1601,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL
endchoice endchoice

2
target/linux/lantiq/patches-5.15/0152-lantiq-VPE.patch
View file

@ -15,7 +15,7 @@ Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
--- a/arch/mips/Kconfig --- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig +++ b/arch/mips/Kconfig
@@ -2430,6 +2430,12 @@ config MIPS_VPE_LOADER @@ -2431,6 +2431,12 @@ config MIPS_VPE_LOADER
Includes a loader for loading an elf relocatable object Includes a loader for loading an elf relocatable object
onto another VPE and running it. onto another VPE and running it.

2
target/linux/layerscape/patches-5.15/701-staging-add-fsl_ppfe-driver.patch
View file

@ -854,7 +854,7 @@ Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
+}; +};
--- a/MAINTAINERS --- a/MAINTAINERS
+++ b/MAINTAINERS +++ b/MAINTAINERS
@@ -7519,6 +7519,14 @@ F: drivers/ptp/ptp_qoriq.c @@ -7520,6 +7520,14 @@ F: drivers/ptp/ptp_qoriq.c
F: drivers/ptp/ptp_qoriq_debugfs.c F: drivers/ptp/ptp_qoriq_debugfs.c
F: include/linux/fsl/ptp_qoriq.h F: include/linux/fsl/ptp_qoriq.h

503
target/linux/mediatek/dts/mt7986a-acer-predator-w6.dts Normal file
View file

@ -0,0 +1,503 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "mt7986a.dtsi"
/ {
model = "Acer Predator W6";
compatible = "acer,predator-w6", "mediatek,mt7986a";
aliases {
serial0 = &uart0;
led-boot = &led_status;
led-failsafe = &led_status;
led-running = &led_status;
led-upgrade = &led_status;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs = "dm-mod.create=\"dm-verity,,,ro,0 31544 verity 1 PARTLABEL=rootfs PARTLABEL=rootfs 4096 4096 3943 3944 sha256 2f969fa9e9e4e20b37746f22633e85b178f5db7c143e11f92733a704299cc933 2dd56e34b15c6c84573cf26c4392028421061d2c808975217b45e9a5b49d2087\" rootfstype=squashfs,ext4 rootwait root=/dev/mmcblk0p6 fstools_ignore_partname=1";
};
memory {
reg = <0 0x40000000 0 0x20000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
gpio-keys {
compatible = "gpio-keys";
factory {
label = "factory";
linux,code = <KEY_RESTART>;
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led_status: led@0 {
label = "ant0:red";
gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@1 {
label = "ant0:green";
gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@2 {
label = "ant0:blue";
gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@3 {
label = "ant1:red";
gpios = <&pio 35 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@4 {
label = "ant1:green";
gpios = <&pio 34 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@5 {
label = "ant1:blue";
gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@6 {
label = "ant2:red";
gpios = <&pio 38 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@7 {
label = "ant2:green";
gpios = <&pio 37 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@8 {
label = "ant2:blue";
gpios = <&pio 26 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@9 {
label = "ant3:red";
gpios = <&pio 25 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@10 {
label = "ant3:green";
gpios = <&pio 24 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@11 {
label = "ant3:blue";
gpios = <&pio 23 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@12 {
label = "ant4:red";
gpios = <&pio 28 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@13 {
label = "ant4:green";
gpios = <&pio 27 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@14 {
label = "ant4:blue";
gpios = <&pio 32 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@15 {
label = "ant5:red";
gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@16 {
label = "ant5:green";
gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@17 {
label = "ant5:blue";
gpios = <&pio 43 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
};
&eth {
status = "okay";
gmac0: mac@0 {
/* LAN */
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
/* WAN */
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
phy-handle = <&phy6>;
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
};
};
&mdio {
phy6: phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <6>;
reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
/* LED0: nc ; LED1: nc ; LED2: Amber ; LED3: Green */
mxl,led-config = <0x0 0x0 0x370 0x80>;
};
switch: switch@0 {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
};
};
&pio {
mmc0_pins_default: mmc0-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_pereset";
};
};
wf_2g_5g_pins: wf_2g_5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf-dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "game";
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy@0 {
reg = <0>;
mediatek,led-config = <
0x21 0x8009 /* BASIC_CTRL */
0x22 0x0c00 /* ON_DURATION */
0x23 0x1400 /* BLINK_DURATION */
0x24 0xc001 /* LED0_ON_CTRL */
0x25 0x0000 /* LED0_BLINK_CTRL */
0x26 0xc007 /* LED1_ON_CTRL */
0x27 0x003f /* LED1_BLINK_CTRL */
>;
};
phy@1 {
reg = <1>;
mediatek,led-config = <
0x21 0x8009 /* BASIC_CTRL */
0x22 0x0c00 /* ON_DURATION */
0x23 0x1400 /* BLINK_DURATION */
0x24 0xc001 /* LED0_ON_CTRL */
0x25 0x0000 /* LED0_BLINK_CTRL */
0x26 0xc007 /* LED1_ON_CTRL */
0x27 0x003f /* LED1_BLINK_CTRL */
>;
};
phy@2 {
reg = <2>;
mediatek,led-config = <
0x21 0x8009 /* BASIC_CTRL */
0x22 0x0c00 /* ON_DURATION */
0x23 0x1400 /* BLINK_DURATION */
0x24 0xc001 /* LED0_ON_CTRL */
0x25 0x0000 /* LED0_BLINK_CTRL */
0x26 0xc007 /* LED1_ON_CTRL */
0x27 0x003f /* LED1_BLINK_CTRL */
>;
};
phy@3 {
reg = <3>;
mediatek,led-config = <
0x21 0x8009 /* BASIC_CTRL */
0x22 0x0c00 /* ON_DURATION */
0x23 0x1400 /* BLINK_DURATION */
0x24 0xc001 /* LED0_ON_CTRL */
0x25 0x0000 /* LED0_BLINK_CTRL */
0x26 0xc007 /* LED1_ON_CTRL */
0x27 0x003f /* LED1_BLINK_CTRL */
>;
};
};
};
&wifi {
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
};
&trng {
status = "okay";
};
&watchdog {
status = "okay";
};
&crypto {
status = "okay";
};
&uart0 {
status = "okay";
};
&ssusb {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
status = "okay";
};
&usb_phy {
status = "okay";
};
&mmc0 {
status = "okay";
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <0x08>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x14014>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
no-sd;
no-sdio;
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
status = "okay";
};
&pcie_phy {
status = "okay";
};

143
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts
View file

@ -7,6 +7,7 @@
/dts-v1/; /dts-v1/;
#include "mt7988a-rfb-spim-nand.dtsi" #include "mt7988a-rfb-spim-nand.dtsi"
#include <dt-bindings/pinctrl/mt65xx.h> #include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/leds/common.h>
/ { / {
model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
@ -29,39 +30,27 @@
pinctrl-0 = <&mdio0_pins>; pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
status = "okay"; status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "internal";
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
}; };
gmac1: mac@1 { &gmac0 {
compatible = "mediatek,eth-mac"; status = "okay";
reg = <1>; };
&gmac1 {
status = "okay";
phy-mode = "internal"; phy-mode = "internal";
phy-connection-type = "internal"; phy-connection-type = "internal";
phy = <&phy15>; phy = <&int_2p5g_phy>;
}; };
gmac2: mac@2 { &gmac2 {
compatible = "mediatek,eth-mac"; status = "okay";
reg = <2>; phy-mode = "usxgmii";
phy-mode = "10gbase-kr"; phy-connection-type = "usxgmii";
phy-connection-type = "10gbase-kr";
phy = <&phy8>; phy = <&phy8>;
}; };
mdio0: mdio-bus { &mdio_bus {
#address-cells = <1>;
#size-cells = <0>;
/* external Aquantia AQR113C */ /* external Aquantia AQR113C */
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
@ -93,109 +82,53 @@
compatible = "ethernet-phy-ieee802.3-c45"; compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x"; phy-mode = "2500base-x";
}; };
};
/* internal 2.5G PHY */ &int_2p5g_phy {
phy15: ethernet-phy@15 {
reg = <15>;
pinctrl-names = "i2p5gbe-led"; pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>; pinctrl-0 = <&i2p5gbe_led0_pins>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "internal";
};
};
}; };
&switch { &switch {
status = "okay"; status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
phy-mode = "internal";
phy-handle = <&gsw_phy0>;
}; };
port@1 { &gsw_phy0 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&gsw_phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&gsw_phy2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&gsw_phy3>;
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "internal";
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
mediatek,pio = <&pio>;
gsw_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id03a2.9481";
reg = <0>;
phy-mode = "internal";
pinctrl-names = "gbe-led"; pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe0_led0_pins>; pinctrl-0 = <&gbe0_led0_pins>;
nvmem-cells = <&phy_calibration_p0>;
nvmem-cell-names = "phy-cal-data";
}; };
gsw_phy1: ethernet-phy@1 { &gsw_phy0_led0 {
compatible = "ethernet-phy-id03a2.9481"; status = "okay";
reg = <1>; color = <LED_COLOR_ID_GREEN>;
phy-mode = "internal"; };
&gsw_phy1 {
pinctrl-names = "gbe-led"; pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe1_led0_pins>; pinctrl-0 = <&gbe1_led0_pins>;
nvmem-cells = <&phy_calibration_p1>;
nvmem-cell-names = "phy-cal-data";
}; };
gsw_phy2: ethernet-phy@2 { &gsw_phy1_led0 {
compatible = "ethernet-phy-id03a2.9481"; status = "okay";
reg = <2>; color = <LED_COLOR_ID_GREEN>;
phy-mode = "internal"; };
&gsw_phy2 {
pinctrl-names = "gbe-led"; pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe2_led0_pins>; pinctrl-0 = <&gbe2_led0_pins>;
nvmem-cells = <&phy_calibration_p2>;
nvmem-cell-names = "phy-cal-data";
}; };
gsw_phy3: ethernet-phy@3 { &gsw_phy2_led0 {
compatible = "ethernet-phy-id03a2.9481"; status = "okay";
reg = <3>; color = <LED_COLOR_ID_GREEN>;
phy-mode = "internal"; };
&gsw_phy3 {
pinctrl-names = "gbe-led"; pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe3_led0_pins>; pinctrl-0 = <&gbe3_led0_pins>;
nvmem-cells = <&phy_calibration_p3>;
nvmem-cell-names = "phy-cal-data";
};
}; };
&gsw_phy3_led0 {
status = "okay";
color = <LED_COLOR_ID_GREEN>;
}; };

321
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
View file

@ -4,12 +4,13 @@
* Author: Sam.Shih <sam.shih@mediatek.com> * Author: Sam.Shih <sam.shih@mediatek.com>
*/ */
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/ti-syscon.h>
#include <dt-bindings/clock/mediatek,mt7988-clk.h> #include <dt-bindings/clock/mediatek,mt7988-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt65xx.h> #include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/reset/ti-syscon.h>
#include <dt-bindings/thermal/thermal.h> #include <dt-bindings/thermal/thermal.h>
/ { / {
@ -144,9 +145,9 @@
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */ /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
secmon_reserved: secmon@43000000 { secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>; reg = <0 0x43000000 0 0x50000>;
no-map; no-map;
}; };
}; };
@ -228,7 +229,7 @@
"iocfg_lb_base", "iocfg_tl_base", "eint"; "iocfg_lb_base", "iocfg_tl_base", "eint";
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-ranges = <&pio 0 0 83>; gpio-ranges = <&pio 0 0 84>;
interrupt-controller; interrupt-controller;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
@ -260,47 +261,131 @@
}; };
}; };
i2c2_pins: i2c2-pins-g0 { i2c1_sfp_pins: i2c1-sfp-pins-g0 {
mux {
function = "i2c";
groups = "i2c1_sfp";
};
};
i2c2_pins: i2c2-pins {
mux {
function = "i2c";
groups = "i2c2";
};
};
i2c2_0_pins: i2c2-pins-g0 {
mux {
function = "i2c";
groups = "i2c2_0";
};
};
i2c2_1_pins: i2c2-pins-g1 {
mux { mux {
function = "i2c"; function = "i2c";
groups = "i2c2_1"; groups = "i2c2_1";
}; };
}; };
gbe0_led0_pins: gbe0-pins { gbe0_led0_pins: gbe0-led0-pins {
mux { mux {
function = "led"; function = "led";
groups = "gbe0_led0"; groups = "gbe0_led0";
}; };
}; };
gbe1_led0_pins: gbe1-pins { gbe1_led0_pins: gbe1-led0-pins {
mux { mux {
function = "led"; function = "led";
groups = "gbe1_led0"; groups = "gbe1_led0";
}; };
}; };
gbe2_led0_pins: gbe2-pins { gbe2_led0_pins: gbe2-led0-pins {
mux { mux {
function = "led"; function = "led";
groups = "gbe2_led0"; groups = "gbe2_led0";
}; };
}; };
gbe3_led0_pins: gbe3-pins { gbe3_led0_pins: gbe3-led0-pins {
mux { mux {
function = "led"; function = "led";
groups = "gbe3_led0"; groups = "gbe3_led0";
}; };
}; };
i2p5gbe_led0_pins: 2p5gbe-pins { gbe0_led1_pins: gbe0-led1-pins {
mux {
function = "led";
groups = "gbe0_led1";
};
};
gbe1_led1_pins: gbe1-led1-pins {
mux {
function = "led";
groups = "gbe1_led1";
};
};
gbe2_led1_pins: gbe2-led1-pins {
mux {
function = "led";
groups = "gbe2_led1";
};
};
gbe3_led1_pins: gbe3-led1-pins {
mux {
function = "led";
groups = "gbe3_led1";
};
};
i2p5gbe_led0_pins: 2p5gbe-led0-pins {
mux { mux {
function = "led"; function = "led";
groups = "2p5gbe_led0"; groups = "2p5gbe_led0";
}; };
}; };
i2p5gbe_led1_pins: 2p5gbe-led1-pins {
mux {
function = "led";
groups = "2p5gbe_led1";
};
};
mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
mux {
function = "flash";
groups = "emmc_45";
};
};
mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
mux {
function = "flash";
groups = "emmc_51";
};
};
mmc0_pins_sdcard: mmc0-pins-sdcard {
mux {
function = "flash";
groups = "sdcard";
};
};
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0";
};
};
}; };
sgmiisys0: syscon@10060000 { sgmiisys0: syscon@10060000 {
@ -380,6 +465,8 @@
<&infracfg CLK_INFRA_MUX_UART0_SEL>; <&infracfg CLK_INFRA_MUX_UART0_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
<&topckgen CLK_TOP_UART_SEL>; <&topckgen CLK_TOP_UART_SEL>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "disabled"; status = "disabled";
}; };
@ -645,6 +732,29 @@
status = "disabled"; status = "disabled";
}; };
mmc0: mmc@11230000 {
compatible = "mediatek,mt7986-mmc",
"mediatek,mt7981-mmc";
reg = <0 0x11230000 0 0x1000>,
<0 0x11D60000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_MSDC400>,
<&infracfg CLK_INFRA_MSDC2_HCK>,
<&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
<&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
<&topckgen CLK_TOP_EMMC_400M_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
<&apmixedsys CLK_APMIXED_MSDCPLL>;
clock-names = "source",
"hclk",
"axi_cg",
"ahb_cg";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
tphy: tphy@11c50000 { tphy: tphy@11c50000 {
compatible = "mediatek,mt7988", compatible = "mediatek,mt7988",
"mediatek,generic-tphy-v2"; "mediatek,generic-tphy-v2";
@ -747,6 +857,157 @@
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ethrst 0>; resets = <&ethrst 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
phy-mode = "internal";
phy-handle = <&gsw_phy0>;
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&gsw_phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&gsw_phy2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&gsw_phy3>;
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "internal";
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
mediatek,pio = <&pio>;
gsw_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id03a2.9481";
reg = <0>;
phy-mode = "internal";
nvmem-cells = <&phy_calibration_p0>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy0_led0: gsw-phy0-led0@0 {
reg = <0>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
gsw_phy0_led1: gsw-phy0-led1@1 {
reg = <1>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
};
};
gsw_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id03a2.9481";
reg = <1>;
phy-mode = "internal";
nvmem-cells = <&phy_calibration_p1>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy1_led0: gsw-phy1-led0@0 {
reg = <0>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
gsw_phy1_led1: gsw-phy1-led1@1 {
reg = <1>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
};
};
gsw_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-id03a2.9481";
reg = <2>;
phy-mode = "internal";
nvmem-cells = <&phy_calibration_p2>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy2_led0: gsw-phy2-led0@0 {
reg = <0>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
gsw_phy2_led1: gsw-phy2-led1@1 {
reg = <1>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
};
};
gsw_phy3: ethernet-phy@3 {
compatible = "ethernet-phy-id03a2.9481";
reg = <3>;
phy-mode = "internal";
nvmem-cells = <&phy_calibration_p3>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy3_led0: gsw-phy3-led0@0 {
reg = <0>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
gsw_phy3_led1: gsw-phy3-led1@1 {
reg = <1>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
};
};
};
}; };
ethwarp: syscon@15031000 { ethwarp: syscon@15031000 {
@ -843,6 +1104,40 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
status = "disabled"; status = "disabled";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "internal";
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
};
gmac2: mac@2 {
compatible = "mediatek,eth-mac";
reg = <2>;
};
mdio_bus: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
/* internal 2.5G PHY */
int_2p5g_phy: ethernet-phy@15 {
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "internal";
};
};
}; };
}; };
}; };

381
target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c
View file

@ -46,37 +46,53 @@ static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
}; };
static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
PIN_FIELD_BASE(0, 1, 5, 0x30, 0x10, 13, 1), PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1),
PIN_FIELD_BASE(2, 3, 5, 0x30, 0x10, 11, 1), PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1),
PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1),
PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1),
PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1),
PIN_FIELD_BASE(5, 6, 5, 0x30, 0x10, 9, 1), PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1),
PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1),
PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1),
PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1),
PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1),
PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1),
PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1),
PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1),
PIN_FIELD_BASE(13, 14, 1, 0x40, 0x10, 1, 1), PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1),
PIN_FIELD_BASE(15, 16, 5, 0x30, 0x10, 7, 1), PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1),
PIN_FIELD_BASE(17, 18, 5, 0x30, 0x10, 3, 1),
PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1),
PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1),
PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1),
PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1),
PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1),
PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1),
PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1),
PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1),
PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1),
PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1),
PIN_FIELD_BASE(25, 26, 3, 0x50, 0x10, 21, 1), PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1),
PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1),
PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1),
PIN_FIELD_BASE(28, 30, 3, 0x50, 0x10, 25, 1), PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1),
PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1),
PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1),
PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1),
PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1),
PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1),
PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1),
PIN_FIELD_BASE(35, 36, 3, 0x50, 0x10, 29, 1), PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1),
PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1),
PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1),
PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1),
PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1),
PIN_FIELD_BASE(40, 41, 3, 0x50, 0x10, 0, 1), PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1),
PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1),
PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1),
@ -86,17 +102,31 @@ static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1),
PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1),
PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1),
PIN_FIELD_BASE(51, 53, 3, 0x50, 0x10, 12, 1), PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1),
PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1),
PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1),
PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1),
PIN_FIELD_BASE(55, 56, 1, 0x40, 0x10, 14, 1),
PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1),
PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1),
PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1),
PIN_FIELD_BASE(58, 60, 1, 0x40, 0x10, 4, 1), PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1),
PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1),
PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1),
PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1),
PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1),
PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1),
PIN_FIELD_BASE(64, 68, 1, 0x40, 0x10, 8, 1), PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1),
PIN_FIELD_BASE(69, 70, 5, 0x30, 0x10, 1, 1), PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1),
PIN_FIELD_BASE(71, 72, 5, 0x30, 0x10, 5, 1), PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1),
PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1),
PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1),
PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1),
PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1),
PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1),
PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1),
PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1),
PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1),
@ -104,42 +134,61 @@ static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1),
PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1),
PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1),
PIN_FIELD_BASE(80, 81, 1, 0x40, 0x10, 18, 1),
PIN_FIELD_BASE(82, 83, 1, 0x40, 0x10, 16, 1), PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1),
PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1),
PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1),
PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1),
}; };
static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
PIN_FIELD_BASE(0, 1, 5, 0xc0, 0x10, 13, 1), PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1),
PIN_FIELD_BASE(2, 3, 5, 0xc0, 0x10, 11, 1), PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1),
PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1),
PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1),
PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1),
PIN_FIELD_BASE(5, 6, 5, 0xc0, 0x10, 9, 1), PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1),
PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1),
PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1),
PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1),
PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1),
PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1),
PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1),
PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1),
PIN_FIELD_BASE(13, 14, 1, 0xe0, 0x10, 1, 1), PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1),
PIN_FIELD_BASE(15, 16, 5, 0xc0, 0x10, 7, 1), PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1),
PIN_FIELD_BASE(17, 18, 5, 0xc0, 0x10, 3, 1),
PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1),
PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1),
PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1),
PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1),
PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1),
PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1),
PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1),
PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1),
PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1),
PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1),
PIN_FIELD_BASE(25, 26, 3, 0x140, 0x10, 21, 1), PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1),
PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1),
PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1),
PIN_FIELD_BASE(28, 30, 3, 0x140, 0x10, 25, 1), PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1),
PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1),
PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1),
PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1),
PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1),
PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1),
PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1),
PIN_FIELD_BASE(35, 36, 3, 0x140, 0x10, 29, 1), PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1),
PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1),
PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1),
PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1),
PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1),
PIN_FIELD_BASE(40, 41, 3, 0x140, 0x10, 0, 1), PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1),
PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1),
PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1),
PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1),
@ -149,17 +198,31 @@ static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1),
PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1),
PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1),
PIN_FIELD_BASE(51, 53, 3, 0x140, 0x10, 12, 1), PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1),
PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1),
PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1),
PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1),
PIN_FIELD_BASE(55, 56, 1, 0xe0, 0x10, 14, 1),
PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1),
PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1),
PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1),
PIN_FIELD_BASE(58, 60, 1, 0xe0, 0x10, 4, 1), PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1),
PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1),
PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1),
PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1),
PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1),
PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1),
PIN_FIELD_BASE(64, 68, 1, 0xe0, 0x10, 8, 1), PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1),
PIN_FIELD_BASE(69, 70, 5, 0xc0, 0x10, 1, 1), PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1),
PIN_FIELD_BASE(71, 72, 5, 0xc0, 0x10, 5, 1), PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1),
PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1),
PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1),
PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1),
PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1),
PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1),
PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1),
PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1),
PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1),
@ -167,8 +230,11 @@ static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1),
PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1),
PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1),
PIN_FIELD_BASE(80, 81, 1, 0xe0, 0x10, 18, 1),
PIN_FIELD_BASE(82, 83, 1, 0xe0, 0x10, 16, 1), PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1),
PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1),
PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1),
PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1),
}; };
static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
@ -176,8 +242,11 @@ static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1),
PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1),
PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1),
PIN_FIELD_BASE(13, 14, 1, 0x70, 0x10, 0, 1),
PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1),
PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1),
PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1),
PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1),
PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1),
PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1),
@ -190,11 +259,19 @@ static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1),
PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1),
PIN_FIELD_BASE(13, 14, 1, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(15, 16, 5, 0x40, 0x10, 4, 1), PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(17, 18, 5, 0x40, 0x10, 0, 1), PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1),
PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1),
PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1),
PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1),
PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1),
PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1),
PIN_FIELD_BASE(71, 72, 5, 0x40, 0x10, 2, 1), PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1),
PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1),
PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1),
PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1),
PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1),
@ -203,26 +280,37 @@ static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
}; };
static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
PIN_FIELD_BASE(0, 1, 5, 0x00, 0x10, 21, 3), PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3),
PIN_FIELD_BASE(2, 3, 5, 0x00, 0x10, 15, 3), PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3),
PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3),
PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3),
PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(5, 6, 5, 0x00, 0x10, 9, 3), PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3),
PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3),
PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3),
PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3),
PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3),
PIN_FIELD_BASE(13, 14, 1, 0x00, 0x10, 3, 3), PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3),
PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3),
PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3),
PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3),
PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3),
PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3),
PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3),
PIN_FIELD_BASE(25, 26, 3, 0x20, 0x10, 3, 3), PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3),
PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3),
PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3),
PIN_FIELD_BASE(28, 30, 3, 0x20, 0x10, 15, 3), PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3),
PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3),
PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3),
PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3),
PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3),
PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3),
@ -232,7 +320,8 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3),
PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3),
PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3),
PIN_FIELD_BASE(40, 41, 3, 0x00, 0x10, 0, 3), PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3),
PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3),
PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3),
@ -242,17 +331,29 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3),
PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3),
PIN_FIELD_BASE(51, 53, 3, 0x10, 0x10, 6, 3), PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3),
PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3),
PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3),
PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3),
PIN_FIELD_BASE(55, 56, 1, 0x10, 0x10, 12, 3),
PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3),
PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3),
PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3),
PIN_FIELD_BASE(58, 60, 1, 0x00, 0x10, 12, 3), PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3),
PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3),
PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3),
PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3),
PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3),
PIN_FIELD_BASE(64, 65, 1, 0x00, 0x10, 24, 3), PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3),
PIN_FIELD_BASE(66, 68, 1, 0x10, 0x10, 0, 3), PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3),
PIN_FIELD_BASE(69, 70, 5, 0x00, 0x10, 3, 3), PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3),
PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3),
PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3),
PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3),
PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3),
PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3),
@ -260,35 +361,49 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3),
PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3),
PIN_FIELD_BASE(80, 81, 1, 0x10, 0x10, 24, 3),
PIN_FIELD_BASE(82, 83, 1, 0x10, 0x10, 18, 3), PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3),
PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3),
PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3),
PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3),
}; };
static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
PIN_FIELD_BASE(0, 1, 5, 0x50, 0x10, 7, 1), PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1),
PIN_FIELD_BASE(2, 3, 5, 0x50, 0x10, 5, 1), PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1),
PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1),
PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1),
PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(5, 6, 5, 0x50, 0x10, 3, 1), PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1),
PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1),
PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1),
PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1),
PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1),
PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1),
PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1),
PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1),
PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1),
PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1),
PIN_FIELD_BASE(25, 26, 3, 0x70, 0x10, 21, 1), PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1),
PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1),
PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1),
PIN_FIELD_BASE(28, 30, 3, 0x70, 0x10, 25, 1), PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1),
PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1),
PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1),
PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1),
PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1),
PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1),
PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1),
PIN_FIELD_BASE(35, 36, 3, 0x70, 0x10, 29, 1), PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1),
PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1),
PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1),
PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1),
PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1),
PIN_FIELD_BASE(40, 41, 3, 0x70, 0x10, 0, 1), PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1),
PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1),
PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1),
PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1),
@ -298,46 +413,73 @@ static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1),
PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1),
PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1),
PIN_FIELD_BASE(51, 53, 3, 0x70, 0x10, 12, 1), PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1),
PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1),
PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1),
PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1),
PIN_FIELD_BASE(55, 56, 1, 0x60, 0x10, 12, 1),
PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1),
PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1),
PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1),
PIN_FIELD_BASE(58, 60, 1, 0x60, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1),
PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1),
PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1),
PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1),
PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1),
PIN_FIELD_BASE(64, 68, 1, 0x60, 0x10, 6, 1), PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1),
PIN_FIELD_BASE(69, 70, 5, 0x50, 0x10, 1, 1), PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1),
PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1),
PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1),
PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1),
PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1),
PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1),
PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(80, 81, 1, 0x60, 0x10, 16, 1),
PIN_FIELD_BASE(82, 83, 1, 0x60, 0x10, 14, 1), PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1),
PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1),
PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1),
PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1),
}; };
static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
PIN_FIELD_BASE(0, 1, 5, 0x60, 0x10, 7, 1), PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1),
PIN_FIELD_BASE(2, 3, 5, 0x60, 0x10, 5, 1), PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1),
PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1),
PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1),
PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1),
PIN_FIELD_BASE(5, 6, 5, 0x60, 0x10, 3, 1), PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1),
PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1),
PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1),
PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1),
PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1),
PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1),
PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1),
PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1),
PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1),
PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1),
PIN_FIELD_BASE(25, 26, 3, 0x90, 0x10, 21, 1), PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1),
PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1),
PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1),
PIN_FIELD_BASE(28, 30, 3, 0x90, 0x10, 25, 1), PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1),
PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1),
PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1),
PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1),
PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1),
PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1),
PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1),
PIN_FIELD_BASE(35, 36, 3, 0x90, 0x10, 29, 1), PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1),
PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1),
PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1),
PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1),
PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1),
PIN_FIELD_BASE(40, 41, 3, 0x90, 0x10, 0, 1), PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1),
PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1),
PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1),
PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1),
@ -347,46 +489,73 @@ static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1),
PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1),
PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1),
PIN_FIELD_BASE(51, 53, 3, 0x90, 0x10, 12, 1), PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1),
PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1),
PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1),
PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1),
PIN_FIELD_BASE(55, 56, 1, 0x80, 0x10, 12, 1),
PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1),
PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1),
PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1),
PIN_FIELD_BASE(58, 60, 1, 0x80, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1),
PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1),
PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1),
PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1),
PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1),
PIN_FIELD_BASE(64, 68, 1, 0x80, 0x10, 6, 1), PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1),
PIN_FIELD_BASE(69, 70, 5, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1),
PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1),
PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1),
PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1),
PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1),
PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1),
PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1),
PIN_FIELD_BASE(80, 81, 1, 0x80, 0x10, 16, 1),
PIN_FIELD_BASE(82, 83, 1, 0x80, 0x10, 14, 1), PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1),
PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1),
PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1),
PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1),
}; };
static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
PIN_FIELD_BASE(0, 1, 5, 0x70, 0x10, 7, 1), PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1),
PIN_FIELD_BASE(2, 3, 5, 0x70, 0x10, 5, 1), PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1),
PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1),
PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1),
PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1),
PIN_FIELD_BASE(5, 6, 5, 0x70, 0x10, 3, 1), PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1),
PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1),
PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1),
PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1),
PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1),
PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1),
PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1),
PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1),
PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1),
PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1),
PIN_FIELD_BASE(25, 26, 3, 0xb0, 0x10, 21, 1), PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1),
PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1),
PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1),
PIN_FIELD_BASE(28, 30, 3, 0xb0, 0x10, 25, 1), PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1),
PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1),
PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1),
PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1),
PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1),
PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1),
PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1),
PIN_FIELD_BASE(35, 36, 3, 0xb0, 0x10, 29, 1), PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1),
PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1),
PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1),
PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1),
PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1),
PIN_FIELD_BASE(40, 41, 3, 0xb0, 0x10, 0, 1), PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1),
PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1),
PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1),
PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1),
@ -396,19 +565,35 @@ static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1),
PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1),
PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1),
PIN_FIELD_BASE(51, 53, 3, 0xb0, 0x10, 12, 1), PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1),
PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1),
PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1),
PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1),
PIN_FIELD_BASE(55, 56, 1, 0x90, 0x10, 12, 1),
PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1),
PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1),
PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1),
PIN_FIELD_BASE(58, 60, 1, 0x90, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1),
PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1),
PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1),
PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1),
PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1),
PIN_FIELD_BASE(64, 68, 1, 0x90, 0x10, 6, 1), PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1),
PIN_FIELD_BASE(69, 70, 5, 0x70, 0x10, 1, 1), PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1),
PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1),
PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1),
PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1),
PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1),
PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1),
PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1),
PIN_FIELD_BASE(80, 81, 1, 0x90, 0x10, 16, 1),
PIN_FIELD_BASE(82, 83, 1, 0x90, 0x10, 14, 1), PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1),
PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1),
PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1),
PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
}; };
static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {

143
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts
View file

@ -7,6 +7,7 @@
/dts-v1/; /dts-v1/;
#include "mt7988a-rfb-spim-nand.dtsi" #include "mt7988a-rfb-spim-nand.dtsi"
#include <dt-bindings/pinctrl/mt65xx.h> #include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/leds/common.h>
/ { / {
model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
@ -29,39 +30,27 @@
pinctrl-0 = <&mdio0_pins>; pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
status = "okay"; status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "internal";
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
}; };
gmac1: mac@1 { &gmac0 {
compatible = "mediatek,eth-mac"; status = "okay";
reg = <1>; };
&gmac1 {
status = "okay";
phy-mode = "internal"; phy-mode = "internal";
phy-connection-type = "internal"; phy-connection-type = "internal";
phy = <&phy15>; phy = <&int_2p5g_phy>;
}; };
gmac2: mac@2 { &gmac2 {
compatible = "mediatek,eth-mac"; status = "okay";
reg = <2>; phy-mode = "usxgmii";
phy-mode = "10gbase-kr"; phy-connection-type = "usxgmii";
phy-connection-type = "10gbase-kr";
phy = <&phy8>; phy = <&phy8>;
}; };
mdio0: mdio-bus { &mdio_bus {
#address-cells = <1>;
#size-cells = <0>;
/* external Aquantia AQR113C */ /* external Aquantia AQR113C */
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
@ -93,109 +82,53 @@
compatible = "ethernet-phy-ieee802.3-c45"; compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "2500base-x"; phy-mode = "2500base-x";
}; };
};
/* internal 2.5G PHY */ &int_2p5g_phy {
phy15: ethernet-phy@15 {
reg = <15>;
pinctrl-names = "i2p5gbe-led"; pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>; pinctrl-0 = <&i2p5gbe_led0_pins>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "internal";
};
};
}; };
&switch { &switch {
status = "okay"; status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
phy-mode = "internal";
phy-handle = <&gsw_phy0>;
}; };
port@1 { &gsw_phy0 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&gsw_phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&gsw_phy2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&gsw_phy3>;
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "internal";
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
mediatek,pio = <&pio>;
gsw_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id03a2.9481";
reg = <0>;
phy-mode = "internal";
pinctrl-names = "gbe-led"; pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe0_led0_pins>; pinctrl-0 = <&gbe0_led0_pins>;
nvmem-cells = <&phy_calibration_p0>;
nvmem-cell-names = "phy-cal-data";
}; };
gsw_phy1: ethernet-phy@1 { &gsw_phy0_led0 {
compatible = "ethernet-phy-id03a2.9481"; status = "okay";
reg = <1>; color = <LED_COLOR_ID_GREEN>;
phy-mode = "internal"; };
&gsw_phy1 {
pinctrl-names = "gbe-led"; pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe1_led0_pins>; pinctrl-0 = <&gbe1_led0_pins>;
nvmem-cells = <&phy_calibration_p1>;
nvmem-cell-names = "phy-cal-data";
}; };
gsw_phy2: ethernet-phy@2 { &gsw_phy1_led0 {
compatible = "ethernet-phy-id03a2.9481"; status = "okay";
reg = <2>; color = <LED_COLOR_ID_GREEN>;
phy-mode = "internal"; };
&gsw_phy2 {
pinctrl-names = "gbe-led"; pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe2_led0_pins>; pinctrl-0 = <&gbe2_led0_pins>;
nvmem-cells = <&phy_calibration_p2>;
nvmem-cell-names = "phy-cal-data";
}; };
gsw_phy3: ethernet-phy@3 { &gsw_phy2_led0 {
compatible = "ethernet-phy-id03a2.9481"; status = "okay";
reg = <3>; color = <LED_COLOR_ID_GREEN>;
phy-mode = "internal"; };
&gsw_phy3 {
pinctrl-names = "gbe-led"; pinctrl-names = "gbe-led";
pinctrl-0 = <&gbe3_led0_pins>; pinctrl-0 = <&gbe3_led0_pins>;
nvmem-cells = <&phy_calibration_p3>;
nvmem-cell-names = "phy-cal-data";
};
}; };
&gsw_phy3_led0 {
status = "okay";
color = <LED_COLOR_ID_GREEN>;
}; };

321
target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
View file

@ -4,12 +4,13 @@
* Author: Sam.Shih <sam.shih@mediatek.com> * Author: Sam.Shih <sam.shih@mediatek.com>
*/ */
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/ti-syscon.h>
#include <dt-bindings/clock/mediatek,mt7988-clk.h> #include <dt-bindings/clock/mediatek,mt7988-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt65xx.h> #include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/reset/ti-syscon.h>
#include <dt-bindings/thermal/thermal.h> #include <dt-bindings/thermal/thermal.h>
/ { / {
@ -144,9 +145,9 @@
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */ /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
secmon_reserved: secmon@43000000 { secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>; reg = <0 0x43000000 0 0x50000>;
no-map; no-map;
}; };
}; };
@ -228,7 +229,7 @@
"iocfg_lb_base", "iocfg_tl_base", "eint"; "iocfg_lb_base", "iocfg_tl_base", "eint";
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-ranges = <&pio 0 0 83>; gpio-ranges = <&pio 0 0 84>;
interrupt-controller; interrupt-controller;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
@ -260,47 +261,131 @@
}; };
}; };
i2c2_pins: i2c2-pins-g0 { i2c1_sfp_pins: i2c1-sfp-pins-g0 {
mux {
function = "i2c";
groups = "i2c1_sfp";
};
};
i2c2_pins: i2c2-pins {
mux {
function = "i2c";
groups = "i2c2";
};
};
i2c2_0_pins: i2c2-pins-g0 {
mux {
function = "i2c";
groups = "i2c2_0";
};
};
i2c2_1_pins: i2c2-pins-g1 {
mux { mux {
function = "i2c"; function = "i2c";
groups = "i2c2_1"; groups = "i2c2_1";
}; };
}; };
gbe0_led0_pins: gbe0-pins { gbe0_led0_pins: gbe0-led0-pins {
mux { mux {
function = "led"; function = "led";
groups = "gbe0_led0"; groups = "gbe0_led0";
}; };
}; };
gbe1_led0_pins: gbe1-pins { gbe1_led0_pins: gbe1-led0-pins {
mux { mux {
function = "led"; function = "led";
groups = "gbe1_led0"; groups = "gbe1_led0";
}; };
}; };
gbe2_led0_pins: gbe2-pins { gbe2_led0_pins: gbe2-led0-pins {
mux { mux {
function = "led"; function = "led";
groups = "gbe2_led0"; groups = "gbe2_led0";
}; };
}; };
gbe3_led0_pins: gbe3-pins { gbe3_led0_pins: gbe3-led0-pins {
mux { mux {
function = "led"; function = "led";
groups = "gbe3_led0"; groups = "gbe3_led0";
}; };
}; };
i2p5gbe_led0_pins: 2p5gbe-pins { gbe0_led1_pins: gbe0-led1-pins {
mux {
function = "led";
groups = "gbe0_led1";
};
};
gbe1_led1_pins: gbe1-led1-pins {
mux {
function = "led";
groups = "gbe1_led1";
};
};
gbe2_led1_pins: gbe2-led1-pins {
mux {
function = "led";
groups = "gbe2_led1";
};
};
gbe3_led1_pins: gbe3-led1-pins {
mux {
function = "led";
groups = "gbe3_led1";
};
};
i2p5gbe_led0_pins: 2p5gbe-led0-pins {
mux { mux {
function = "led"; function = "led";
groups = "2p5gbe_led0"; groups = "2p5gbe_led0";
}; };
}; };
i2p5gbe_led1_pins: 2p5gbe-led1-pins {
mux {
function = "led";
groups = "2p5gbe_led1";
};
};
mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
mux {
function = "flash";
groups = "emmc_45";
};
};
mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
mux {
function = "flash";
groups = "emmc_51";
};
};
mmc0_pins_sdcard: mmc0-pins-sdcard {
mux {
function = "flash";
groups = "sdcard";
};
};
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0";
};
};
}; };
sgmiisys0: syscon@10060000 { sgmiisys0: syscon@10060000 {
@ -380,6 +465,8 @@
<&infracfg CLK_INFRA_MUX_UART0_SEL>; <&infracfg CLK_INFRA_MUX_UART0_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
<&topckgen CLK_TOP_UART_SEL>; <&topckgen CLK_TOP_UART_SEL>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "disabled"; status = "disabled";
}; };
@ -645,6 +732,29 @@
status = "disabled"; status = "disabled";
}; };
mmc0: mmc@11230000 {
compatible = "mediatek,mt7986-mmc",
"mediatek,mt7981-mmc";
reg = <0 0x11230000 0 0x1000>,
<0 0x11D60000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_MSDC400>,
<&infracfg CLK_INFRA_MSDC2_HCK>,
<&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
<&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
<&topckgen CLK_TOP_EMMC_400M_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
<&apmixedsys CLK_APMIXED_MSDCPLL>;
clock-names = "source",
"hclk",
"axi_cg",
"ahb_cg";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
tphy: tphy@11c50000 { tphy: tphy@11c50000 {
compatible = "mediatek,mt7988", compatible = "mediatek,mt7988",
"mediatek,generic-tphy-v2"; "mediatek,generic-tphy-v2";
@ -747,6 +857,157 @@
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ethrst 0>; resets = <&ethrst 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan0";
phy-mode = "internal";
phy-handle = <&gsw_phy0>;
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&gsw_phy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&gsw_phy2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&gsw_phy3>;
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "internal";
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
mediatek,pio = <&pio>;
gsw_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id03a2.9481";
reg = <0>;
phy-mode = "internal";
nvmem-cells = <&phy_calibration_p0>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy0_led0: gsw-phy0-led0@0 {
reg = <0>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
gsw_phy0_led1: gsw-phy0-led1@1 {
reg = <1>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
};
};
gsw_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id03a2.9481";
reg = <1>;
phy-mode = "internal";
nvmem-cells = <&phy_calibration_p1>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy1_led0: gsw-phy1-led0@0 {
reg = <0>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
gsw_phy1_led1: gsw-phy1-led1@1 {
reg = <1>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
};
};
gsw_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-id03a2.9481";
reg = <2>;
phy-mode = "internal";
nvmem-cells = <&phy_calibration_p2>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy2_led0: gsw-phy2-led0@0 {
reg = <0>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
gsw_phy2_led1: gsw-phy2-led1@1 {
reg = <1>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
};
};
gsw_phy3: ethernet-phy@3 {
compatible = "ethernet-phy-id03a2.9481";
reg = <3>;
phy-mode = "internal";
nvmem-cells = <&phy_calibration_p3>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy3_led0: gsw-phy3-led0@0 {
reg = <0>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
gsw_phy3_led1: gsw-phy3-led1@1 {
reg = <1>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
};
};
};
}; };
ethwarp: syscon@15031000 { ethwarp: syscon@15031000 {
@ -843,6 +1104,40 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
status = "disabled"; status = "disabled";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "internal";
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
};
gmac2: mac@2 {
compatible = "mediatek,eth-mac";
reg = <2>;
};
mdio_bus: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
/* internal 2.5G PHY */
int_2p5g_phy: ethernet-phy@15 {
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c45";
phy-mode = "internal";
};
};
}; };
}; };
}; };

382
target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c
View file

@ -46,37 +46,53 @@ static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
}; };
static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
PIN_FIELD_BASE(0, 1, 5, 0x30, 0x10, 13, 1), PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1),
PIN_FIELD_BASE(2, 3, 5, 0x30, 0x10, 11, 1), PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1),
PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1),
PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1),
PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1),
PIN_FIELD_BASE(5, 6, 5, 0x30, 0x10, 9, 1), PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1),
PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1),
PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1),
PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1),
PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1),
PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1),
PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1),
PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1),
PIN_FIELD_BASE(13, 14, 1, 0x40, 0x10, 1, 1), PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1),
PIN_FIELD_BASE(15, 16, 5, 0x30, 0x10, 7, 1), PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1),
PIN_FIELD_BASE(17, 18, 5, 0x30, 0x10, 3, 1),
PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1),
PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1),
PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1),
PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1),
PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1),
PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1),
PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1),
PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1),
PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1),
PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1),
PIN_FIELD_BASE(25, 26, 3, 0x50, 0x10, 21, 1), PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1),
PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1),
PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1),
PIN_FIELD_BASE(28, 30, 3, 0x50, 0x10, 25, 1), PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1),
PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1),
PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1),
PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1),
PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1),
PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1),
PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1),
PIN_FIELD_BASE(35, 36, 3, 0x50, 0x10, 29, 1), PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1),
PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1),
PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1),
PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1),
PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1),
PIN_FIELD_BASE(40, 41, 3, 0x50, 0x10, 0, 1), PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1),
PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1),
PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1),
@ -86,17 +102,31 @@ static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1),
PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1),
PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1),
PIN_FIELD_BASE(51, 53, 3, 0x50, 0x10, 12, 1), PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1),
PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1),
PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1),
PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1),
PIN_FIELD_BASE(55, 56, 1, 0x40, 0x10, 14, 1),
PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1),
PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1),
PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1),
PIN_FIELD_BASE(58, 60, 1, 0x40, 0x10, 4, 1), PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1),
PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1),
PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1),
PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1),
PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1),
PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1),
PIN_FIELD_BASE(64, 68, 1, 0x40, 0x10, 8, 1), PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1),
PIN_FIELD_BASE(69, 70, 5, 0x30, 0x10, 1, 1), PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1),
PIN_FIELD_BASE(71, 72, 5, 0x30, 0x10, 5, 1), PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1),
PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1),
PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1),
PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1),
PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1),
PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1),
PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1),
PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1),
PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1),
@ -104,42 +134,61 @@ static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1),
PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1),
PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1),
PIN_FIELD_BASE(80, 81, 1, 0x40, 0x10, 18, 1),
PIN_FIELD_BASE(82, 83, 1, 0x40, 0x10, 16, 1), PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1),
PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1),
PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1),
PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1),
}; };
static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
PIN_FIELD_BASE(0, 1, 5, 0xc0, 0x10, 13, 1), PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1),
PIN_FIELD_BASE(2, 3, 5, 0xc0, 0x10, 11, 1), PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1),
PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1),
PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1),
PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1),
PIN_FIELD_BASE(5, 6, 5, 0xc0, 0x10, 9, 1), PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1),
PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1),
PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1),
PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1),
PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1),
PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1),
PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1),
PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1),
PIN_FIELD_BASE(13, 14, 1, 0xe0, 0x10, 1, 1), PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1),
PIN_FIELD_BASE(15, 16, 5, 0xc0, 0x10, 7, 1), PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1),
PIN_FIELD_BASE(17, 18, 5, 0xc0, 0x10, 3, 1),
PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1),
PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1),
PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1),
PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1),
PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1),
PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1),
PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1),
PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1),
PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1),
PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1),
PIN_FIELD_BASE(25, 26, 3, 0x140, 0x10, 21, 1), PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1),
PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1),
PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1),
PIN_FIELD_BASE(28, 30, 3, 0x140, 0x10, 25, 1), PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1),
PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1),
PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1),
PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1),
PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1),
PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1),
PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1),
PIN_FIELD_BASE(35, 36, 3, 0x140, 0x10, 29, 1), PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1),
PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1),
PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1),
PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1),
PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1),
PIN_FIELD_BASE(40, 41, 3, 0x140, 0x10, 0, 1), PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1),
PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1),
PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1),
PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1),
@ -149,17 +198,31 @@ static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1),
PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1),
PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1),
PIN_FIELD_BASE(51, 53, 3, 0x140, 0x10, 12, 1), PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1),
PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1),
PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1),
PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1),
PIN_FIELD_BASE(55, 56, 1, 0xe0, 0x10, 14, 1),
PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1),
PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1),
PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1),
PIN_FIELD_BASE(58, 60, 1, 0xe0, 0x10, 4, 1), PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1),
PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1),
PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1),
PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1),
PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1),
PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1),
PIN_FIELD_BASE(64, 68, 1, 0xe0, 0x10, 8, 1), PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1),
PIN_FIELD_BASE(69, 70, 5, 0xc0, 0x10, 1, 1), PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1),
PIN_FIELD_BASE(71, 72, 5, 0xc0, 0x10, 5, 1), PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1),
PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1),
PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1),
PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1),
PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1),
PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1),
PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1),
PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1),
PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1),
@ -167,8 +230,11 @@ static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1),
PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1),
PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1),
PIN_FIELD_BASE(80, 81, 1, 0xe0, 0x10, 18, 1),
PIN_FIELD_BASE(82, 83, 1, 0xe0, 0x10, 16, 1), PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1),
PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1),
PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1),
PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1),
}; };
static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
@ -176,8 +242,11 @@ static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1),
PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1),
PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1),
PIN_FIELD_BASE(13, 14, 1, 0x70, 0x10, 0, 1),
PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1),
PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1),
PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1),
PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1),
PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1),
PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1),
@ -190,11 +259,19 @@ static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1),
PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1),
PIN_FIELD_BASE(13, 14, 1, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(15, 16, 5, 0x40, 0x10, 4, 1), PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(17, 18, 5, 0x40, 0x10, 0, 1), PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1),
PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1),
PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1),
PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1),
PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1),
PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1),
PIN_FIELD_BASE(71, 72, 5, 0x40, 0x10, 2, 1), PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1),
PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1),
PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1),
PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1),
PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1),
@ -203,26 +280,37 @@ static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
}; };
static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
PIN_FIELD_BASE(0, 1, 5, 0x00, 0x10, 21, 3), PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3),
PIN_FIELD_BASE(2, 3, 5, 0x00, 0x10, 15, 3), PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3),
PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3),
PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3),
PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(5, 6, 5, 0x00, 0x10, 9, 3), PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3),
PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3),
PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3),
PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3),
PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3),
PIN_FIELD_BASE(13, 14, 1, 0x00, 0x10, 3, 3), PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3),
PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3),
PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3),
PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3),
PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3),
PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3),
PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3),
PIN_FIELD_BASE(25, 26, 3, 0x20, 0x10, 3, 3), PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3),
PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3),
PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3),
PIN_FIELD_BASE(28, 30, 3, 0x20, 0x10, 15, 3), PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3),
PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3),
PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3),
PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3),
PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3),
PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3),
@ -232,7 +320,8 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3),
PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3),
PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3),
PIN_FIELD_BASE(40, 41, 3, 0x00, 0x10, 0, 3), PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3),
PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3),
PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3),
@ -242,17 +331,29 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3),
PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3),
PIN_FIELD_BASE(51, 53, 3, 0x10, 0x10, 6, 3), PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3),
PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3),
PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3),
PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3),
PIN_FIELD_BASE(55, 56, 1, 0x10, 0x10, 12, 3),
PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3),
PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3),
PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3),
PIN_FIELD_BASE(58, 60, 1, 0x00, 0x10, 12, 3), PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3),
PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3),
PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3),
PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3),
PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3),
PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3),
PIN_FIELD_BASE(64, 65, 1, 0x00, 0x10, 24, 3), PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3),
PIN_FIELD_BASE(66, 68, 1, 0x10, 0x10, 0, 3), PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3),
PIN_FIELD_BASE(69, 70, 5, 0x00, 0x10, 3, 3), PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3),
PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3),
PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3),
PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3),
PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3),
PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3),
PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3),
@ -260,35 +361,49 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3),
PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3),
PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3),
PIN_FIELD_BASE(80, 81, 1, 0x10, 0x10, 24, 3),
PIN_FIELD_BASE(82, 83, 1, 0x10, 0x10, 18, 3), PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3),
PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3),
PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3),
PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3),
}; };
static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
PIN_FIELD_BASE(0, 1, 5, 0x50, 0x10, 7, 1), PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1),
PIN_FIELD_BASE(2, 3, 5, 0x50, 0x10, 5, 1), PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1),
PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1),
PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1),
PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(5, 6, 5, 0x50, 0x10, 3, 1), PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1),
PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1),
PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1),
PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1),
PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1),
PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1),
PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1),
PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1),
PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1),
PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1),
PIN_FIELD_BASE(25, 26, 3, 0x70, 0x10, 21, 1), PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1),
PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1),
PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1),
PIN_FIELD_BASE(28, 30, 3, 0x70, 0x10, 25, 1), PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1),
PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1),
PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1),
PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1),
PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1),
PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1),
PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1),
PIN_FIELD_BASE(35, 36, 3, 0x70, 0x10, 29, 1), PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1),
PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1),
PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1),
PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1),
PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1),
PIN_FIELD_BASE(40, 41, 3, 0x70, 0x10, 0, 1), PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1),
PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1),
PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1),
PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1),
@ -298,46 +413,73 @@ static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1),
PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1),
PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1),
PIN_FIELD_BASE(51, 53, 3, 0x70, 0x10, 12, 1), PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1),
PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1),
PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1),
PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1),
PIN_FIELD_BASE(55, 56, 1, 0x60, 0x10, 12, 1),
PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1),
PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1),
PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1),
PIN_FIELD_BASE(58, 60, 1, 0x60, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1),
PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1),
PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1),
PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1),
PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1),
PIN_FIELD_BASE(64, 68, 1, 0x60, 0x10, 6, 1), PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1),
PIN_FIELD_BASE(69, 70, 5, 0x50, 0x10, 1, 1), PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1),
PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1),
PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1),
PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1),
PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1),
PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1),
PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1),
PIN_FIELD_BASE(80, 81, 1, 0x60, 0x10, 16, 1),
PIN_FIELD_BASE(82, 83, 1, 0x60, 0x10, 14, 1), PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1),
PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1),
PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1),
PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1),
}; };
static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
PIN_FIELD_BASE(0, 1, 5, 0x60, 0x10, 7, 1), PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1),
PIN_FIELD_BASE(2, 3, 5, 0x60, 0x10, 5, 1), PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1),
PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1),
PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1),
PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1),
PIN_FIELD_BASE(5, 6, 5, 0x60, 0x10, 3, 1), PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1),
PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1),
PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1),
PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1),
PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1),
PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1),
PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1),
PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1),
PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1),
PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1),
PIN_FIELD_BASE(25, 26, 3, 0x90, 0x10, 21, 1), PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1),
PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1),
PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1),
PIN_FIELD_BASE(28, 30, 3, 0x90, 0x10, 25, 1), PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1),
PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1),
PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1),
PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1),
PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1),
PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1),
PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1),
PIN_FIELD_BASE(35, 36, 3, 0x90, 0x10, 29, 1), PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1),
PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1),
PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1),
PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1),
PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1),
PIN_FIELD_BASE(40, 41, 3, 0x90, 0x10, 0, 1), PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1),
PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1),
PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1),
PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1),
@ -347,46 +489,73 @@ static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1),
PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1),
PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1),
PIN_FIELD_BASE(51, 53, 3, 0x90, 0x10, 12, 1), PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1),
PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1),
PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1),
PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1),
PIN_FIELD_BASE(55, 56, 1, 0x80, 0x10, 12, 1),
PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1),
PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1),
PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1),
PIN_FIELD_BASE(58, 60, 1, 0x80, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1),
PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1),
PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1),
PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1),
PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1),
PIN_FIELD_BASE(64, 68, 1, 0x80, 0x10, 6, 1), PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1),
PIN_FIELD_BASE(69, 70, 5, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1),
PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1),
PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1),
PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1),
PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1),
PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1),
PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1),
PIN_FIELD_BASE(80, 81, 1, 0x80, 0x10, 16, 1),
PIN_FIELD_BASE(82, 83, 1, 0x80, 0x10, 14, 1), PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1),
PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1),
PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1),
PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1),
}; };
static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
PIN_FIELD_BASE(0, 1, 5, 0x70, 0x10, 7, 1), PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1),
PIN_FIELD_BASE(2, 3, 5, 0x70, 0x10, 5, 1), PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1),
PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1),
PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1),
PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1),
PIN_FIELD_BASE(5, 6, 5, 0x70, 0x10, 3, 1), PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1),
PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1),
PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1),
PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1),
PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1),
PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1),
PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1),
PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1),
PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1),
PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1),
PIN_FIELD_BASE(25, 26, 3, 0xb0, 0x10, 21, 1), PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1),
PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1),
PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1),
PIN_FIELD_BASE(28, 30, 3, 0xb0, 0x10, 25, 1), PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1),
PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1),
PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1),
PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1),
PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1),
PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1),
PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1),
PIN_FIELD_BASE(35, 36, 3, 0xb0, 0x10, 29, 1), PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1),
PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1),
PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1),
PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1),
PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1),
PIN_FIELD_BASE(40, 41, 3, 0xb0, 0x10, 0, 1), PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1),
PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1),
PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1),
PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1),
PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1),
@ -396,19 +565,35 @@ static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1),
PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1),
PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1),
PIN_FIELD_BASE(51, 53, 3, 0xb0, 0x10, 12, 1), PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1),
PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1),
PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1),
PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1),
PIN_FIELD_BASE(55, 56, 1, 0x90, 0x10, 12, 1),
PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1),
PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1),
PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1),
PIN_FIELD_BASE(58, 60, 1, 0x90, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1),
PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1),
PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1),
PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1),
PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1),
PIN_FIELD_BASE(64, 68, 1, 0x90, 0x10, 6, 1), PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1),
PIN_FIELD_BASE(69, 70, 5, 0x70, 0x10, 1, 1), PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1),
PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1),
PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1),
PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1),
PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1),
PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1),
PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1),
PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1),
PIN_FIELD_BASE(80, 81, 1, 0x90, 0x10, 16, 1),
PIN_FIELD_BASE(82, 83, 1, 0x90, 0x10, 14, 1), PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1),
PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1),
PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1),
PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
}; };
static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
@ -1279,4 +1464,3 @@ static int __init mt7988_pinctrl_init(void)
return platform_driver_register(&mt7988_pinctrl_driver); return platform_driver_register(&mt7988_pinctrl_driver);
} }
arch_initcall(mt7988_pinctrl_init); arch_initcall(mt7988_pinctrl_init);

3
target/linux/mediatek/filogic/base-files/etc/board.d/02_network
View file

@ -8,6 +8,9 @@ mediatek_setup_interfaces()
local board="$1" local board="$1"
case $board in case $board in
acer,predator-w6)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 game" eth1
;;
asus,tuf-ax4200) asus,tuf-ax4200)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1 ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1
;; ;;

14
target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata
View file

@ -7,6 +7,20 @@
board=$(board_name) board=$(board_name)
case "$FIRMWARE" in case "$FIRMWARE" in
"mediatek/mt7916_eeprom.bin")
case "$board" in
acer,predator-w6)
caldata_extract_mmc "factory" 0xA0000 0x1000
;;
esac
;;
"mediatek/mt7986_eeprom_mt7976.bin")
case "$board" in
acer,predator-w6)
caldata_extract_mmc "factory" 0x0 0x1000
;;
esac
;;
"mediatek/mt7986_eeprom_mt7976_dbdc.bin") "mediatek/mt7986_eeprom_mt7976_dbdc.bin")
case "$board" in case "$board" in
asus,tuf-ax4200) asus,tuf-ax4200)

6
target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
View file

@ -10,6 +10,12 @@ PHYNBR=${DEVPATH##*/phy}
board=$(board_name) board=$(board_name)
case "$board" in case "$board" in
acer,predator-w6)
key_path="/var/qcidata/data"
[ "$PHYNBR" = "0" ] && cat $key_path/2gMAC > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && cat $key_path/6gMAC > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "2" ] && cat $key_path/5gMAC > /sys${DEVPATH}/macaddress
;;
asus,tuf-ax4200) asus,tuf-ax4200)
CI_UBIPART="UBI_DEV" CI_UBIPART="UBI_DEV"
addr=$(mtd_get_mac_binary_ubi "Factory" 0x4) addr=$(mtd_get_mac_binary_ubi "Factory" 0x4)

25
target/linux/mediatek/filogic/base-files/lib/preinit/05_extract_factory_data.sh Normal file
View file

@ -0,0 +1,25 @@
. /lib/functions/system.sh
predator_w6_factory_extract() {
local mmc_part
mmc_part="$(find_mmc_part qcidata)"
mkdir -p /var/qcidata/data
mkdir -p /var/qcidata/mount
mount -r "$mmc_part" /var/qcidata/mount
cp /var/qcidata/mount/factory/*MAC "/var/qcidata/data/"
umount "/var/qcidata/mount"
}
preinit_extract_factory() {
case $(board_name) in
acer,predator-w6)
predator_w6_factory_extract
;;
esac
}
boot_hook_add preinit_main preinit_extract_factory

8
target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh
View file

@ -2,6 +2,14 @@
preinit_set_mac_address() { preinit_set_mac_address() {
case $(board_name) in case $(board_name) in
acer,predator-w6)
key_path="/var/qcidata/data"
ip link set dev lan1 address "$(cat $key_path/LANMAC)"
ip link set dev lan2 address "$(cat $key_path/LANMAC)"
ip link set dev lan3 address "$(cat $key_path/LANMAC)"
ip link set dev game address "$(cat $key_path/LANMAC)"
ip link set dev eth1 address "$(cat $key_path/WANMAC)"
;;
asus,tuf-ax4200) asus,tuf-ax4200)
CI_UBIPART="UBI_DEV" CI_UBIPART="UBI_DEV"
addr=$(mtd_get_mac_binary_ubi "Factory" 0x4) addr=$(mtd_get_mac_binary_ubi "Factory" 0x4)

5
target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
View file

@ -51,6 +51,11 @@ platform_do_upgrade() {
local board=$(board_name) local board=$(board_name)
case "$board" in case "$board" in
acer,predator-w6)
CI_KERNPART="kernel"
CI_ROOTPART="rootfs"
emmc_do_upgrade "$1"
;;
asus,tuf-ax4200) asus,tuf-ax4200)
CI_UBIPART="UBI_DEV" CI_UBIPART="UBI_DEV"
CI_KERNPART="linux" CI_KERNPART="linux"

15
target/linux/mediatek/image/filogic.mk
View file

@ -98,6 +98,21 @@ define Device/asus_tuf-ax4200
endef endef
TARGET_DEVICES += asus_tuf-ax4200 TARGET_DEVICES += asus_tuf-ax4200
define Device/acer_predator-w6
DEVICE_VENDOR := Acer
DEVICE_MODEL := Predator W6
DEVICE_DTS := mt7986a-acer-predator-w6
DEVICE_DTS_DIR := ../dts
DEVICE_DTS_LOADADDR := 0x47000000
DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware kmod-mt7916-firmware mt7986-wo-firmware
IMAGES := sysupgrade.bin
KERNEL := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
KERNEL_INITRAMFS := kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
endef
TARGET_DEVICES += acer_predator-w6
define Device/bananapi_bpi-r3 define Device/bananapi_bpi-r3
DEVICE_VENDOR := Bananapi DEVICE_VENDOR := Bananapi
DEVICE_MODEL := BPi-R3 DEVICE_MODEL := BPi-R3

2
target/linux/mediatek/patches-5.15/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch
View file

@ -24,7 +24,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
--- a/MAINTAINERS --- a/MAINTAINERS
+++ b/MAINTAINERS +++ b/MAINTAINERS
@@ -11790,6 +11790,15 @@ S: Maintained @@ -11791,6 +11791,15 @@ S: Maintained
F: drivers/net/pcs/pcs-mtk-lynxi.c F: drivers/net/pcs/pcs-mtk-lynxi.c
F: include/linux/pcs/pcs-mtk-lynxi.h F: include/linux/pcs/pcs-mtk-lynxi.h

2
target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch
View file

@ -257,7 +257,7 @@ Signed-off-by: Wolfram Sang <wsa@kernel.org>
--- a/drivers/i2c/busses/i2c-ibm_iic.c --- a/drivers/i2c/busses/i2c-ibm_iic.c
+++ b/drivers/i2c/busses/i2c-ibm_iic.c +++ b/drivers/i2c/busses/i2c-ibm_iic.c
@@ -738,7 +738,7 @@ static int iic_probe(struct platform_dev @@ -736,7 +736,7 @@ static int iic_probe(struct platform_dev
adap = &dev->adap; adap = &dev->adap;
adap->dev.parent = &ofdev->dev; adap->dev.parent = &ofdev->dev;
adap->dev.of_node = of_node_get(np); adap->dev.of_node = of_node_get(np);

2
target/linux/mediatek/patches-5.15/901-arm-add-cmdline-override.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm/Kconfig --- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig +++ b/arch/arm/Kconfig
@@ -1729,6 +1729,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN @@ -1730,6 +1730,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
endchoice endchoice

4
target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch
View file

@ -1,6 +1,6 @@
--- a/arch/arm/Kconfig --- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig +++ b/arch/arm/Kconfig
@@ -1588,6 +1588,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN @@ -1589,6 +1589,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
endchoice endchoice
@ -37,7 +37,7 @@
* CONFIG_CMDLINE is meant to be a default in case nothing else * CONFIG_CMDLINE is meant to be a default in case nothing else
--- a/arch/arm64/Kconfig --- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig
@@ -2202,6 +2202,14 @@ config CMDLINE_FORCE @@ -2221,6 +2221,14 @@ config CMDLINE_FORCE
endchoice endchoice

1
target/linux/mvebu/Makefile
View file

@ -10,6 +10,7 @@ FEATURES:=fpu usb pci pcie gpio nand squashfs ramdisk boot-part rootfs-part lega
SUBTARGETS:=cortexa9 cortexa53 cortexa72 SUBTARGETS:=cortexa9 cortexa53 cortexa72
KERNEL_PATCHVER:=5.15 KERNEL_PATCHVER:=5.15
KERNEL_TESTING_PATCHVER:=6.1
include $(INCLUDE_DIR)/target.mk include $(INCLUDE_DIR)/target.mk

435
target/linux/mvebu/config-6.1 Normal file
View file

@ -0,0 +1,435 @@
CONFIG_AHCI_MVEBU=y
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_MVEBU=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARMADA_370_CLK=y
CONFIG_ARMADA_370_XP_IRQ=y
CONFIG_ARMADA_370_XP_TIMER=y
# CONFIG_ARMADA_37XX_WATCHDOG is not set
CONFIG_ARMADA_38X_CLK=y
CONFIG_ARMADA_THERMAL=y
CONFIG_ARMADA_XP_CLK=y
CONFIG_ARM_APPENDED_DTB=y
# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set
# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set
CONFIG_ARM_ATAG_DTB_COMPAT=y
# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
CONFIG_ARM_CPU_SUSPEND=y
CONFIG_ARM_CRYPTO=y
CONFIG_ARM_ERRATA_720789=y
CONFIG_ARM_ERRATA_764369=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GLOBAL_TIMER=y
CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=1
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_HEAVY_MB=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_MVEBU_V7_CPUIDLE=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_ATA=y
CONFIG_ATAGS=y
CONFIG_ATA_LEDS=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NVME=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BOUNCE=y
# CONFIG_CACHE_FEROCEON_L2 is not set
CONFIG_CACHE_L2X0=y
CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PJ4B=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
CONFIG_CRYPTO_AES_ARM=y
CONFIG_CRYPTO_AES_ARM_BS=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DEV_MARVELL=y
CONFIG_CRYPTO_DEV_MARVELL_CESA=y
CONFIG_CRYPTO_ESSIV=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA1_ARM=y
CONFIG_CRYPTO_SHA1_ARM_NEON=y
CONFIG_CRYPTO_SHA256_ARM=y
CONFIG_CRYPTO_SHA512_ARM=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_ALIGN_RODATA=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
CONFIG_DEBUG_MVEBU_UART0=y
# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set
# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set
CONFIG_DEBUG_UART_8250=y
CONFIG_DEBUG_UART_8250_SHIFT=2
CONFIG_DEBUG_UART_PHYS=0xd0012000
CONFIG_DEBUG_UART_VIRT=0xfec12000
CONFIG_DEBUG_UNCOMPRESS=y
CONFIG_DEBUG_USER=y
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_ENGINE_RAID=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
CONFIG_DMA_REMAP=y
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EXT4_FS=y
CONFIG_EXTCON=y
CONFIG_F2FS_FS=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GLOB=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_GPIO_MVEBU=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GRO_CELLS=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HIGHMEM=y
CONFIG_HIGHPTE=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HWBM=y
CONFIG_HWMON=y
CONFIG_HW_RANDOM=y
CONFIG_HZ_FIXED=0
CONFIG_HZ_PERIODIC=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MV64XXX=y
# CONFIG_I2C_PXA is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_IWMMXT is not set
CONFIG_JBD2=y
CONFIG_KMAP_LOCAL=y
CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PCA963X=y
CONFIG_LEDS_TLC591XX=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MACH_ARMADA_370=y
# CONFIG_MACH_ARMADA_375 is not set
CONFIG_MACH_ARMADA_38X=y
# CONFIG_MACH_ARMADA_39X is not set
CONFIG_MACH_ARMADA_XP=y
# CONFIG_MACH_DOVE is not set
CONFIG_MACH_MVEBU_ANY=y
CONFIG_MACH_MVEBU_V7=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_MANGLE_BOOTARGS=y
CONFIG_MARVELL_PHY=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_I2C=y
CONFIG_MEMFD_CREATE=y
CONFIG_MEMORY=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_MVSDIO=y
CONFIG_MMC_SDHCI=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_PXAV3=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_MVEBU_CLK_COMMON=y
CONFIG_MVEBU_CLK_COREDIV=y
CONFIG_MVEBU_CLK_CPU=y
CONFIG_MVEBU_DEVBUS=y
CONFIG_MVEBU_MBUS=y
CONFIG_MVMDIO=y
CONFIG_MVNETA=y
CONFIG_MVNETA_BM=y
CONFIG_MVNETA_BM_ENABLE=y
# CONFIG_MVPP2 is not set
CONFIG_MV_XOR=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEON=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MV88E6XXX=y
CONFIG_NET_DSA_TAG_DSA=y
CONFIG_NET_DSA_TAG_DSA_COMMON=y
CONFIG_NET_DSA_TAG_EDSA=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NLS=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
CONFIG_NVME_CORE=y
# CONFIG_NVME_HWMON is not set
# CONFIG_NVME_MULTIPATH is not set
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_ORION_WATCHDOG=y
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PAGE_POOL=y
CONFIG_PCI=y
CONFIG_PCI_BRIDGE_EMUL=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_MVEBU=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
# CONFIG_PHY_MVEBU_A3700_COMPHY is not set
# CONFIG_PHY_MVEBU_A3700_UTMI is not set
# CONFIG_PHY_MVEBU_A38X_COMPHY is not set
# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
# CONFIG_PHY_MVEBU_CP110_UTMI is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_370=y
CONFIG_PINCTRL_ARMADA_38X=y
CONFIG_PINCTRL_ARMADA_XP=y
CONFIG_PINCTRL_MVEBU=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PJ4B_ERRATA_4742=y
CONFIG_PL310_ERRATA_753970=y
CONFIG_PLAT_ORION=y
CONFIG_PM_OPP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_ARMADA38X=y
# CONFIG_RTC_DRV_MV is not set
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_SATA_HOST=y
CONFIG_SATA_MV=y
CONFIG_SATA_PMP=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
CONFIG_SENSORS_PWM_FAN=y
CONFIG_SENSORS_TMP421=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MVEBU_CONSOLE=y
CONFIG_SERIAL_MVEBU_UART=y
CONFIG_SFP=y
CONFIG_SGL_ALLOC=y
CONFIG_SG_POOL=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOC_BUS=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
# CONFIG_SPI_ARMADA_3700 is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_ORION=y
CONFIG_SRAM=y
CONFIG_SRAM_EXEC=y
CONFIG_SRCU=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_ORION=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_LEDS_TRIGGER_USBPORT=y
CONFIG_USB_PHY=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_MVEBU=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

83
target/linux/mvebu/cortexa53/config-6.1 Normal file
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@ -0,0 +1,83 @@
CONFIG_64BIT=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
CONFIG_ARMADA_37XX_CLK=y
CONFIG_ARMADA_37XX_RWTM_MBOX=y
CONFIG_ARMADA_37XX_WATCHDOG=y
CONFIG_ARMADA_AP806_SYSCON=y
CONFIG_ARMADA_AP_CP_HELPER=y
CONFIG_ARMADA_CP110_SYSCON=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_ARM_MHU_V2 is not set
# CONFIG_ARM_PL172_MPMC is not set
CONFIG_ARM_PSCI_FW=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_FRAME_POINTER=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_PINCONF=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_MAILBOX=y
# CONFIG_MAILBOX_TEST is not set
CONFIG_MFD_SYSCON=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MVEBU_GICP=y
CONFIG_MVEBU_ICU=y
CONFIG_MVEBU_ODMI=y
CONFIG_MVEBU_PIC=y
CONFIG_MVEBU_SEI=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI_AARDVARK=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_PHY_MVEBU_A3700_COMPHY=y
CONFIG_PHY_MVEBU_A3700_UTMI=y
CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_PINCTRL_ARMADA_AP806=y
CONFIG_PINCTRL_ARMADA_CP110=y
CONFIG_POWER_SUPPLY=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_REGULATOR_GPIO=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPI_ARMADA_3700=y
CONFIG_SWIOTLB=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TURRIS_MOX_RWTM=y
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_VMAP_STACK=y
CONFIG_ZONE_DMA32=y

97
target/linux/mvebu/cortexa72/config-6.1 Normal file
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@ -0,0 +1,97 @@
CONFIG_64BIT=y
CONFIG_AQUANTIA_PHY=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1742098=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_SVE=y
# CONFIG_ARM64_TAGGED_ADDR_ABI is not set
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
CONFIG_ARMADA_37XX_CLK=y
CONFIG_ARMADA_AP806_SYSCON=y
CONFIG_ARMADA_AP_CPU_CLK=y
CONFIG_ARMADA_AP_CP_HELPER=y
CONFIG_ARMADA_CP110_SYSCON=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
CONFIG_ARM_ARMADA_8K_CPUFREQ=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
# CONFIG_ARM_PL172_MPMC is not set
CONFIG_ARM_PSCI_FW=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_FRAME_POINTER=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_PINCONF=y
CONFIG_HW_RANDOM_OMAP=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LEDS_IEI_WT61P803_PUZZLE=y
CONFIG_LEDS_IS31FL319X=y
CONFIG_MARVELL_10G_PHY=y
CONFIG_MFD_CORE=y
CONFIG_MFD_IEI_WT61P803_PUZZLE=y
CONFIG_MFD_SYSCON=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MVEBU_GICP=y
CONFIG_MVEBU_ICU=y
CONFIG_MVEBU_ODMI=y
CONFIG_MVEBU_PIC=y
CONFIG_MVEBU_SEI=y
CONFIG_MVPP2=y
CONFIG_MV_XOR_V2=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_ARMADA_8K=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
# CONFIG_PCI_AARDVARK is not set
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_PHY_MVEBU_CP110_COMPHY=y
CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_PINCTRL_ARMADA_AP806=y
CONFIG_PINCTRL_ARMADA_CP110=y
CONFIG_POWER_SUPPLY=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RAS=y
# CONFIG_RAVE_SP_CORE is not set
CONFIG_REGULATOR_GPIO=y
# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SWIOTLB=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_VMAP_STACK=y
CONFIG_ZONE_DMA32=y

3
target/linux/mvebu/cortexa9/config-6.1 Normal file
View file

@ -0,0 +1,3 @@
CONFIG_LED_TRIGGER_PHY=y
CONFIG_PHY_MVEBU_A38X_COMPHY=y
CONFIG_RTC_DRV_MV=y

6
target/linux/mvebu/patches-5.15/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch
View file

@ -28,7 +28,7 @@ Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
--- a/arch/arm/Kconfig --- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig +++ b/arch/arm/Kconfig
@@ -1727,6 +1727,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN @@ -1728,6 +1728,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
The command-line arguments provided by the boot loader will be The command-line arguments provided by the boot loader will be
appended to the the device tree bootargs property. appended to the the device tree bootargs property.
@ -247,7 +247,7 @@ Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
} }
--- a/init/main.c --- a/init/main.c
+++ b/init/main.c +++ b/init/main.c
@@ -114,6 +114,10 @@ @@ -112,6 +112,10 @@
#include <kunit/test.h> #include <kunit/test.h>
@ -258,7 +258,7 @@ Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
static int kernel_init(void *); static int kernel_init(void *);
extern void init_IRQ(void); extern void init_IRQ(void);
@@ -991,6 +995,18 @@ asmlinkage __visible void __init __no_sa @@ -988,6 +992,18 @@ asmlinkage __visible void __init __no_sa
page_alloc_init(); page_alloc_init();
pr_notice("Kernel command line: %s\n", saved_command_line); pr_notice("Kernel command line: %s\n", saved_command_line);

2
target/linux/mvebu/patches-5.15/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch
View file

@ -16,7 +16,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
--- a/MAINTAINERS --- a/MAINTAINERS
+++ b/MAINTAINERS +++ b/MAINTAINERS
@@ -9056,6 +9056,22 @@ F: include/net/nl802154.h @@ -9057,6 +9057,22 @@ F: include/net/nl802154.h
F: net/ieee802154/ F: net/ieee802154/
F: net/mac802154/ F: net/mac802154/

81
target/linux/mvebu/patches-6.1/100-aardvark-workaround-PCIe.patch Normal file
View file

@ -0,0 +1,81 @@
Subject: [PATCH v2] PCI: aardvark: Implement workaround for PCIe Completion Timeout
Date: Tue, 2 Aug 2022 14:38:16 +0200
Message-Id: <20220802123816.21817-1-pali@kernel.org>
X-Mailer: git-send-email 2.20.1
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Precedence: bulk
List-ID: <linux-pci.vger.kernel.org>
X-Mailing-List: linux-pci@vger.kernel.org
Marvell Armada 3700 Functional Errata, Guidelines, and Restrictions
document describes in erratum 3.12 PCIe Completion Timeout (Ref #: 251),
that PCIe IP does not support a strong-ordered model for inbound posted vs.
outbound completion.
As a workaround for this erratum, DIS_ORD_CHK flag in Debug Mux Control
register must be set. It disables the ordering check in the core between
Completions and Posted requests received from the link.
Marvell also suggests to do full memory barrier at the beginning of
aardvark summary interrupt handler before calling interrupt handlers of
endpoint drivers in order to minimize the risk for the race condition
documented in the Erratum between the DMA done status reading and the
completion of writing to the host memory.
More details about this issue and suggested workarounds are in discussion:
https://lore.kernel.org/linux-pci/BN9PR18MB425154FE5019DCAF2028A1D5DB8D9@BN9PR18MB4251.namprd18.prod.outlook.com/t/#u
It was reported that enabling this workaround fixes instability issues and
"Unhandled fault" errors when using 60 GHz WiFi 802.11ad card with Qualcomm
QCA6335 chip under significant load which were caused by interrupt status
stuck in the outbound CMPLT queue traced back to this erratum.
This workaround fixes also kernel panic triggered after some minutes of
usage 5 GHz WiFi 802.11ax card with Mediatek MT7915 chip:
Internal error: synchronous external abort: 96000210 [#1] SMP
Kernel panic - not syncing: Fatal exception in interrupt
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc: stable@vger.kernel.org
---
drivers/pci/controller/pci-aardvark.c | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -212,6 +212,8 @@ enum {
};
#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
+#define DEBUG_MUX_CTRL_REG (LMI_BASE_ADDR + 0x208)
+#define DIS_ORD_CHK BIT(30)
/* PCIe core controller registers */
#define CTRL_CORE_BASE_ADDR 0x18000
@@ -560,6 +562,11 @@ static void advk_pcie_setup_hw(struct ad
PCIE_CORE_CTRL2_TD_ENABLE;
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
+ /* Disable ordering checks, workaround for erratum 3.12 "PCIe completion timeout" */
+ reg = advk_readl(pcie, DEBUG_MUX_CTRL_REG);
+ reg |= DIS_ORD_CHK;
+ advk_writel(pcie, reg, DEBUG_MUX_CTRL_REG);
+
/* Set lane X1 */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
reg &= ~LANE_CNT_MSK;
@@ -1661,6 +1668,9 @@ static irqreturn_t advk_pcie_irq_handler
struct advk_pcie *pcie = arg;
u32 status;
+ /* Full memory barrier (ARM dsb sy), workaround for erratum 3.12 "PCIe completion timeout" */
+ mb();
+
status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
if (!(status & PCIE_IRQ_CORE_INT))
return IRQ_NONE;

118
target/linux/mvebu/patches-6.1/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch Normal file
View file

@ -0,0 +1,118 @@
From 80e643510cb14f116f687e992210c0008a09d869 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Mon, 4 Jul 2022 12:59:53 +0200
Subject: [PATCH] leds: turris-omnia: support HW controlled mode via
private trigger
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add support for enabling MCU controlled mode of the Turris Omnia LEDs
via a LED private trigger called "omnia-mcu".
When in MCU controlled mode, the user can still set LED color, but the
blinking is done by MCU, which does different things for various LEDs:
- WAN LED is blinked according to the LED[0] pin of the WAN PHY
- LAN LEDs are blinked according to the LED[0] output of corresponding
port of the LAN switch
- PCIe LEDs are blinked according to the logical OR of the MiniPCIe port
LED pins
For a long time I wanted to actually do this differently: I wanted to
make the netdev trigger to transparently offload the blinking to the HW
if user set compatible settings for the netdev trigger.
There was some work on this, and hopefully we will be able to complete
it sometime, but since there are various complications, it will probably
not be soon.
In the meantime let's support HW controlled mode via this private LED
trigger. If, in the future, we manage to complete the netdev trigger
offloading, we can still keep this private trigger for backwards
compatiblity, if needed.
We also set "omnia-mcu" to cdev->default_trigger, so that the MCU keeps
control until the user first wants to take over it. If a different
default trigger is specified in device-tree via the
`linux,default-trigger` property, LED class will overwrite
cdev->default_trigger, and so the DT property will be respected.
Signed-off-by: Marek Behún <kabel@kernel.org>
---
drivers/leds/Kconfig | 1 +
drivers/leds/leds-turris-omnia.c | 41 ++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+)
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -163,6 +163,7 @@ config LEDS_TURRIS_OMNIA
depends on I2C
depends on MACH_ARMADA_38X || COMPILE_TEST
depends on OF
+ select LEDS_TRIGGERS
help
This option enables basic support for the LEDs found on the front
side of CZ.NIC's Turris Omnia router. There are 12 RGB LEDs on the
--- a/drivers/leds/leds-turris-omnia.c
+++ b/drivers/leds/leds-turris-omnia.c
@@ -41,6 +41,39 @@ struct omnia_leds {
struct omnia_led leds[];
};
+static struct led_hw_trigger_type omnia_hw_trigger_type;
+
+static int omnia_hwtrig_activate(struct led_classdev *cdev)
+{
+ struct omnia_leds *leds = dev_get_drvdata(cdev->dev->parent);
+ struct omnia_led *led = to_omnia_led(lcdev_to_mccdev(cdev));
+
+ /* put the LED into MCU controlled mode */
+ return i2c_smbus_write_byte_data(leds->client, CMD_LED_MODE,
+ CMD_LED_MODE_LED(led->reg));
+}
+
+static void omnia_hwtrig_deactivate(struct led_classdev *cdev)
+{
+ struct omnia_leds *leds = dev_get_drvdata(cdev->dev->parent);
+ struct omnia_led *led = to_omnia_led(lcdev_to_mccdev(cdev));
+ int ret;
+
+ /* put the LED into software mode */
+ ret = i2c_smbus_write_byte_data(leds->client, CMD_LED_MODE,
+ CMD_LED_MODE_LED(led->reg) |
+ CMD_LED_MODE_USER);
+ if (ret < 0)
+ dev_err(cdev->dev, "Cannot put to software mode: %i\n", ret);
+}
+
+static struct led_trigger omnia_hw_trigger = {
+ .name = "omnia-mcu",
+ .activate = omnia_hwtrig_activate,
+ .deactivate = omnia_hwtrig_deactivate,
+ .trigger_type = &omnia_hw_trigger_type,
+};
+
static int omnia_led_brightness_set_blocking(struct led_classdev *cdev,
enum led_brightness brightness)
{
@@ -112,6 +145,8 @@ static int omnia_led_register(struct i2c
cdev = &led->mc_cdev.led_cdev;
cdev->max_brightness = 255;
cdev->brightness_set_blocking = omnia_led_brightness_set_blocking;
+ cdev->trigger_type = &omnia_hw_trigger_type;
+ cdev->default_trigger = omnia_hw_trigger.name;
/* put the LED into software mode */
ret = i2c_smbus_write_byte_data(client, CMD_LED_MODE,
@@ -228,6 +263,12 @@ static int omnia_leds_probe(struct i2c_c
mutex_init(&leds->lock);
+ ret = devm_led_trigger_register(dev, &omnia_hw_trigger);
+ if (ret < 0) {
+ dev_err(dev, "Cannot register private LED trigger: %d\n", ret);
+ return ret;
+ }
+
led = &leds->leds[0];
for_each_available_child_of_node(np, child) {
ret = omnia_led_register(client, led, child);

33
target/linux/mvebu/patches-6.1/103-leds-turris-omnia-initialize-multi-intensity-to-full.patch Normal file
View file

@ -0,0 +1,33 @@
From bda176cceb735b9b46c1900658b6486c34e13ae6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Mon, 4 Jul 2022 12:59:54 +0200
Subject: [PATCH] leds: turris-omnia: initialize multi-intensity to full
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The default color of each LED before driver probe (255, 255, 255).
Initialize multi_intensity to this value, so that it corresponds to the
reality.
Signed-off-by: Marek Behún <kabel@kernel.org>
---
drivers/leds/leds-turris-omnia.c | 3 +++
1 file changed, 3 insertions(+)
--- a/drivers/leds/leds-turris-omnia.c
+++ b/drivers/leds/leds-turris-omnia.c
@@ -131,10 +131,13 @@ static int omnia_led_register(struct i2c
}
led->subled_info[0].color_index = LED_COLOR_ID_RED;
+ led->subled_info[0].intensity = 255;
led->subled_info[0].channel = 0;
led->subled_info[1].color_index = LED_COLOR_ID_GREEN;
+ led->subled_info[1].intensity = 255;
led->subled_info[1].channel = 1;
led->subled_info[2].color_index = LED_COLOR_ID_BLUE;
+ led->subled_info[2].intensity = 255;
led->subled_info[2].channel = 2;
led->mc_cdev.subled_info = led->subled_info;

31
target/linux/mvebu/patches-6.1/104-leds-turris-omnia-change-max-brightness-from-255-to-.patch Normal file
View file

@ -0,0 +1,31 @@
From 349cbe949b9622cc05b148ecfa6268cbbae35b45 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
Date: Mon, 4 Jul 2022 12:59:55 +0200
Subject: [PATCH] leds: turris-omnia: change max brightness from 255 to 1
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Using binary brightness makes more sense for this controller, because
internally in the MCU it works that way: the LED has a color, and a
state whether it is ON or OFF.
The resulting brightness computation with led_mc_calc_color_components()
will now always result in either (0, 0, 0) or the multi_intensity value.
Signed-off-by: Marek Behún <kabel@kernel.org>
---
drivers/leds/leds-turris-omnia.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/leds/leds-turris-omnia.c
+++ b/drivers/leds/leds-turris-omnia.c
@@ -146,7 +146,7 @@ static int omnia_led_register(struct i2c
init_data.fwnode = &np->fwnode;
cdev = &led->mc_cdev.led_cdev;
- cdev->max_brightness = 255;
+ cdev->max_brightness = 1;
cdev->brightness_set_blocking = omnia_led_brightness_set_blocking;
cdev->trigger_type = &omnia_hw_trigger_type;
cdev->default_trigger = omnia_hw_trigger.name;

15
target/linux/mvebu/patches-6.1/105-power-reset-linkstation-poweroff-add-ls220de.patch Normal file
View file

@ -0,0 +1,15 @@
--- a/drivers/power/reset/linkstation-poweroff.c
+++ b/drivers/power/reset/linkstation-poweroff.c
@@ -142,6 +142,12 @@ static void linkstation_poweroff(void)
}
static const struct of_device_id ls_poweroff_of_match[] = {
+ { .compatible = "buffalo,ls220d",
+ .data = &linkstation_power_off_cfg,
+ },
+ { .compatible = "buffalo,ls220de",
+ .data = &linkstation_power_off_cfg,
+ },
{ .compatible = "buffalo,ls421d",
.data = &linkstation_power_off_cfg,
},

279
target/linux/mvebu/patches-6.1/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch Normal file
View file

@ -0,0 +1,279 @@
From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
From: Adrian Panella <ianchi74@outlook.com>
Date: Thu, 9 Mar 2017 09:37:17 +0100
Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
The command-line arguments provided by the boot loader will be
appended to a new device tree property: bootloader-args.
If there is a property "append-rootblock" in DT under /chosen
and a root= option in bootloaders command line it will be parsed
and added to DT bootargs with the form: <append-rootblock>XX.
Only command line ATAG will be processed, the rest of the ATAGs
sent by bootloader will be ignored.
This is usefull in dual boot systems, to get the current root partition
without afecting the rest of the system.
Signed-off-by: Adrian Panella <ianchi74@outlook.com>
This patch has been modified to be mvebu specific. The original patch
did not pass the bootloader cmdline on if no append-rootblock stanza
was found, resulting in blank cmdline and failure to boot.
Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
---
arch/arm/Kconfig | 11 ++++
arch/arm/boot/compressed/atags_to_fdt.c | 85 ++++++++++++++++++++++++-
init/main.c | 16 +++++
3 files changed, 111 insertions(+), 1 deletion(-)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1587,6 +1587,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
The command-line arguments provided by the boot loader will be
appended to the the device tree bootargs property.
+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
+ bool "Append rootblock parsing bootloader's kernel arguments"
+ help
+ The command-line arguments provided by the boot loader will be
+ appended to a new device tree property: bootloader-args.
+ If there is a property "append-rootblock" in DT under /chosen
+ and a root= option in bootloaders command line it will be parsed
+ and added to DT bootargs with the form: <append-rootblock>XX.
+ Only command line ATAG will be processed, the rest of the ATAGs
+ sent by bootloader will be ignored.
+
endchoice
config CMDLINE
--- a/arch/arm/boot/compressed/atags_to_fdt.c
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -5,6 +5,8 @@
#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
#define do_extend_cmdline 1
+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+#define do_extend_cmdline 1
#else
#define do_extend_cmdline 0
#endif
@@ -20,6 +22,7 @@ static int node_offset(void *fdt, const
return offset;
}
+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
static int setprop(void *fdt, const char *node_path, const char *property,
void *val_array, int size)
{
@@ -28,6 +31,7 @@ static int setprop(void *fdt, const char
return offset;
return fdt_setprop(fdt, offset, property, val_array, size);
}
+#endif
static int setprop_string(void *fdt, const char *node_path,
const char *property, const char *string)
@@ -38,6 +42,7 @@ static int setprop_string(void *fdt, con
return fdt_setprop_string(fdt, offset, property, string);
}
+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
static int setprop_cell(void *fdt, const char *node_path,
const char *property, uint32_t val)
{
@@ -46,6 +51,7 @@ static int setprop_cell(void *fdt, const
return offset;
return fdt_setprop_cell(fdt, offset, property, val);
}
+#endif
static const void *getprop(const void *fdt, const char *node_path,
const char *property, int *len)
@@ -58,6 +64,7 @@ static const void *getprop(const void *f
return fdt_getprop(fdt, offset, property, len);
}
+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
static uint32_t get_cell_size(const void *fdt)
{
int len;
@@ -69,6 +76,74 @@ static uint32_t get_cell_size(const void
return cell_size;
}
+#endif
+
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+
+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
+{
+ const char *ptr, *end;
+ const char *root="root=";
+ int i, l;
+ const char *rootblock;
+
+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
+ ptr = str - 1;
+
+ do {
+ //first find an 'r' at the begining or after a space
+ do {
+ ptr++;
+ ptr = strchr(ptr, 'r');
+ if (!ptr)
+ goto no_append;
+
+ } while (ptr != str && *(ptr-1) != ' ');
+
+ //then check for the rest
+ for(i = 1; i <= 4; i++)
+ if(*(ptr+i) != *(root+i)) break;
+
+ } while (i != 5);
+
+ end = strchr(ptr, ' ');
+ end = end ? (end - 1) : (strchr(ptr, 0) - 1);
+
+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
+ ptr = end + 1;
+
+ /* if append-rootblock property is set use it to append to command line */
+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
+ if (rootblock == NULL)
+ goto no_append;
+
+ if (*dest != ' ') {
+ *dest = ' ';
+ dest++;
+ len++;
+ }
+
+ if (len + l + i <= COMMAND_LINE_SIZE) {
+ memcpy(dest, rootblock, l);
+ dest += l - 1;
+ memcpy(dest, ptr, i);
+ dest += i;
+ }
+
+ return dest;
+
+no_append:
+ len = strlen(str);
+ if (len + 1 < COMMAND_LINE_SIZE) {
+ memcpy(dest, str, len);
+ dest += len;
+ }
+
+ return dest;
+}
+#endif
+
static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
{
char cmdline[COMMAND_LINE_SIZE];
@@ -88,18 +163,28 @@ static void merge_fdt_bootargs(void *fdt
/* and append the ATAG_CMDLINE */
if (fdt_cmdline) {
+
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+ //save original bootloader args
+ //and append ubi.mtd with root partition number to current cmdline
+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
+
+#else
len = strlen(fdt_cmdline);
if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
*ptr++ = ' ';
memcpy(ptr, fdt_cmdline, len);
ptr += len;
}
+#endif
}
*ptr = '\0';
setprop_string(fdt, "/chosen", "bootargs", cmdline);
}
+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
static void hex_str(char *out, uint32_t value)
{
uint32_t digit;
@@ -117,6 +202,7 @@ static void hex_str(char *out, uint32_t
}
*out = '\0';
}
+#endif
/*
* Convert and fold provided ATAGs into the provided FDT.
@@ -131,9 +217,11 @@ int atags_to_fdt(void *atag_list, void *
struct tag *atag = atag_list;
/* In the case of 64 bits memory size, need to reserve 2 cells for
* address and size for each bank */
+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
__be32 mem_reg_property[2 * 2 * NR_BANKS];
- int memcount = 0;
- int ret, memsize;
+ int memsize, memcount = 0;
+#endif
+ int ret;
/* make sure we've got an aligned pointer */
if ((u32)atag_list & 0x3)
@@ -168,7 +256,9 @@ int atags_to_fdt(void *atag_list, void *
else
setprop_string(fdt, "/chosen", "bootargs",
atag->u.cmdline.cmdline);
- } else if (atag->hdr.tag == ATAG_MEM) {
+ }
+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
+ else if (atag->hdr.tag == ATAG_MEM) {
if (memcount >= sizeof(mem_reg_property)/4)
continue;
if (!atag->u.mem.size)
@@ -212,6 +302,10 @@ int atags_to_fdt(void *atag_list, void *
setprop(fdt, "/memory", "reg", mem_reg_property,
4 * memcount * memsize);
}
+#else
+
+ }
+#endif
return fdt_pack(fdt);
}
--- a/init/main.c
+++ b/init/main.c
@@ -112,6 +112,10 @@
#include <kunit/test.h>
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+#include <linux/of.h>
+#endif
+
static int kernel_init(void *);
extern void init_IRQ(void);
@@ -989,6 +993,18 @@ asmlinkage __visible void __init __no_sa
page_alloc_init();
pr_notice("Kernel command line: %s\n", saved_command_line);
+
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+ //Show bootloader's original command line for reference
+ if(of_chosen) {
+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
+ if(prop)
+ pr_notice("Bootloader command line (ignored): %s\n", prop);
+ else
+ pr_notice("Bootloader command line not present\n");
+ }
+#endif
+
/* parameters may set static keys */
jump_label_init();
parse_early_param();

10
target/linux/mvebu/patches-6.1/301-mvebu-armada-38x-enable-libata-leds.patch Normal file
View file

@ -0,0 +1,10 @@
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -66,6 +66,7 @@ config MACH_ARMADA_38X
select HAVE_ARM_TWD if SMP
select MACH_MVEBU_V7
select PINCTRL_ARMADA_38X
+ select ARCH_WANT_LIBATA_LEDS
help
Say 'Y' here if you want your kernel to support boards based
on the Marvell Armada 380/385 SoC with device tree.

770
target/linux/mvebu/patches-6.1/302-add_powertables.patch Normal file
View file

@ -0,0 +1,770 @@
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -214,11 +214,19 @@
&pcie1 {
/* Marvell 88W8864, 5GHz-only */
status = "okay";
+
+ mwlwifi {
+ marvell,2ghz = <0>;
+ };
};
&pcie2 {
/* Marvell 88W8864, 2GHz-only */
status = "okay";
+
+ mwlwifi {
+ marvell,5ghz = <0>;
+ };
};
&pinctrl {
--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
@@ -142,3 +142,205 @@
};
};
};
+
+&pcie1 {
+ mwlwifi {
+ marvell,chainmask = <2 2>;
+ marvell,powertable {
+ AU =
+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
+ <149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>;
+ CA =
+ <36 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
+ <40 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
+ <44 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
+ <48 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
+ CN =
+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <149 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x11 0x11 0x11 0x11 0 0xf>,
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x16 0x16 0x16 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>;
+ ETSI =
+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
+ <149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>;
+ FCC =
+ <36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
+ };
+ };
+};
+
+&pcie2 {
+ mwlwifi {
+ marvell,chainmask = <2 2>;
+ marvell,powertable {
+ AU =
+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
+ CA =
+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>,
+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>;
+ CN =
+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
+ ETSI =
+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
+ FCC =
+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>;
+ };
+ };
+};
--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
@@ -142,3 +142,205 @@
};
};
};
+
+&pcie1 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ AU =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
+ CA =
+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
+ CN =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
+ ETSI =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
+ FCC =
+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
+ };
+ };
+};
+
+&pcie2 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ AU =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ CA =
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
+ CN =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ ETSI =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ FCC =
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
+ };
+ };
+};
--- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
@@ -142,3 +142,205 @@
};
};
};
+
+&pcie1 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ AU =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
+ CA =
+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
+ CN =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
+ ETSI =
+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
+ FCC =
+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
+ };
+ };
+};
+
+&pcie2 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ AU =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ CA =
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
+ CN =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ ETSI =
+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
+ FCC =
+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
+ };
+ };
+};
--- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
@@ -157,6 +157,18 @@
};
};
+&pcie1 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ };
+};
+
+&pcie2 {
+ mwlwifi {
+ marvell,chainmask = <4 4>;
+ };
+};
+
&sdhci {
pinctrl-names = "default";
pinctrl-0 = <&sdhci_pins>;
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -223,12 +223,100 @@
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
+
+ mwlwifi {
+ marvell,5ghz = <0>;
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ FCC =
+ <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>;
+
+ ETSI =
+ <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
+ <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>;
+ };
+ };
};
/* Second mini-PCIe port */
pcie@3,0 {
/* Port 0, Lane 3 */
status = "okay";
+
+ mwlwifi {
+ marvell,2ghz = <0>;
+ marvell,chainmask = <4 4>;
+ marvell,powertable {
+ FCC =
+ <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
+ <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
+ <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
+ <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
+ <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
+ <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
+ <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
+ <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
+ <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
+ <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>;
+
+ ETSI =
+ <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
+ <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>;
+ };
+ };
};
};

15
target/linux/mvebu/patches-6.1/304-revert_i2c_delay.patch Normal file
View file

@ -0,0 +1,15 @@
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -237,12 +237,10 @@
};
&i2c0 {
- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
};
&i2c1 {
- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};

19
target/linux/mvebu/patches-6.1/305-armada-385-rd-mtd-partitions.patch Normal file
View file

@ -0,0 +1,19 @@
--- a/arch/arm/boot/dts/armada-388-rd.dts
+++ b/arch/arm/boot/dts/armada-388-rd.dts
@@ -103,6 +103,16 @@
compatible = "st,m25p128", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
+
+ partition@0 {
+ label = "uboot";
+ reg = <0 0x400000>;
+ };
+
+ partition@1 {
+ label = "firmware";
+ reg = <0x400000 0xc00000>;
+ };
};
};

35
target/linux/mvebu/patches-6.1/306-ARM-mvebu-385-ap-Add-partitions.patch Normal file
View file

@ -0,0 +1,35 @@
From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001
From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Tue, 13 Jan 2015 11:14:09 +0100
Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/armada-385-db-ap.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
@@ -218,19 +218,19 @@
#size-cells = <1>;
partition@0 {
- label = "U-Boot";
+ label = "u-boot";
reg = <0x00000000 0x00800000>;
read-only;
};
partition@800000 {
- label = "uImage";
+ label = "kernel";
reg = <0x00800000 0x00400000>;
read-only;
};
partition@c00000 {
- label = "Root";
+ label = "ubi";
reg = <0x00c00000 0x3f400000>;
};
};

10
target/linux/mvebu/patches-6.1/307-armada-xp-linksys-mamba-broken-idle.patch Normal file
View file

@ -0,0 +1,10 @@
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -483,3 +483,7 @@
};
};
};
+
+&coherencyfab {
+ broken-idle;
+};

11
target/linux/mvebu/patches-6.1/308-armada-xp-linksys-mamba-wan.patch Normal file
View file

@ -0,0 +1,11 @@
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -385,7 +385,7 @@
port@4 {
reg = <4>;
- label = "internet";
+ label = "wan";
};
port@5 {

50
target/linux/mvebu/patches-6.1/309-linksys-status-led.patch Normal file
View file

@ -0,0 +1,50 @@
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -14,6 +14,13 @@
compatible = "linksys,armada385", "marvell,armada385",
"marvell,armada380";
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -71,7 +78,7 @@
pinctrl-0 = <&gpio_leds_pins>;
pinctrl-names = "default";
- power {
+ led_power: power {
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -26,6 +26,13 @@
compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
"marvell,armadaxp", "marvell,armada-370-xp";
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = &uart0;
@@ -195,7 +202,7 @@
pinctrl-0 = <&power_led_pin>;
pinctrl-names = "default";
- power {
+ led_power: power {
label = "mamba:white:power";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
default-state = "on";

25
target/linux/mvebu/patches-6.1/310-linksys-use-eth0-as-cpu-port.patch Normal file
View file

@ -0,0 +1,25 @@
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -116,7 +116,7 @@
};
&eth2 {
- status = "okay";
+ status = "disabled";
phy-mode = "sgmii";
buffer-manager = <&bm>;
bm,pool-long = <2>;
@@ -200,10 +200,10 @@
label = "wan";
};
- port@5 {
- reg = <5>;
+ port@6 {
+ reg = <6>;
label = "cpu";
- ethernet = <&eth2>;
+ ethernet = <&eth0>;
fixed-link {
speed = <1000>;

68
target/linux/mvebu/patches-6.1/311-adjust-compatible-for-linksys.patch Normal file
View file

@ -0,0 +1,68 @@
--- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
@@ -12,8 +12,8 @@
/ {
model = "Linksys WRT3200ACM";
- compatible = "linksys,rango", "linksys,armada385", "marvell,armada385",
- "marvell,armada380";
+ compatible = "linksys,wrt3200acm", "linksys,rango", "linksys,armada385",
+ "marvell,armada385", "marvell,armada380";
};
&expander0 {
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -22,9 +22,10 @@
#include "armada-xp-mv78230.dtsi"
/ {
- model = "Linksys WRT1900AC";
- compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
- "marvell,armadaxp", "marvell,armada-370-xp";
+ model = "Linksys WRT1900AC v1";
+ compatible = "linksys,wrt1900ac-v1", "linksys,mamba",
+ "marvell,armadaxp-mv78230", "marvell,armadaxp",
+ "marvell,armada-370-xp";
aliases {
led-boot = &led_power;
--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
@@ -9,8 +9,9 @@
#include "armada-385-linksys.dtsi"
/ {
- model = "Linksys WRT1900ACv2";
- compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385",
+ model = "Linksys WRT1900AC v2";
+ compatible = "linksys,wrt1900ac-v2", "linksys,cobra",
+ "linksys,armada385", "marvell,armada385",
"marvell,armada380";
};
--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
@@ -10,8 +10,8 @@
/ {
model = "Linksys WRT1200AC";
- compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385",
- "marvell,armada380";
+ compatible = "linksys,wrt1200ac", "linksys,caiman", "linksys,armada385",
+ "marvell,armada385", "marvell,armada380";
};
&expander0 {
--- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
@@ -10,7 +10,8 @@
/ {
model = "Linksys WRT1900ACS";
- compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385",
+ compatible = "linksys,wrt1900acs", "linksys,shelby",
+ "linksys,armada385", "marvell,armada385",
"marvell,armada380";
};

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