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Merge branch 'openwrt:master' into master

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Hayzam Sherif 2023-09-29 07:11:28 +05:30 committed by GitHub
commit 7b38455b95
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78 changed files with 2217 additions and 6445 deletions
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29
package/base-files/files/bin/ipcalc.sh
View file

@ -50,27 +50,37 @@ BEGIN {
network=and(ipaddr,netmask)
prefix=32-bitcount(compl32(netmask))
broadcast=or(network,compl32(netmask))
print "IP="int2ip(ipaddr)
print "NETMASK="int2ip(netmask)
print "BROADCAST="int2ip(broadcast)
print "NETWORK="int2ip(network)
if (prefix<=30) {
broadcast=or(network,compl32(netmask))
print "BROADCAST="int2ip(broadcast)
}
print "PREFIX="prefix
# range calculations:
# ipcalc <ip> <netmask> <start> <num>
# ipcalc <ip> <netmask> <range_start> <range_size>
if (ARGC <= 3)
exit(0)
if (prefix<=30)
limit=network+1
else
limit=network
start=or(network,and(ip2int(ARGV[3]),compl32(netmask)))
limit=network+1
if (start<limit) start=limit
if (start==ipaddr) start=ipaddr+1
end=start+ARGV[4]
limit=or(network,compl32(netmask))-1
if (prefix<=30)
limit=or(network,compl32(netmask))-1
else
limit=or(network,compl32(netmask))
end=start+ARGV[4]-1
if (end>limit) end=limit
if (end==ipaddr) end=ipaddr-1
@ -79,9 +89,10 @@ BEGIN {
exit(1)
}
if (ipaddr > start && ipaddr < end) {
print "ipaddr inside range" > "/dev/stderr"
exit(1)
if (ipaddr >= start && ipaddr <= end) {
print "warning: ipaddr inside range - this might not be supported in future releases of Openwrt" > "/dev/stderr"
# turn this into an error after Openwrt 24 has been released
# exit(1)
}
print "START="int2ip(start)

5
package/base-files/files/lib/functions.sh
View file

@ -315,6 +315,11 @@ include() {
done
}
ipcalc() {
set -- $(ipcalc.sh "$@")
[ $? -eq 0 ] && export -- "$@"
}
find_mtd_index() {
local PART="$(grep "\"$1\"" /proc/mtd | awk -F: '{print $1}')"
local INDEX="${PART##mtd}"

1
package/boot/at91bootstrap/Makefile
View file

@ -13,6 +13,7 @@ PKG_VERSION:=v4.0.3
PKG_MIRROR_HASH:=1ecdc31a13350fcdcaa3f77ed8ad73906f79fc668dbb2f337e1d5dd877bf9882
PKG_SOURCE_VERSION:=1d9e673698d9db4a4f2301559f481274de2e75ae
BINARIES_DIR:=build/binaries
PKG_CPE_ID:=cpe:/a:linux4sam:at91bootstrap
AT91BOOTSTRAP_V4=y
ifdef CONFIG_PACKAGE_at91bootstrap-sama5d4_xplaineddf_uboot_secure

4
package/boot/uboot-envtools/files/mediatek_filogic
View file

@ -40,6 +40,10 @@ bananapi,bpi-r3)
glinet,gl-mt3000)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x20000"
;;
glinet,gl-mt6000)
local envdev=$(find_mmc_part "u-boot-env")
ubootenv_add_uci_config "$envdev" "0x0" "0x80000"
;;
mercusys,mr90x-v1)
local envdev=/dev/mtd$(find_mtd_index "u-boot-env")
ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x20000" "1"

13
package/boot/uboot-mediatek/Makefile
View file

@ -357,6 +357,18 @@ define U-Boot/mt7986_bananapi_bpi-r3-nor
FIP_COMPRESS:=1
endef
define U-Boot/mt7986_glinet_gl-mt6000
NAME:=GL.iNet GL-MT6000
BUILD_SUBTARGET:=filogic
BUILD_DEVICES:=glinet_gl-mt6000
UBOOT_CONFIG:=mt7986a_glinet_gl-mt6000
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=emmc
BL2_SOC:=mt7986
BL2_DDRTYPE:=ddr4
DEPENDS:=+trusted-firmware-a-mt7986-emmc-ddr4
endef
define U-Boot/mt7986_tplink_tl-xdr4288
NAME:=TP-LINK TL-XDR4288
BUILD_SUBTARGET:=filogic
@ -496,6 +508,7 @@ UBOOT_TARGETS := \
mt7986_bananapi_bpi-r3-sdmmc \
mt7986_bananapi_bpi-r3-snand \
mt7986_bananapi_bpi-r3-nor \
mt7986_glinet_gl-mt6000 \
mt7986_tplink_tl-xdr4288 \
mt7986_tplink_tl-xdr6086 \
mt7986_tplink_tl-xdr6088 \

270
package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch
View file

@ -1,4 +1,4 @@
From a3c5878599d530330027412eb8be12f816ac215c Mon Sep 17 00:00:00 2001
From 8d0665327819c41fce2c8d50f19c967b22eae564 Mon Sep 17 00:00:00 2001
From: Weijie Gao <weijie.gao@mediatek.com>
Date: Wed, 27 Jul 2022 16:36:13 +0800
Subject: [PATCH 57/71] mtd: spi-nand: backport from upstream kernel
@ -7,30 +7,34 @@ Backport new features from upstream kernel
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
drivers/mtd/nand/spi/Kconfig | 8 +
drivers/mtd/nand/spi/core.c | 101 ++++++----
drivers/mtd/nand/spi/Kconfig | 1 +
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c | 102 ++++++----
drivers/mtd/nand/spi/etron.c | 181 +++++++++++++++++
drivers/mtd/nand/spi/gigadevice.c | 322 ++++++++++++++++++++++++++----
drivers/mtd/nand/spi/macronix.c | 173 +++++++++++++---
drivers/mtd/nand/spi/micron.c | 50 ++---
drivers/mtd/nand/spi/toshiba.c | 66 +++---
drivers/mtd/nand/spi/winbond.c | 171 +++++++++++++---
include/linux/mtd/spinand.h | 86 +++++---
8 files changed, 753 insertions(+), 224 deletions(-)
drivers/mtd/nand/spi/winbond.c | 164 ++++++++++++---
include/linux/mtd/spinand.h | 87 +++++---
10 files changed, 923 insertions(+), 225 deletions(-)
create mode 100644 drivers/mtd/nand/spi/etron.c
--- a/drivers/mtd/nand/spi/Kconfig
+++ b/drivers/mtd/nand/spi/Kconfig
@@ -5,3 +5,11 @@ menuconfig MTD_SPI_NAND
@@ -5,3 +5,4 @@ menuconfig MTD_SPI_NAND
select SPI_MEM
help
This is the framework for the SPI NAND device drivers.
+
+config MTD_SPI_NAND_W25N01KV
+ tristate "Winbond W25N01KV Support"
+ select MTD_SPI_NAND
+ default n
+ help
+ Winbond W25N01KV share the same ID with W25N01GV. However, they have
+ different attributes.
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o
+spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o etron.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -17,6 +17,7 @@
@ -75,7 +79,15 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
static int spinand_lock_block(struct spinand_device *spinand, u8 lock)
{
return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock);
@@ -836,24 +826,63 @@ static const struct spinand_manufacturer
@@ -829,6 +819,7 @@ static const struct nand_ops spinand_ops
};
static const struct spinand_manufacturer *spinand_manufacturers[] = {
+ &etron_spinand_manufacturer,
&gigadevice_spinand_manufacturer,
&macronix_spinand_manufacturer,
&micron_spinand_manufacturer,
@@ -836,24 +827,63 @@ static const struct spinand_manufacturer
&winbond_spinand_manufacturer,
};
@ -147,7 +159,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
static int spinand_manufacturer_init(struct spinand_device *spinand)
{
if (spinand->manufacturer->ops->init)
@@ -909,9 +938,9 @@ spinand_select_op_variant(struct spinand
@@ -909,9 +939,9 @@ spinand_select_op_variant(struct spinand
* @spinand: SPI NAND object
* @table: SPI NAND device description table
* @table_size: size of the device description table
@ -159,7 +171,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* entry in the SPI NAND description table. If a match is found, the spinand
* object will be initialized with information provided by the matching
* spinand_info entry.
@@ -920,8 +949,10 @@ spinand_select_op_variant(struct spinand
@@ -920,8 +950,10 @@ spinand_select_op_variant(struct spinand
*/
int spinand_match_and_init(struct spinand_device *spinand,
const struct spinand_info *table,
@ -171,7 +183,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
struct nand_device *nand = spinand_to_nand(spinand);
unsigned int i;
@@ -929,13 +960,17 @@ int spinand_match_and_init(struct spinan
@@ -929,13 +961,17 @@ int spinand_match_and_init(struct spinan
const struct spinand_info *info = &table[i];
const struct spi_mem_op *op;
@ -190,7 +202,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
spinand->select_target = table[i].select_target;
op = spinand_select_op_variant(spinand,
@@ -967,17 +1002,7 @@ static int spinand_detect(struct spinand
@@ -967,17 +1003,7 @@ static int spinand_detect(struct spinand
struct nand_device *nand = spinand_to_nand(spinand);
int ret;
@ -209,6 +221,190 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
if (ret) {
dev_err(spinand->slave->dev, "unknown raw ID %02x %02x %02x %02x\n",
spinand->id.data[0], spinand->id.data[1],
--- /dev/null
+++ b/drivers/mtd/nand/spi/etron.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Etron Technology, Inc.
+ *
+ */
+#ifndef __UBOOT__
+#include <malloc.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/bug.h>
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_ETRON 0xD5
+
+#define STATUS_ECC_LIMIT_BITFLIPS (3 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int etron_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (14 * section) + 72;
+ region->length = 14;
+
+ return 0;
+}
+
+static int etron_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ if (section) {
+ region->offset = 18 * section;
+ region->length = 18;
+ } else {
+ /* section 0 has one byte reserved for bad block mark */
+ region->offset = 2;
+ region->length = 16;
+ }
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops etron_ooblayout = {
+ .ecc = etron_ooblayout_ecc,
+ .rfree = etron_ooblayout_free,
+};
+
+static int etron_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ case STATUS_ECC_HAS_BITFLIPS:
+ return nand->eccreq.strength >> 1;
+
+ case STATUS_ECC_LIMIT_BITFLIPS:
+ return nand->eccreq.strength;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static const struct spinand_info etron_spinand_table[] = {
+ /* EM73C 1Gb 3.3V */
+ SPINAND_INFO("EM73C044VCF",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x25),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ /* EM7xD 2Gb */
+ SPINAND_INFO("EM73D044VCR",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM73D044VCO",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3A),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM78D044VCM",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8E),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ /* EM7xE 4Gb */
+ SPINAND_INFO("EM73E044VCE",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM78E044VCD",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8F),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ /* EM7xF044VCA 8Gb */
+ SPINAND_INFO("EM73F044VCA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
+ NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+ SPINAND_INFO("EM78F044VCA",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x8D),
+ NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)),
+};
+
+static const struct spinand_manufacturer_ops etron_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer etron_spinand_manufacturer = {
+ .id = SPINAND_MFR_ETRON,
+ .name = "Etron",
+ .chips = etron_spinand_table,
+ .nchips = ARRAY_SIZE(etron_spinand_table),
+ .ops = &etron_spinand_manuf_ops,
+};
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -22,8 +22,13 @@
@ -1153,7 +1349,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
};
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -19,6 +19,25 @@
@@ -19,6 +19,23 @@
#define WINBOND_CFG_BUF_READ BIT(3)
@ -1168,18 +1364,16 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+#define W25N01_M02GV_STATUS_ECC_1_BITFLIPS (1 << 4)
+#define W25N01_M02GV_STATUS_ECC_UNCOR_ERROR (2 << 4)
+
+#if IS_ENABLED(CONFIG_MTD_SPI_NAND_W25N01KV)
+#define W25N01KV_STATUS_ECC_MASK (3 << 4)
+#define W25N01KV_STATUS_ECC_NO_BITFLIPS (0 << 4)
+#define W25N01KV_STATUS_ECC_1_3_BITFLIPS (1 << 4)
+#define W25N01KV_STATUS_ECC_4_BITFLIPS (3 << 4)
+#define W25N01KV_STATUS_ECC_UNCOR_ERROR (2 << 4)
+#endif
+
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
@@ -35,6 +54,35 @@ static SPINAND_OP_VARIANTS(update_cache_
@@ -35,6 +52,35 @@ static SPINAND_OP_VARIANTS(update_cache_
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
@ -1215,11 +1409,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
@@ -78,8 +126,63 @@ static int w25m02gv_select_target(struct
@@ -78,8 +124,61 @@ static int w25m02gv_select_target(struct
return spi_mem_exec_op(spinand->slave, &op);
}
+#if IS_ENABLED(CONFIG_MTD_SPI_NAND_W25N01KV)
+static int w25n01kv_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
@ -1242,7 +1435,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+
+ return -EINVAL;
+}
+#endif
+
+static int w25n02kv_n04kv_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
@ -1280,28 +1472,26 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2),
NAND_ECCREQ(1, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
@@ -88,7 +191,19 @@ static const struct spinand_info winbond
@@ -88,7 +187,17 @@ static const struct spinand_info winbond
0,
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
SPINAND_SELECT_TARGET(w25m02gv_select_target)),
- SPINAND_INFO("W25N01GV", 0xAA,
+#if IS_ENABLED(CONFIG_MTD_SPI_NAND_W25N01KV)
+ SPINAND_INFO("W25N01KV",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21),
+ NAND_MEMORG(1, 2048, 96, 64, 1024, 1, 1, 1),
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, w25n01kv_ecc_get_status)),
+#else
+ SPINAND_INFO("W25N01GV",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21),
NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
NAND_ECCREQ(1, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
@@ -96,32 +211,31 @@ static const struct spinand_info winbond
@@ -96,32 +205,30 @@ static const struct spinand_info winbond
&update_cache_variants),
0,
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
@ -1320,7 +1510,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
- /*
- * Winbond SPI NAND read ID need a dummy byte,
- * so the first byte in raw_id is dummy.
+#endif
+ SPINAND_INFO("W25N02KV",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
@ -1358,7 +1547,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
static int winbond_spinand_init(struct spinand_device *spinand)
{
@@ -142,12 +256,13 @@ static int winbond_spinand_init(struct s
@@ -142,12 +249,13 @@ static int winbond_spinand_init(struct s
}
static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
@ -1495,7 +1684,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
int (*init)(struct spinand_device *spinand);
void (*cleanup)(struct spinand_device *spinand);
};
@@ -192,11 +219,16 @@ struct spinand_manufacturer_ops {
@@ -192,15 +219,21 @@ struct spinand_manufacturer_ops {
* struct spinand_manufacturer - SPI NAND manufacturer instance
* @id: manufacturer ID
* @name: manufacturer name
@ -1512,7 +1701,12 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
const struct spinand_manufacturer_ops *ops;
};
@@ -268,7 +300,7 @@ struct spinand_ecc_info {
/* SPI NAND manufacturers */
+extern const struct spinand_manufacturer etron_spinand_manufacturer;
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
extern const struct spinand_manufacturer micron_spinand_manufacturer;
@@ -268,7 +301,7 @@ struct spinand_ecc_info {
*/
struct spinand_info {
const char *model;
@ -1521,7 +1715,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
u32 flags;
struct nand_memory_organization memorg;
struct nand_ecc_req eccreq;
@@ -282,6 +314,13 @@ struct spinand_info {
@@ -282,6 +315,13 @@ struct spinand_info {
unsigned int target);
};
@ -1535,7 +1729,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
#define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
{ \
.read_cache = __read, \
@@ -440,9 +479,10 @@ static inline void spinand_set_ofnode(st
@@ -440,9 +480,10 @@ static inline void spinand_set_ofnode(st
}
#endif /* __UBOOT__ */

274
package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch Normal file
View file

@ -0,0 +1,274 @@
--- /dev/null
+++ b/arch/arm/dts/mt7986a-glinet-gl-mt6000.dts
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "mt7986.dtsi"
+
+/ {
+ model = "GL.iNet GL-MT6000";
+ compatible = "glinet,gl-mt6000", "mediatek,mt7986-emmc-rfb", "mediatek,mt7986";
+
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x40000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ wps {
+ label = "reset";
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_status_blue: green {
+ label = "blue:status";
+ gpios = <&gpio 28 GPIO_ACTIVE_LOW>;
+ };
+
+ led_status_white: blue {
+ label = "white:status";
+ gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+};
+
+&uart0 {
+ mediatek,force-highspeed;
+ status = "okay";
+};
+
+&eth {
+ status = "okay";
+ mediatek,gmac-id = <0>;
+ phy-mode = "2500base-x";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+};
+
+&pinctrl {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "flash";
+ groups = "emmc_51";
+ };
+
+ conf-cmd-dat {
+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+ input-enable;
+ drive-strength = <MTK_DRIVE_4mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ conf-clk {
+ pins = "EMMC_CK";
+ drive-strength = <MTK_DRIVE_6mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ conf-dsl {
+ pins = "EMMC_DSL";
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ conf-rst {
+ pins = "EMMC_RSTB";
+ drive-strength = <MTK_DRIVE_4mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&wmcpu_emi {
+ status = "disabled";
+};
--- /dev/null
+++ b/configs/mt7986a_glinet_gl-mt6000_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x80000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-glinet-gl-mt6000"
+CONFIG_SYS_PROMPT="MT7986> "
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_TARGET_MT7986=y
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_DEBUG_UART_BASE=0x11002000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_MENU_SHOW=y
+CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-glinet-gl-mt6000.dtb"
+CONFIG_LOGLEVEL=7
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_LOG=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
+CONFIG_CMD_UUID=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_SMC=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="glinet_gl-mt6000_env"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+CONFIG_USE_IPADDR=y
+CONFIG_IPADDR="192.168.1.1"
+CONFIG_USE_SERVERIP=y
+CONFIG_SERVERIP="192.168.1.254"
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_CLK=y
+CONFIG_GPIO_HOG=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MTK=y
+CONFIG_PHY_FIXED=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7986=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_STORAGE=y
+CONFIG_HEXDUMP=y
+CONFIG_LMB_MAX_REGIONS=64
--- /dev/null
+++ b/glinet_gl-mt6000_env
@@ -0,0 +1,25 @@
+ipaddr=192.168.1.1
+serverip=192.168.1.254
+loadaddr=0x46000000
+bootdelay=3
+bootfile_bl2=openwrt-mediatek-filogic-glinet_gl-mt6000-preloader.bin
+bootfile_fip=openwrt-mediatek-filogic-glinet_gl-mt6000-bl31-uboot.fip
+bootfile_firmware=openwrt-mediatek-filogic-glinet_gl-mt6000-squashfs-factory.bin
+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
+bootmenu_title= *** U-Boot Boot Menu for GL-iNet GL-MT6000 ***
+bootmenu_0=Startup system (Default).=run boot_system
+bootmenu_1=Load Firmware via TFTP then write to eMMC.=run boot_tftp_firmware ; run bootmenu_confirm_return
+bootmenu_2=Load BL31+U-Boot FIP via TFTP then write to eMMC.=run boot_tftp_write_fip ; run bootmenu_confirm_return
+bootmenu_3=mLoad BL2 preloader via TFTP then write to eMMC.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
+bootmenu_4=Reboot.=reset
+bootmenu_5=Reset all settings to factory defaults.=run reset_factory ; reset
+filesize_to_blk=setexpr cnt $filesize + 0x1ff && setexpr cnt $cnt / 0x200
+mmc_read_kernel=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr $part_addr $image_size
+boot_system=part start mmc 0 kernel part_addr && part size mmc 0 kernel part_size && run mmc_read_kernel && bootm
+boot_tftp_firmware=tftpboot $loadaddr $bootfile_firmware && run emmc_write_firmware
+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip
+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2
+emmc_write_firmware=part start mmc 0 kernel part_addr && run filesize_to_blk && mmc write $loadaddr $part_addr $cnt
+emmc_write_bl2=run filesize_to_blk && test 0x$cnt -le 0x800 && mmc partconf 0 1 1 1 && && mmc write $loadaddr 0x0 0x800 ; mmc partconf 0 1 1 0
+emmc_write_fip=part start mmc 0 fip part_addr && part size mmc 0 fip part_size && run filesize_to_blk && test 0x$cnt -le 0x$part_size && mmc write $loadaddr $part_addr $cnt
+reset_factory=eraseenv && reset

2
package/kernel/mt76/Makefile
View file

@ -586,8 +586,6 @@ define KernelPackage/mt7986-firmware/install
$(PKG_BUILD_DIR)/firmware/mt7986_wm.bin \
$(PKG_BUILD_DIR)/firmware/mt7986_rom_patch_mt7975.bin \
$(PKG_BUILD_DIR)/firmware/mt7986_rom_patch.bin \
$(PKG_BUILD_DIR)/firmware/mt7986_eeprom_mt7975_dual.bin \
$(PKG_BUILD_DIR)/firmware/mt7986_eeprom_mt7976_dual.bin \
$(1)/lib/firmware/mediatek
endef

1
package/libs/popt/Makefile
View file

@ -15,6 +15,7 @@ PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=http://ftp.rpm.org/popt/releases/popt-1.x/
PKG_HASH:=c25a4838fc8e4c1c8aacb8bd620edb3084a3d63bf8987fdad3ca2758c63240f9
PKG_LICENSE:=MIT
PKG_CPE_ID:=cpe:/a:popt_project:popt
PKG_FIXUP:=autoreconf
PKG_REMOVE_FILES:=autogen.sh aclocal.m4

1
package/libs/sysfsutils/Makefile
View file

@ -15,6 +15,7 @@ PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=@SF/linux-diag
PKG_HASH:=e865de2c1f559fff0d3fc936e660c0efaf7afe662064f2fb97ccad1ec28d208a
PKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>
PKG_CPE_ID:=cpe:/a:sysfsutils_project:sysfsutils
PKG_LICENSE:=LGPL-2.1
PKG_LICENSE_FILES:=COPYING cmd/GPL lib/LGPL

2
package/network/config/netifd/Makefile
View file

@ -1,7 +1,7 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=netifd
PKG_RELEASE:=1
PKG_RELEASE:=2
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/netifd.git

6
package/network/config/netifd/files/lib/netifd/dhcp.script
View file

@ -18,13 +18,13 @@ setup_interface () {
proto_add_ipv4_address "$ip" "${subnet:-255.255.255.0}"
# TODO: apply $broadcast
local ip_net
eval "$(ipcalc.sh "$ip/$mask")";ip_net="$NETWORK"
local ip_net IP PREFIX NETWORK NETMASK BROADCAST
ipcalc "$ip/$mask" && ip_net="$NETWORK"
local i
for i in $router; do
local gw_net
eval "$(ipcalc.sh "$i/$mask")";gw_net="$NETWORK"
ipcalc "$i/$mask" && gw_net="$NETWORK"
[ "$ip_net" != "$gw_net" ] && proto_add_ipv4_route "$i" 32 "" "$ip"
proto_add_ipv4_route 0.0.0.0 0 "$i" "$ip"

2
package/network/ipv6/6rd/Makefile
View file

@ -8,7 +8,7 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=6rd
PKG_RELEASE:=12
PKG_RELEASE:=13
PKG_LICENSE:=GPL-2.0
include $(INCLUDE_DIR)/package.mk

4
package/network/ipv6/6rd/files/6rd.sh
View file

@ -40,8 +40,8 @@ proto_6rd_setup() {
# Determine the relay prefix.
local ip4prefixlen="${ip4prefixlen:-0}"
local ip4prefix
eval "$(ipcalc.sh "$ipaddr/$ip4prefixlen")";ip4prefix=$NETWORK
local ip4prefix IP PREFIX NETWORK NETMASK BROADCAST
ipcalc "$ipaddr/$ip4prefixlen" && ip4prefix="$NETWORK"
# Determine our IPv6 address.
local ip6subnet=$(6rdcalc "$ip6prefix/$ip6prefixlen" "$ipaddr/$ip4prefixlen")

2
package/network/services/dnsmasq/Makefile
View file

@ -10,7 +10,7 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=dnsmasq
PKG_UPSTREAM_VERSION:=2.89
PKG_VERSION:=$(subst test,~~test,$(subst rc,~rc,$(PKG_UPSTREAM_VERSION)))
PKG_RELEASE:=4
PKG_RELEASE:=6
PKG_SOURCE:=$(PKG_NAME)-$(PKG_UPSTREAM_VERSION).tar.xz
PKG_SOURCE_URL:=https://thekelleys.org.uk/dnsmasq/

9
package/network/services/dnsmasq/files/dnsmasq.init
View file

@ -1,6 +1,8 @@
#!/bin/sh /etc/rc.common
# Copyright (C) 2007-2012 OpenWrt.org
. /lib/functions.sh
START=19
USE_PROCD=1
@ -509,7 +511,6 @@ dhcp_boot_add() {
dhcp_option_add "$cfg" "$networkid" "$force"
}
dhcp_add() {
local cfg="$1"
local dhcp6range="::"
@ -582,12 +583,8 @@ dhcp_add() {
nettag="${networkid:+set:${networkid},}"
if [ "$limit" -gt 0 ] ; then
limit=$((limit-1))
fi
# make sure the DHCP range is not empty
if [ "$dhcpv4" != "disabled" ] && eval "$(ipcalc.sh "${subnet%%/*}" "$netmask" "$start" "$limit")" ; then
if [ "$dhcpv4" != "disabled" ] && ipcalc "${subnet%%/*}" "$netmask" "$start" "$limit" ; then
[ "$dynamicdhcpv4" = "0" ] && END="static"
xappend "--dhcp-range=$tags$nettag$START,$END,$NETMASK,$leasetime${options:+ $options}"

19
package/network/services/hostapd/files/hostapd.uc
View file

@ -122,6 +122,14 @@ function iface_config_macaddr_list(config)
return macaddr_list;
}
function iface_update_supplicant_macaddr(phy, config)
{
let macaddr_list = [];
for (let i = 0; i < length(config.bss); i++)
push(macaddr_list, config.bss[i].bssid);
ubus.call("wpa_supplicant", "phy_set_macaddr_list", { phy: phy, macaddr: macaddr_list });
}
function iface_restart(phydev, config, old_config)
{
let phy = phydev.name;
@ -142,6 +150,8 @@ function iface_restart(phydev, config, old_config)
bss.bssid = phydev.macaddr_next();
}
iface_update_supplicant_macaddr(phy, config);
let bss = config.bss[0];
let err = wdev_create(phy, bss.ifname, { mode: "ap" });
if (err)
@ -498,14 +508,6 @@ function iface_reload_config(phydev, config, old_config)
return true;
}
function iface_update_supplicant_macaddr(phy, config)
{
let macaddr_list = [];
for (let i = 0; i < length(config.bss); i++)
push(macaddr_list, config.bss[i].bssid);
ubus.call("wpa_supplicant", "phy_set_macaddr_list", { phy: phy, macaddr: macaddr_list });
}
function iface_set_config(phy, config)
{
let old_config = hostapd.data.config[phy];
@ -536,7 +538,6 @@ function iface_set_config(phy, config)
hostapd.printf(`Restart interface for phy ${phy}`);
let ret = iface_restart(phydev, config, old_config);
iface_update_supplicant_macaddr(phy, config);
return ret;
}

2
package/network/services/hostapd/files/wdev.uc
View file

@ -41,7 +41,7 @@ function iface_start(wdev)
wdev_config[key] = wdev[key];
if (!wdev_config.macaddr && wdev.mode != "monitor")
wdev_config.macaddr = phydev.macaddr_next();
wdev_create(phy, ifname, wdev);
wdev_create(phy, ifname, wdev_config);
system([ "ip", "link", "set", "dev", ifname, "up" ]);
if (wdev.freq)
system(`iw dev ${ifname} set freq ${wdev.freq} ${wdev.htmode}`);

27
package/network/services/hostapd/src/src/ap/ucode.c
View file

@ -465,17 +465,10 @@ uc_hostapd_bss_ctrl(uc_vm_t *vm, size_t nargs)
return ucv_string_new_length(reply, reply_len);
}
static uc_value_t *
uc_hostapd_iface_stop(uc_vm_t *vm, size_t nargs)
static void
uc_hostapd_disable_iface(struct hostapd_iface *iface)
{
struct hostapd_iface *iface = uc_fn_thisval("hostapd.iface");
int i;
if (!iface)
return NULL;
switch (iface->state) {
case HAPD_IFACE_ENABLED:
case HAPD_IFACE_DISABLED:
break;
#ifdef CONFIG_ACS
@ -488,9 +481,19 @@ uc_hostapd_iface_stop(uc_vm_t *vm, size_t nargs)
hostapd_disable_iface(iface);
break;
}
}
static uc_value_t *
uc_hostapd_iface_stop(uc_vm_t *vm, size_t nargs)
{
struct hostapd_iface *iface = uc_fn_thisval("hostapd.iface");
int i;
if (!iface)
return NULL;
if (iface->state != HAPD_IFACE_ENABLED)
hostapd_disable_iface(iface);
uc_hostapd_disable_iface(iface);
for (i = 0; i < iface->num_bss; i++) {
struct hostapd_data *hapd = iface->bss[i];
@ -561,8 +564,6 @@ uc_hostapd_iface_start(uc_vm_t *vm, size_t nargs)
out:
switch (iface->state) {
case HAPD_IFACE_DISABLED:
break;
case HAPD_IFACE_ENABLED:
if (!hostapd_is_dfs_required(iface) ||
hostapd_is_dfs_chan_available(iface))
@ -570,7 +571,7 @@ out:
wpa_printf(MSG_INFO, "DFS CAC required on new channel, restart interface");
/* fallthrough */
default:
hostapd_disable_iface(iface);
uc_hostapd_disable_iface(iface);
break;
}

1
package/system/iucode-tool/Makefile
View file

@ -14,6 +14,7 @@ PKG_RELEASE:=2
PKG_SOURCE:=iucode-tool_$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=https://gitlab.com/iucode-tool/releases/raw/latest
PKG_HASH:=12b88efa4d0d95af08db05a50b3dcb217c0eb2bfc67b483779e33d498ddb2f95
PKG_CPE_ID:=cpe:/a:iucode-tool_project:iucode-tool
PKG_BUILD_DEPENDS:=USE_UCLIBC:argp-standalone USE_MUSL:argp-standalone
HOST_BUILD_DEPENDS:=HOST_OS_MACOS:argp-standalone/host

1
target/linux/generic/config-6.1
View file

@ -6989,6 +6989,7 @@ CONFIG_TRAD_SIGNALS=y
# CONFIG_TRUSTED_FOUNDATIONS is not set
# CONFIG_TRUSTED_KEYS is not set
# CONFIG_TRUSTED_KEYS_TPM is not set
# CONFIG_TRUSTED_KEYS_TEE is not set
# CONFIG_TSL2583 is not set
# CONFIG_TSL2591 is not set
# CONFIG_TSL2772 is not set

63
target/linux/generic/pending-5.15/731-net-phy-realtek-support-interrupt-of-RTL8221B.patch Normal file
View file

@ -0,0 +1,63 @@
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -971,6 +971,51 @@ static int rtl8221b_config_init(struct p
return 0;
}
+static int rtl8221b_ack_interrupt(struct phy_device *phydev)
+{
+ int err;
+
+ err = phy_read_mmd(phydev, RTL8221B_MMD_PHY_CTRL, 0xa4d4);
+
+ return (err < 0) ? err : 0;
+}
+
+static int rtl8221b_config_intr(struct phy_device *phydev)
+{
+ int err;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+ err = rtl8221b_ack_interrupt(phydev);
+ if (err)
+ return err;
+
+ err = phy_write_mmd(phydev, RTL8221B_MMD_PHY_CTRL, 0xa4d2, 0x7ff);
+ } else {
+ err = phy_write_mmd(phydev, RTL8221B_MMD_PHY_CTRL, 0xa4d2, 0x0);
+ if (err)
+ return err;
+
+ err = rtl8221b_ack_interrupt(phydev);
+ }
+
+ return err;
+}
+
+static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev)
+{
+ int err;
+
+ err = rtl8221b_ack_interrupt(phydev);
+ if (err) {
+ phy_error(phydev);
+ return IRQ_NONE;
+ }
+
+ phy_trigger_machine(phydev);
+
+ return IRQ_HANDLED;
+}
+
static struct phy_driver realtek_drvs[] = {
{
PHY_ID_MATCH_EXACT(0x00008201),
@@ -1119,6 +1164,8 @@ static struct phy_driver realtek_drvs[]
.get_features = rtl822x_get_features,
.config_init = rtl8221b_config_init,
.config_aneg = rtl822x_config_aneg,
+ .config_intr = rtl8221b_config_intr,
+ .handle_interrupt = rtl8221b_handle_interrupt,
.probe = rtl822x_probe,
.read_status = rtl822x_read_status,
.suspend = genphy_suspend,

63
target/linux/generic/pending-6.1/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch Normal file
View file

@ -0,0 +1,63 @@
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -979,6 +979,51 @@ static int rtl8221b_config_init(struct p
return 0;
}
+static int rtl8221b_ack_interrupt(struct phy_device *phydev)
+{
+ int err;
+
+ err = phy_read_mmd(phydev, RTL8221B_MMD_PHY_CTRL, 0xa4d4);
+
+ return (err < 0) ? err : 0;
+}
+
+static int rtl8221b_config_intr(struct phy_device *phydev)
+{
+ int err;
+
+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+ err = rtl8221b_ack_interrupt(phydev);
+ if (err)
+ return err;
+
+ err = phy_write_mmd(phydev, RTL8221B_MMD_PHY_CTRL, 0xa4d2, 0x7ff);
+ } else {
+ err = phy_write_mmd(phydev, RTL8221B_MMD_PHY_CTRL, 0xa4d2, 0x0);
+ if (err)
+ return err;
+
+ err = rtl8221b_ack_interrupt(phydev);
+ }
+
+ return err;
+}
+
+static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev)
+{
+ int err;
+
+ err = rtl8221b_ack_interrupt(phydev);
+ if (err) {
+ phy_error(phydev);
+ return IRQ_NONE;
+ }
+
+ phy_trigger_machine(phydev);
+
+ return IRQ_HANDLED;
+}
+
static struct phy_driver realtek_drvs[] = {
{
PHY_ID_MATCH_EXACT(0x00008201),
@@ -1139,6 +1184,8 @@ static struct phy_driver realtek_drvs[]
.get_features = rtl822x_get_features,
.config_init = rtl8221b_config_init,
.config_aneg = rtl822x_config_aneg,
+ .config_intr = rtl8221b_config_intr,
+ .handle_interrupt = rtl8221b_handle_interrupt,
.probe = rtl822x_probe,
.read_status = rtl822x_read_status,
.suspend = genphy_suspend,

3
target/linux/ipq40xx/Makefile
View file

@ -8,8 +8,7 @@ CPU_TYPE:=cortex-a7
CPU_SUBTYPE:=neon-vfpv4
SUBTARGETS:=generic chromium mikrotik
KERNEL_PATCHVER:=5.15
KERNEL_TESTING_PATCHVER:=6.1
KERNEL_PATCHVER:=6.1
KERNELNAME:=zImage Image dtbs

3
target/linux/ipq40xx/base-files/etc/board.d/02_network
View file

@ -74,6 +74,9 @@ ipq40xx_setup_interfaces()
devolo,magic-2-wifi-next)
ucidef_set_interface_lan "lan1 lan2 ghn"
;;
extreme-networks,ws-ap391x)
ucidef_set_interfaces_lan_wan "sw-eth1 sw-eth2 sw-eth3 sw-eth5" "sw-eth4"
;;
linksys,whw01)
ucidef_set_interface_lan "eth1 eth2"
;;

6
target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
View file

@ -94,7 +94,8 @@ case "$FIRMWARE" in
caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 2)
;;
extreme-networks,ws-ap3915i)
extreme-networks,ws-ap3915i |\
extreme-networks,ws-ap391x)
caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(mtd_get_mac_ascii CFG1 RADIOADDR0)
;;
@ -189,7 +190,8 @@ case "$FIRMWARE" in
caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 3)
;;
extreme-networks,ws-ap3915i)
extreme-networks,ws-ap3915i |\
extreme-networks,ws-ap391x)
caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(mtd_get_mac_ascii CFG1 RADIOADDR1)
;;

3
target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh
View file

@ -20,7 +20,8 @@ preinit_set_mac_address() {
base_mac=$(cat /sys/class/net/eth0/address)
ip link set dev eth1 address $(macaddr_add "$base_mac" 1)
;;
extreme-networks,ws-ap3915i)
extreme-networks,ws-ap3915i|\
extreme-networks,ws-ap391x)
ip link set dev eth0 address $(mtd_get_mac_ascii CFG1 ethaddr)
;;
linksys,ea8300|\

2
target/linux/ipq40xx/base-files/lib/upgrade/platform.sh
View file

@ -214,7 +214,9 @@ platform_do_upgrade() {
teltonika,rutx10 |\
teltonika,rutx50 |\
zte,mf18a |\
zte,mf282plus |\
zte,mf286d |\
zte,mf287 |\
zte,mf287plus |\
zte,mf287pro |\
zte,mf289f)

509
target/linux/ipq40xx/config-5.15
View file

@ -1,509 +0,0 @@
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_APQ_GCC_8084 is not set
# CONFIG_APQ_MMCC_8084 is not set
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_IPQ40XX=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
# CONFIG_ARCH_MDM9615 is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_ARCH_MSM8960 is not set
# CONFIG_ARCH_MSM8974 is not set
# CONFIG_ARCH_MSM8X60 is not set
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
CONFIG_ARM_CPUIDLE=y
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_ARM_CRYPTO=y
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_AT803X_PHY=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BCH=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BOUNCE=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_CLKSRC_QCOM=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE_PARTITION=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRC8=y
CONFIG_CRYPTO_AES_ARM=y
CONFIG_CRYPTO_AES_ARM_BS=y
CONFIG_CRYPTO_BLAKE2S_ARM=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DEV_QCE=y
# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
CONFIG_CRYPTO_DEV_QCOM_RNG=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA256_ARM=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DEBUG_MISC=y
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_DT_IDLE_STATES=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EEPROM_AT24=y
CONFIG_EXTCON=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_74X164=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_GRO_CELLS=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_OPTEE=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
# CONFIG_I2C_QCOM_CCI is not set
CONFIG_I2C_QUP=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
# CONFIG_IPQ_APSS_PLL is not set
CONFIG_IPQ_GCC_4019=y
# CONFIG_IPQ_GCC_6018 is not set
# CONFIG_IPQ_GCC_806X is not set
# CONFIG_IPQ_GCC_8074 is not set
# CONFIG_IPQ_LCC_806X is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_KMAP_LOCAL=y
CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
# CONFIG_KPSS_XCC is not set
# CONFIG_KRAITCC is not set
CONFIG_LEDS_LP5523=y
CONFIG_LEDS_LP5562=y
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LEDS_TLC591XX=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_IPQ4019=y
# CONFIG_MDM_GCC_9615 is not set
# CONFIG_MDM_LCC_9615 is not set
CONFIG_MEMFD_CREATE=y
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_MFD_QCOM_RPM is not set
# CONFIG_MFD_SPMI_PMIC is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_MSM=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MODULES_USE_ELF_REL=y
# CONFIG_MSM_GCC_8660 is not set
# CONFIG_MSM_GCC_8916 is not set
# CONFIG_MSM_GCC_8939 is not set
# CONFIG_MSM_GCC_8960 is not set
# CONFIG_MSM_GCC_8974 is not set
# CONFIG_MSM_GCC_8994 is not set
# CONFIG_MSM_GCC_8996 is not set
# CONFIG_MSM_GCC_8998 is not set
# CONFIG_MSM_GPUCC_8998 is not set
# CONFIG_MSM_LCC_8960 is not set
# CONFIG_MSM_MMCC_8960 is not set
# CONFIG_MSM_MMCC_8974 is not set
# CONFIG_MSM_MMCC_8996 is not set
# CONFIG_MSM_MMCC_8998 is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_QCOM=y
# CONFIG_MTD_QCOMSMEM_PARTS is not set
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_SPLIT_WRGG_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEON=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_QCA8K_IPQ4019=y
CONFIG_NET_DSA_TAG_IPQ4019=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NLS=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
CONFIG_NVMEM_QCOM_QFPROM=y
# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_QCOM=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
CONFIG_PHY_QCOM_IPQ4019_USB=y
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
# CONFIG_PHY_QCOM_IPQ806X_USB is not set
# CONFIG_PHY_QCOM_PCIE2 is not set
# CONFIG_PHY_QCOM_QMP is not set
# CONFIG_PHY_QCOM_QUSB2 is not set
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
# CONFIG_PHY_QCOM_USB_SS is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_APQ8064 is not set
# CONFIG_PINCTRL_APQ8084 is not set
CONFIG_PINCTRL_IPQ4019=y
# CONFIG_PINCTRL_IPQ6018 is not set
# CONFIG_PINCTRL_IPQ8064 is not set
# CONFIG_PINCTRL_IPQ8074 is not set
# CONFIG_PINCTRL_MDM9615 is not set
CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_MSM8226 is not set
# CONFIG_PINCTRL_MSM8660 is not set
# CONFIG_PINCTRL_MSM8916 is not set
# CONFIG_PINCTRL_MSM8960 is not set
# CONFIG_PINCTRL_MSM8976 is not set
# CONFIG_PINCTRL_MSM8994 is not set
# CONFIG_PINCTRL_MSM8996 is not set
# CONFIG_PINCTRL_MSM8998 is not set
# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
# CONFIG_PINCTRL_QCS404 is not set
# CONFIG_PINCTRL_SC7180 is not set
# CONFIG_PINCTRL_SDM660 is not set
# CONFIG_PINCTRL_SDM845 is not set
# CONFIG_PINCTRL_SM8150 is not set
# CONFIG_PINCTRL_SM8250 is not set
CONFIG_PM_OPP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_POWER_RESET_MSM=y
CONFIG_POWER_SUPPLY=y
CONFIG_PPS=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_QCA807X_PHY=y
CONFIG_QCOM_A53PLL=y
# CONFIG_QCOM_ADM is not set
CONFIG_QCOM_BAM_DMA=y
# CONFIG_QCOM_COMMAND_DB is not set
# CONFIG_QCOM_CPR is not set
# CONFIG_QCOM_EBI2 is not set
# CONFIG_QCOM_GENI_SE is not set
# CONFIG_QCOM_GSBI is not set
# CONFIG_QCOM_HFPLL is not set
# CONFIG_QCOM_IOMMU is not set
CONFIG_QCOM_IPQ4019_ESS_EDMA=y
# CONFIG_QCOM_LLCC is not set
# CONFIG_QCOM_OCMEM is not set
# CONFIG_QCOM_PDC is not set
# CONFIG_QCOM_RMTFS_MEM is not set
# CONFIG_QCOM_RPMH is not set
CONFIG_QCOM_SCM=y
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
CONFIG_QCOM_SMEM=y
# CONFIG_QCOM_SMSM is not set
# CONFIG_QCOM_SOCINFO is not set
CONFIG_QCOM_TCSR=y
# CONFIG_QCOM_TSENS is not set
CONFIG_QCOM_WDT=y
# CONFIG_QCS_GCC_404 is not set
# CONFIG_QCS_Q6SSTOP_404 is not set
# CONFIG_QCS_TURING_404 is not set
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_QCOM_LABIBB is not set
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
CONFIG_REGULATOR_VCTRL=y
CONFIG_REGULATOR_VQMMC_IPQ4019=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_QCOM_AOSS is not set
# CONFIG_RESET_QCOM_PDC is not set
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SC_DISPCC_7180 is not set
# CONFIG_SC_GCC_7180 is not set
# CONFIG_SC_GPUCC_7180 is not set
# CONFIG_SC_LPASS_CORECC_7180 is not set
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SC_VIDEOCC_7180 is not set
# CONFIG_SDM_CAMCC_845 is not set
# CONFIG_SDM_DISPCC_845 is not set
# CONFIG_SDM_GCC_660 is not set
# CONFIG_SDM_GCC_845 is not set
# CONFIG_SDM_GPUCC_845 is not set
# CONFIG_SDM_LPASSCC_845 is not set
# CONFIG_SDM_VIDEOCC_845 is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
# CONFIG_SM_GCC_8150 is not set
# CONFIG_SM_GCC_8250 is not set
# CONFIG_SM_GPUCC_8150 is not set
# CONFIG_SM_GPUCC_8250 is not set
# CONFIG_SM_VIDEOCC_8150 is not set
# CONFIG_SM_VIDEOCC_8250 is not set
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_QUP=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
CONFIG_SPMI_MSM_PMIC_ARB=y
# CONFIG_SPMI_PMIC_CLKDIV is not set
CONFIG_SRCU=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_TEE=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_OF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

1687
target/linux/ipq40xx/files-5.15/drivers/net/dsa/qca/qca8k-ipq4019.c
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target/linux/ipq40xx/files-5.15/drivers/net/dsa/qca/qca8k-ipq4019.h
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@ -1,293 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*/
#ifndef __QCA8K_H
#define __QCA8K_H
#include <linux/regmap.h>
#define QCA8K_NUM_PORTS 6
#define QCA8K_CPU_PORT 0
#define QCA8K_MAX_MTU 9000
#define QCA8K_BUSY_WAIT_TIMEOUT 2000
#define QCA8K_NUM_FDB_RECORDS 2048
#define QCA8K_PORT_VID_DEF 1
/* Global control registers */
#define QCA8K_REG_MASK_CTRL 0x000
#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0)
#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0)
#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
#define QCA8K_REG_RGMII_CTRL 0x004
#define QCA8K_RGMII_CTRL_RGMII_RXC GENMASK(1, 0)
#define QCA8K_RGMII_CTRL_RGMII_TXC GENMASK(9, 8)
/* Some kind of CLK selection
* 0: gcc_ess_dly2ns
* 1: gcc_ess_clk
*/
#define QCA8K_RGMII_CTRL_CLK BIT(10)
#define QCA8K_RGMII_CTRL_DELAY_RMII0 GENMASK(17, 16)
#define QCA8K_RGMII_CTRL_INVERT_RMII0_REF_CLK BIT(18)
#define QCA8K_RGMII_CTRL_DELAY_RMII1 GENMASK(20, 19)
#define QCA8K_RGMII_CTRL_INVERT_RMII1_REF_CLK BIT(21)
#define QCA8K_RGMII_CTRL_INVERT_RMII0_MASTER_EN BIT(24)
#define QCA8K_RGMII_CTRL_INVERT_RMII1_MASTER_EN BIT(25)
#define QCA8K_REG_MODULE_EN 0x030
#define QCA8K_MODULE_EN_MIB BIT(0)
#define QCA8K_REG_MIB 0x034
#define QCA8K_MIB_FLUSH BIT(24)
#define QCA8K_MIB_CPU_KEEP BIT(20)
#define QCA8K_MIB_BUSY BIT(17)
#define QCA8K_GOL_MAC_ADDR0 0x60
#define QCA8K_GOL_MAC_ADDR1 0x64
#define QCA8K_MAX_FRAME_SIZE 0x78
#define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
#define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
#define QCA8K_PORT_STATUS_SPEED_10 0
#define QCA8K_PORT_STATUS_SPEED_100 0x1
#define QCA8K_PORT_STATUS_SPEED_1000 0x2
#define QCA8K_PORT_STATUS_TXMAC BIT(2)
#define QCA8K_PORT_STATUS_RXMAC BIT(3)
#define QCA8K_PORT_STATUS_TXFLOW BIT(4)
#define QCA8K_PORT_STATUS_RXFLOW BIT(5)
#define QCA8K_PORT_STATUS_DUPLEX BIT(6)
#define QCA8K_PORT_STATUS_LINK_UP BIT(8)
#define QCA8K_PORT_STATUS_LINK_AUTO BIT(9)
#define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10)
#define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12)
#define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
#define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
#define QCA8K_PORT_HDR_CTRL_RX_S 2
#define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
#define QCA8K_PORT_HDR_CTRL_TX_S 0
#define QCA8K_PORT_HDR_CTRL_ALL 2
#define QCA8K_PORT_HDR_CTRL_MGMT 1
#define QCA8K_PORT_HDR_CTRL_NONE 0
#define QCA8K_REG_SGMII_CTRL 0x0e0
#define QCA8K_SGMII_EN_PLL BIT(1)
#define QCA8K_SGMII_EN_RX BIT(2)
#define QCA8K_SGMII_EN_TX BIT(3)
#define QCA8K_SGMII_EN_SD BIT(4)
#define QCA8K_SGMII_CLK125M_DELAY BIT(7)
#define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23))
#define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22)
#define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22)
#define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22)
/* EEE control registers */
#define QCA8K_REG_EEE_CTRL 0x100
#define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)
/* ACL registers */
#define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
#define QCA8K_PORT_VLAN_CVID(x) (x << 16)
#define QCA8K_PORT_VLAN_SVID(x) x
#define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
#define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
#define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
/* Lookup registers */
#define QCA8K_REG_ATU_DATA0 0x600
#define QCA8K_ATU_ADDR2_S 24
#define QCA8K_ATU_ADDR3_S 16
#define QCA8K_ATU_ADDR4_S 8
#define QCA8K_REG_ATU_DATA1 0x604
#define QCA8K_ATU_PORT_M 0x7f
#define QCA8K_ATU_PORT_S 16
#define QCA8K_ATU_ADDR0_S 8
#define QCA8K_REG_ATU_DATA2 0x608
#define QCA8K_ATU_VID_M 0xfff
#define QCA8K_ATU_VID_S 8
#define QCA8K_ATU_STATUS_M 0xf
#define QCA8K_ATU_STATUS_STATIC 0xf
#define QCA8K_REG_ATU_FUNC 0x60c
#define QCA8K_ATU_FUNC_BUSY BIT(31)
#define QCA8K_ATU_FUNC_PORT_EN BIT(14)
#define QCA8K_ATU_FUNC_MULTI_EN BIT(13)
#define QCA8K_ATU_FUNC_FULL BIT(12)
#define QCA8K_ATU_FUNC_PORT_M 0xf
#define QCA8K_ATU_FUNC_PORT_S 8
#define QCA8K_REG_VTU_FUNC0 0x610
#define QCA8K_VTU_FUNC0_VALID BIT(20)
#define QCA8K_VTU_FUNC0_IVL_EN BIT(19)
#define QCA8K_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
#define QCA8K_VTU_FUNC0_EG_MODE_MASK 3
#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0
#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG 1
#define QCA8K_VTU_FUNC0_EG_MODE_TAG 2
#define QCA8K_VTU_FUNC0_EG_MODE_NOT 3
#define QCA8K_REG_VTU_FUNC1 0x614
#define QCA8K_VTU_FUNC1_BUSY BIT(31)
#define QCA8K_VTU_FUNC1_VID_S 16
#define QCA8K_VTU_FUNC1_FULL BIT(4)
#define QCA8K_REG_ATU_CTRL 0x618
#define QCA8K_ATU_AGE_TIME_MASK GENMASK(15, 0)
#define QCA8K_ATU_AGE_TIME(x) FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))
#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24
#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16
#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8
#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0
#define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
#define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
#define QCA8K_PORT_LOOKUP_VLAN_MODE GENMASK(9, 8)
#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8)
#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK (1 << 8)
#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK (2 << 8)
#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE (3 << 8)
#define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)
#define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16)
#define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16)
#define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16)
#define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16)
#define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16)
#define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16)
#define QCA8K_PORT_LOOKUP_LEARN BIT(20)
#define QCA8K_PORT_LOOKUP_LOOPBACK BIT(21)
#define QCA8K_REG_GLOBAL_FC_THRESH 0x800
#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16)
#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16)
#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0)
#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0)
#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8)
#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0)
#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0)
#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4)
#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4)
#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8)
#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8)
#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12)
#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12)
#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16)
#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16)
#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20)
#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20)
#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24)
#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24)
#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0)
#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0)
#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6)
#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7)
#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8)
#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
/* Pkt edit registers */
#define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
/* L3 registers */
#define QCA8K_HROUTER_CONTROL 0xe00
#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16)
#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S 16
#define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE 1
#define QCA8K_HROUTER_PBASED_CONTROL1 0xe08
#define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c
#define QCA8K_HNAT_CONTROL 0xe38
/* MIB registers */
#define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100)
/* IPQ4019 PSGMII PHY registers */
#define PSGMIIPHY_MODE_CONTROL 0x1b4
#define PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M BIT(0)
#define PSGMIIPHY_TX_CONTROL 0x288
#define PSGMIIPHY_TX_CONTROL_MAGIC_VALUE 0x8380
#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1 0x9c
#define PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART BIT(14)
#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2 0xa0
#define PSGMIIPHY_REG_PLL_VCO_CALIB_READY BIT(0)
#define QCA8K_PSGMII_CALB_NUM 100
#define MII_QCA8075_SSTATUS 0x11
#define QCA8075_PHY_SPEC_STATUS_LINK BIT(10)
#define QCA8075_MMD7_CRC_AND_PKTS_COUNT 0x8029
#define QCA8075_MMD7_PKT_GEN_PKT_NUMB 0x8021
#define QCA8075_MMD7_PKT_GEN_PKT_SIZE 0x8062
#define QCA8075_MMD7_PKT_GEN_CTRL 0x8020
#define QCA8075_MMD7_CNT_SELFCLR BIT(1)
#define QCA8075_MMD7_CNT_FRAME_CHK_EN BIT(0)
#define QCA8075_MMD7_PKT_GEN_START BIT(13)
#define QCA8075_MMD7_PKT_GEN_INPROGR BIT(15)
#define QCA8075_MMD7_IG_FRAME_RECV_CNT_HI 0x802a
#define QCA8075_MMD7_IG_FRAME_RECV_CNT_LO 0x802b
#define QCA8075_MMD7_IG_FRAME_ERR_CNT 0x802c
#define QCA8075_MMD7_EG_FRAME_RECV_CNT_HI 0x802d
#define QCA8075_MMD7_EG_FRAME_RECV_CNT_LO 0x802e
#define QCA8075_MMD7_EG_FRAME_ERR_CNT 0x802f
#define QCA8075_MMD7_MDIO_BRDCST_WRITE 0x8028
#define QCA8075_MMD7_MDIO_BRDCST_WRITE_EN BIT(15)
#define QCA8075_MDIO_BRDCST_PHY_ADDR 0x1f
#define QCA8075_PKT_GEN_PKTS_COUNT 4096
enum {
QCA8K_PORT_SPEED_10M = 0,
QCA8K_PORT_SPEED_100M = 1,
QCA8K_PORT_SPEED_1000M = 2,
QCA8K_PORT_SPEED_ERR = 3,
};
enum qca8k_fdb_cmd {
QCA8K_FDB_FLUSH = 1,
QCA8K_FDB_LOAD = 2,
QCA8K_FDB_PURGE = 3,
QCA8K_FDB_FLUSH_PORT = 5,
QCA8K_FDB_NEXT = 6,
QCA8K_FDB_SEARCH = 7,
};
enum qca8k_vlan_cmd {
QCA8K_VLAN_FLUSH = 1,
QCA8K_VLAN_LOAD = 2,
QCA8K_VLAN_PURGE = 3,
QCA8K_VLAN_REMOVE_PORT = 4,
QCA8K_VLAN_NEXT = 5,
QCA8K_VLAN_READ = 6,
};
struct ar8xxx_port_status {
int enabled;
};
struct qca8k_priv {
struct regmap *regmap;
struct mii_bus *bus;
struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
struct dsa_switch *ds;
struct mutex reg_mutex;
struct device *dev;
struct dsa_switch_ops ops;
unsigned int port_mtu[QCA8K_NUM_PORTS];
/* IPQ4019 specific */
struct regmap *psgmii;
bool psgmii_calibrated;
struct phy_device *psgmii_ethphy;
};
struct qca8k_mib_desc {
unsigned int size;
unsigned int offset;
const char *name;
};
struct qca8k_fdb {
u16 vid;
u8 port_mask;
u8 aging;
u8 mac[6];
};
#endif /* __QCA8K_H */

8
target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/Makefile
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# SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for the IPQ ESS driver
#
obj-$(CONFIG_QCOM_IPQ4019_ESS_EDMA) += ipq_ess.o
ipq_ess-objs := ipqess.o ipqess_ethtool.o

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target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
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target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess.h
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// SPDX-License-Identifier: (GPL-2.0 OR ISC)
/* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
* Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
* Copyright (c) 2018 - 2019, Christian Lamparter <chunkeey@gmail.com>
* Copyright (c) 2020 - 2021, Gabor Juhos <j4g8y7@gmail.com>
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _IPQESS_H_
#define _IPQESS_H_
#define IPQESS_NETDEV_QUEUES 4
#define IPQESS_TPD_EOP_SHIFT 31
#define IPQESS_PORT_ID_SHIFT 12
#define IPQESS_PORT_ID_MASK 0x7
/* tpd word 3 bit 18-28 */
#define IPQESS_TPD_PORT_BITMAP_SHIFT 18
#define IPQESS_TPD_FROM_CPU_SHIFT 25
#define IPQESS_RX_RING_SIZE 128
#define IPQESS_RX_HEAD_BUFF_SIZE 1540
#define IPQESS_TX_RING_SIZE 128
#define IPQESS_MAX_RX_QUEUE 8
#define IPQESS_MAX_TX_QUEUE 16
/* Configurations */
#define IPQESS_INTR_CLEAR_TYPE 0
#define IPQESS_INTR_SW_IDX_W_TYPE 0
#define IPQESS_FIFO_THRESH_TYPE 0
#define IPQESS_RSS_TYPE 0
#define IPQESS_RX_IMT 0x0020
#define IPQESS_TX_IMT 0x0050
#define IPQESS_TPD_BURST 5
#define IPQESS_TXF_BURST 0x100
#define IPQESS_RFD_BURST 8
#define IPQESS_RFD_THR 16
#define IPQESS_RFD_LTHR 0
/* Flags used in transmit direction */
#define IPQESS_DESC_LAST 0x1
#define IPQESS_DESC_SINGLE 0x2
#define IPQESS_DESC_PAGE 0x4
struct ipqesstool_statistics {
u32 tx_q0_pkt;
u32 tx_q1_pkt;
u32 tx_q2_pkt;
u32 tx_q3_pkt;
u32 tx_q4_pkt;
u32 tx_q5_pkt;
u32 tx_q6_pkt;
u32 tx_q7_pkt;
u32 tx_q8_pkt;
u32 tx_q9_pkt;
u32 tx_q10_pkt;
u32 tx_q11_pkt;
u32 tx_q12_pkt;
u32 tx_q13_pkt;
u32 tx_q14_pkt;
u32 tx_q15_pkt;
u32 tx_q0_byte;
u32 tx_q1_byte;
u32 tx_q2_byte;
u32 tx_q3_byte;
u32 tx_q4_byte;
u32 tx_q5_byte;
u32 tx_q6_byte;
u32 tx_q7_byte;
u32 tx_q8_byte;
u32 tx_q9_byte;
u32 tx_q10_byte;
u32 tx_q11_byte;
u32 tx_q12_byte;
u32 tx_q13_byte;
u32 tx_q14_byte;
u32 tx_q15_byte;
u32 rx_q0_pkt;
u32 rx_q1_pkt;
u32 rx_q2_pkt;
u32 rx_q3_pkt;
u32 rx_q4_pkt;
u32 rx_q5_pkt;
u32 rx_q6_pkt;
u32 rx_q7_pkt;
u32 rx_q0_byte;
u32 rx_q1_byte;
u32 rx_q2_byte;
u32 rx_q3_byte;
u32 rx_q4_byte;
u32 rx_q5_byte;
u32 rx_q6_byte;
u32 rx_q7_byte;
u32 tx_desc_error;
};
struct ipqess_tx_desc {
__le16 len;
__le16 svlan_tag;
__le32 word1;
__le32 addr;
__le32 word3;
} __aligned(16) __packed;
struct ipqess_rx_desc {
u16 rrd0;
u16 rrd1;
u16 rrd2;
u16 rrd3;
u16 rrd4;
u16 rrd5;
u16 rrd6;
u16 rrd7;
} __aligned(16) __packed;
struct ipqess_buf {
struct sk_buff *skb;
dma_addr_t dma;
u32 flags;
u16 length;
};
struct ipqess_tx_ring {
struct napi_struct napi_tx;
u32 idx;
int ring_id;
struct ipqess *ess;
struct netdev_queue *nq;
struct ipqess_tx_desc *hw_desc;
struct ipqess_buf *buf;
dma_addr_t dma;
u16 count;
u16 head;
u16 tail;
};
struct ipqess_rx_ring {
struct napi_struct napi_rx;
u32 idx;
int ring_id;
struct ipqess *ess;
struct device *ppdev;
struct ipqess_rx_desc **hw_desc;
struct ipqess_buf *buf;
dma_addr_t dma;
u16 head;
u16 tail;
atomic_t refill_count;
};
struct ipqess_rx_ring_refill {
struct ipqess_rx_ring *rx_ring;
struct work_struct refill_work;
};
#define IPQESS_IRQ_NAME_LEN 32
struct ipqess {
struct net_device *netdev;
void __iomem *hw_addr;
struct clk *ess_clk;
struct reset_control *ess_rst;
struct ipqess_rx_ring rx_ring[IPQESS_NETDEV_QUEUES];
struct platform_device *pdev;
struct phylink *phylink;
struct phylink_config phylink_config;
struct ipqess_tx_ring tx_ring[IPQESS_NETDEV_QUEUES];
struct ipqesstool_statistics ipqessstats;
spinlock_t stats_lock;
struct net_device_stats stats;
struct ipqess_rx_ring_refill rx_refill[IPQESS_NETDEV_QUEUES];
u32 tx_irq[IPQESS_MAX_TX_QUEUE];
char tx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN];
u32 rx_irq[IPQESS_MAX_RX_QUEUE];
char rx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN];
};
static inline void build_test(void)
{
struct ipqess *ess;
BUILD_BUG_ON(ARRAY_SIZE(ess->rx_ring) != ARRAY_SIZE(ess->rx_refill));
}
void ipqess_set_ethtool_ops(struct net_device *netdev);
void ipqess_update_hw_stats(struct ipqess *ess);
/* register definition */
#define IPQESS_REG_MAS_CTRL 0x0
#define IPQESS_REG_TIMEOUT_CTRL 0x004
#define IPQESS_REG_DBG0 0x008
#define IPQESS_REG_DBG1 0x00C
#define IPQESS_REG_SW_CTRL0 0x100
#define IPQESS_REG_SW_CTRL1 0x104
/* Interrupt Status Register */
#define IPQESS_REG_RX_ISR 0x200
#define IPQESS_REG_TX_ISR 0x208
#define IPQESS_REG_MISC_ISR 0x210
#define IPQESS_REG_WOL_ISR 0x218
#define IPQESS_MISC_ISR_RX_URG_Q(x) (1 << x)
#define IPQESS_MISC_ISR_AXIR_TIMEOUT 0x00000100
#define IPQESS_MISC_ISR_AXIR_ERR 0x00000200
#define IPQESS_MISC_ISR_TXF_DEAD 0x00000400
#define IPQESS_MISC_ISR_AXIW_ERR 0x00000800
#define IPQESS_MISC_ISR_AXIW_TIMEOUT 0x00001000
#define IPQESS_WOL_ISR 0x00000001
/* Interrupt Mask Register */
#define IPQESS_REG_MISC_IMR 0x214
#define IPQESS_REG_WOL_IMR 0x218
#define IPQESS_RX_IMR_NORMAL_MASK 0x1
#define IPQESS_TX_IMR_NORMAL_MASK 0x1
#define IPQESS_MISC_IMR_NORMAL_MASK 0x80001FFF
#define IPQESS_WOL_IMR_NORMAL_MASK 0x1
/* Edma receive consumer index */
#define IPQESS_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
/* Edma transmit consumer index */
#define IPQESS_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
/* IRQ Moderator Initial Timer Register */
#define IPQESS_REG_IRQ_MODRT_TIMER_INIT 0x280
#define IPQESS_IRQ_MODRT_TIMER_MASK 0xFFFF
#define IPQESS_IRQ_MODRT_RX_TIMER_SHIFT 0
#define IPQESS_IRQ_MODRT_TX_TIMER_SHIFT 16
/* Interrupt Control Register */
#define IPQESS_REG_INTR_CTRL 0x284
#define IPQESS_INTR_CLR_TYP_SHIFT 0
#define IPQESS_INTR_SW_IDX_W_TYP_SHIFT 1
#define IPQESS_INTR_CLEAR_TYPE_W1 0
#define IPQESS_INTR_CLEAR_TYPE_R 1
/* RX Interrupt Mask Register */
#define IPQESS_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
/* TX Interrupt mask register */
#define IPQESS_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
/* Load Ptr Register
* Software sets this bit after the initialization of the head and tail
*/
#define IPQESS_REG_TX_SRAM_PART 0x400
#define IPQESS_LOAD_PTR_SHIFT 16
/* TXQ Control Register */
#define IPQESS_REG_TXQ_CTRL 0x404
#define IPQESS_TXQ_CTRL_IP_OPTION_EN 0x10
#define IPQESS_TXQ_CTRL_TXQ_EN 0x20
#define IPQESS_TXQ_CTRL_ENH_MODE 0x40
#define IPQESS_TXQ_CTRL_LS_8023_EN 0x80
#define IPQESS_TXQ_CTRL_TPD_BURST_EN 0x100
#define IPQESS_TXQ_CTRL_LSO_BREAK_EN 0x200
#define IPQESS_TXQ_NUM_TPD_BURST_MASK 0xF
#define IPQESS_TXQ_TXF_BURST_NUM_MASK 0xFFFF
#define IPQESS_TXQ_NUM_TPD_BURST_SHIFT 0
#define IPQESS_TXQ_TXF_BURST_NUM_SHIFT 16
#define IPQESS_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
#define IPQESS_TXF_WATER_MARK_MASK 0x0FFF
#define IPQESS_TXF_LOW_WATER_MARK_SHIFT 0
#define IPQESS_TXF_HIGH_WATER_MARK_SHIFT 16
#define IPQESS_TXQ_CTRL_BURST_MODE_EN 0x80000000
/* WRR Control Register */
#define IPQESS_REG_WRR_CTRL_Q0_Q3 0x40c
#define IPQESS_REG_WRR_CTRL_Q4_Q7 0x410
#define IPQESS_REG_WRR_CTRL_Q8_Q11 0x414
#define IPQESS_REG_WRR_CTRL_Q12_Q15 0x418
/* Weight round robin(WRR), it takes queue as input, and computes
* starting bits where we need to write the weight for a particular
* queue
*/
#define IPQESS_WRR_SHIFT(x) (((x) * 5) % 20)
/* Tx Descriptor Control Register */
#define IPQESS_REG_TPD_RING_SIZE 0x41C
#define IPQESS_TPD_RING_SIZE_SHIFT 0
#define IPQESS_TPD_RING_SIZE_MASK 0xFFFF
/* Transmit descriptor base address */
#define IPQESS_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */
/* TPD Index Register */
#define IPQESS_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */
#define IPQESS_TPD_PROD_IDX_BITS 0x0000FFFF
#define IPQESS_TPD_CONS_IDX_BITS 0xFFFF0000
#define IPQESS_TPD_PROD_IDX_MASK 0xFFFF
#define IPQESS_TPD_CONS_IDX_MASK 0xFFFF
#define IPQESS_TPD_PROD_IDX_SHIFT 0
#define IPQESS_TPD_CONS_IDX_SHIFT 16
/* TX Virtual Queue Mapping Control Register */
#define IPQESS_REG_VQ_CTRL0 0x4A0
#define IPQESS_REG_VQ_CTRL1 0x4A4
/* Virtual QID shift, it takes queue as input, and computes
* Virtual QID position in virtual qid control register
*/
#define IPQESS_VQ_ID_SHIFT(i) (((i) * 3) % 24)
/* Virtual Queue Default Value */
#define IPQESS_VQ_REG_VALUE 0x240240
/* Tx side Port Interface Control Register */
#define IPQESS_REG_PORT_CTRL 0x4A8
#define IPQESS_PAD_EN_SHIFT 15
/* Tx side VLAN Configuration Register */
#define IPQESS_REG_VLAN_CFG 0x4AC
#define IPQESS_VLAN_CFG_SVLAN_TPID_SHIFT 0
#define IPQESS_VLAN_CFG_SVLAN_TPID_MASK 0xffff
#define IPQESS_VLAN_CFG_CVLAN_TPID_SHIFT 16
#define IPQESS_VLAN_CFG_CVLAN_TPID_MASK 0xffff
#define IPQESS_TX_CVLAN 16
#define IPQESS_TX_INS_CVLAN 17
#define IPQESS_TX_CVLAN_TAG_SHIFT 0
#define IPQESS_TX_SVLAN 14
#define IPQESS_TX_INS_SVLAN 15
#define IPQESS_TX_SVLAN_TAG_SHIFT 16
/* Tx Queue Packet Statistic Register */
#define IPQESS_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */
#define IPQESS_TX_STAT_PKT_MASK 0xFFFFFF
/* Tx Queue Byte Statistic Register */
#define IPQESS_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */
/* Load Balance Based Ring Offset Register */
#define IPQESS_REG_LB_RING 0x800
#define IPQESS_LB_RING_ENTRY_MASK 0xff
#define IPQESS_LB_RING_ID_MASK 0x7
#define IPQESS_LB_RING_PROFILE_ID_MASK 0x3
#define IPQESS_LB_RING_ENTRY_BIT_OFFSET 8
#define IPQESS_LB_RING_ID_OFFSET 0
#define IPQESS_LB_RING_PROFILE_ID_OFFSET 3
#define IPQESS_LB_REG_VALUE 0x6040200
/* Load Balance Priority Mapping Register */
#define IPQESS_REG_LB_PRI_START 0x804
#define IPQESS_REG_LB_PRI_END 0x810
#define IPQESS_LB_PRI_REG_INC 4
#define IPQESS_LB_PRI_ENTRY_BIT_OFFSET 4
#define IPQESS_LB_PRI_ENTRY_MASK 0xf
/* RSS Priority Mapping Register */
#define IPQESS_REG_RSS_PRI 0x820
#define IPQESS_RSS_PRI_ENTRY_MASK 0xf
#define IPQESS_RSS_RING_ID_MASK 0x7
#define IPQESS_RSS_PRI_ENTRY_BIT_OFFSET 4
/* RSS Indirection Register */
#define IPQESS_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */
#define IPQESS_NUM_IDT 16
#define IPQESS_RSS_IDT_VALUE 0x64206420
/* Default RSS Ring Register */
#define IPQESS_REG_DEF_RSS 0x890
#define IPQESS_DEF_RSS_MASK 0x7
/* RSS Hash Function Type Register */
#define IPQESS_REG_RSS_TYPE 0x894
#define IPQESS_RSS_TYPE_NONE 0x01
#define IPQESS_RSS_TYPE_IPV4TCP 0x02
#define IPQESS_RSS_TYPE_IPV6_TCP 0x04
#define IPQESS_RSS_TYPE_IPV4_UDP 0x08
#define IPQESS_RSS_TYPE_IPV6UDP 0x10
#define IPQESS_RSS_TYPE_IPV4 0x20
#define IPQESS_RSS_TYPE_IPV6 0x40
#define IPQESS_RSS_HASH_MODE_MASK 0x7f
#define IPQESS_REG_RSS_HASH_VALUE 0x8C0
#define IPQESS_REG_RSS_TYPE_RESULT 0x8C4
#define IPQESS_HASH_TYPE_START 0
#define IPQESS_HASH_TYPE_END 5
#define IPQESS_HASH_TYPE_SHIFT 12
#define IPQESS_RFS_FLOW_ENTRIES 1024
#define IPQESS_RFS_FLOW_ENTRIES_MASK (IPQESS_RFS_FLOW_ENTRIES - 1)
#define IPQESS_RFS_EXPIRE_COUNT_PER_CALL 128
/* RFD Base Address Register */
#define IPQESS_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */
/* RFD Index Register */
#define IPQESS_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2)) /* x = queue id */
#define IPQESS_RFD_PROD_IDX_BITS 0x00000FFF
#define IPQESS_RFD_CONS_IDX_BITS 0x0FFF0000
#define IPQESS_RFD_PROD_IDX_MASK 0xFFF
#define IPQESS_RFD_CONS_IDX_MASK 0xFFF
#define IPQESS_RFD_PROD_IDX_SHIFT 0
#define IPQESS_RFD_CONS_IDX_SHIFT 16
/* Rx Descriptor Control Register */
#define IPQESS_REG_RX_DESC0 0xA10
#define IPQESS_RFD_RING_SIZE_MASK 0xFFF
#define IPQESS_RX_BUF_SIZE_MASK 0xFFFF
#define IPQESS_RFD_RING_SIZE_SHIFT 0
#define IPQESS_RX_BUF_SIZE_SHIFT 16
#define IPQESS_REG_RX_DESC1 0xA14
#define IPQESS_RXQ_RFD_BURST_NUM_MASK 0x3F
#define IPQESS_RXQ_RFD_PF_THRESH_MASK 0x1F
#define IPQESS_RXQ_RFD_LOW_THRESH_MASK 0xFFF
#define IPQESS_RXQ_RFD_BURST_NUM_SHIFT 0
#define IPQESS_RXQ_RFD_PF_THRESH_SHIFT 8
#define IPQESS_RXQ_RFD_LOW_THRESH_SHIFT 16
/* RXQ Control Register */
#define IPQESS_REG_RXQ_CTRL 0xA18
#define IPQESS_FIFO_THRESH_TYPE_SHIF 0
#define IPQESS_FIFO_THRESH_128_BYTE 0x0
#define IPQESS_FIFO_THRESH_64_BYTE 0x1
#define IPQESS_RXQ_CTRL_RMV_VLAN 0x00000002
#define IPQESS_RXQ_CTRL_EN_MASK GENMASK(15, 8)
#define IPQESS_RXQ_CTRL_EN(__qid) BIT(8 + (__qid))
/* AXI Burst Size Config */
#define IPQESS_REG_AXIW_CTRL_MAXWRSIZE 0xA1C
#define IPQESS_AXIW_MAXWRSIZE_VALUE 0x0
/* Rx Statistics Register */
#define IPQESS_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */
#define IPQESS_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */
/* WoL Pattern Length Register */
#define IPQESS_REG_WOL_PATTERN_LEN0 0xC00
#define IPQESS_WOL_PT_LEN_MASK 0xFF
#define IPQESS_WOL_PT0_LEN_SHIFT 0
#define IPQESS_WOL_PT1_LEN_SHIFT 8
#define IPQESS_WOL_PT2_LEN_SHIFT 16
#define IPQESS_WOL_PT3_LEN_SHIFT 24
#define IPQESS_REG_WOL_PATTERN_LEN1 0xC04
#define IPQESS_WOL_PT4_LEN_SHIFT 0
#define IPQESS_WOL_PT5_LEN_SHIFT 8
#define IPQESS_WOL_PT6_LEN_SHIFT 16
/* WoL Control Register */
#define IPQESS_REG_WOL_CTRL 0xC08
#define IPQESS_WOL_WK_EN 0x00000001
#define IPQESS_WOL_MG_EN 0x00000002
#define IPQESS_WOL_PT0_EN 0x00000004
#define IPQESS_WOL_PT1_EN 0x00000008
#define IPQESS_WOL_PT2_EN 0x00000010
#define IPQESS_WOL_PT3_EN 0x00000020
#define IPQESS_WOL_PT4_EN 0x00000040
#define IPQESS_WOL_PT5_EN 0x00000080
#define IPQESS_WOL_PT6_EN 0x00000100
/* MAC Control Register */
#define IPQESS_REG_MAC_CTRL0 0xC20
#define IPQESS_REG_MAC_CTRL1 0xC24
/* WoL Pattern Register */
#define IPQESS_REG_WOL_PATTERN_START 0x5000
#define IPQESS_PATTERN_PART_REG_OFFSET 0x40
/* TX descriptor fields */
#define IPQESS_TPD_HDR_SHIFT 0
#define IPQESS_TPD_PPPOE_EN 0x00000100
#define IPQESS_TPD_IP_CSUM_EN 0x00000200
#define IPQESS_TPD_TCP_CSUM_EN 0x0000400
#define IPQESS_TPD_UDP_CSUM_EN 0x00000800
#define IPQESS_TPD_CUSTOM_CSUM_EN 0x00000C00
#define IPQESS_TPD_LSO_EN 0x00001000
#define IPQESS_TPD_LSO_V2_EN 0x00002000
/* The VLAN_TAGGED bit is not used in the publicly available
* drivers. The definition has been stolen from the Atheros
* 'alx' driver (drivers/net/ethernet/atheros/alx/hw.h). It
* seems that it has the same meaning in regard to the EDMA
* hardware.
*/
#define IPQESS_TPD_VLAN_TAGGED 0x00004000
#define IPQESS_TPD_IPV4_EN 0x00010000
#define IPQESS_TPD_MSS_MASK 0x1FFF
#define IPQESS_TPD_MSS_SHIFT 18
#define IPQESS_TPD_CUSTOM_CSUM_SHIFT 18
/* RRD descriptor fields */
#define IPQESS_RRD_NUM_RFD_MASK 0x000F
#define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF
#define IPQESS_RRD_SRC_PORT_NUM_MASK 0x4000
#define IPQESS_RRD_SVLAN 0x8000
#define IPQESS_RRD_FLOW_COOKIE_MASK 0x07FF;
#define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF
#define IPQESS_RRD_CSUM_FAIL_MASK 0xC000
#define IPQESS_RRD_CVLAN 0x0001
#define IPQESS_RRD_DESC_VALID 0x8000
#define IPQESS_RRD_PRIORITY_SHIFT 4
#define IPQESS_RRD_PRIORITY_MASK 0x7
#define IPQESS_RRD_PORT_TYPE_SHIFT 7
#define IPQESS_RRD_PORT_TYPE_MASK 0x1F
#endif

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target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess_ethtool.c
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// SPDX-License-Identifier: (GPL-2.0 OR ISC)
/* Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
* Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/ethtool.h>
#include <linux/netdevice.h>
#include <linux/string.h>
#include <linux/phylink.h>
#include "ipqess.h"
struct ipqesstool_stats {
uint8_t string[ETH_GSTRING_LEN];
uint32_t offset;
};
#define IPQESS_STAT(m) offsetof(struct ipqesstool_statistics, m)
#define DRVINFO_LEN 32
static const struct ipqesstool_stats ipqess_stats[] = {
{"tx_q0_pkt", IPQESS_STAT(tx_q0_pkt)},
{"tx_q1_pkt", IPQESS_STAT(tx_q1_pkt)},
{"tx_q2_pkt", IPQESS_STAT(tx_q2_pkt)},
{"tx_q3_pkt", IPQESS_STAT(tx_q3_pkt)},
{"tx_q4_pkt", IPQESS_STAT(tx_q4_pkt)},
{"tx_q5_pkt", IPQESS_STAT(tx_q5_pkt)},
{"tx_q6_pkt", IPQESS_STAT(tx_q6_pkt)},
{"tx_q7_pkt", IPQESS_STAT(tx_q7_pkt)},
{"tx_q8_pkt", IPQESS_STAT(tx_q8_pkt)},
{"tx_q9_pkt", IPQESS_STAT(tx_q9_pkt)},
{"tx_q10_pkt", IPQESS_STAT(tx_q10_pkt)},
{"tx_q11_pkt", IPQESS_STAT(tx_q11_pkt)},
{"tx_q12_pkt", IPQESS_STAT(tx_q12_pkt)},
{"tx_q13_pkt", IPQESS_STAT(tx_q13_pkt)},
{"tx_q14_pkt", IPQESS_STAT(tx_q14_pkt)},
{"tx_q15_pkt", IPQESS_STAT(tx_q15_pkt)},
{"tx_q0_byte", IPQESS_STAT(tx_q0_byte)},
{"tx_q1_byte", IPQESS_STAT(tx_q1_byte)},
{"tx_q2_byte", IPQESS_STAT(tx_q2_byte)},
{"tx_q3_byte", IPQESS_STAT(tx_q3_byte)},
{"tx_q4_byte", IPQESS_STAT(tx_q4_byte)},
{"tx_q5_byte", IPQESS_STAT(tx_q5_byte)},
{"tx_q6_byte", IPQESS_STAT(tx_q6_byte)},
{"tx_q7_byte", IPQESS_STAT(tx_q7_byte)},
{"tx_q8_byte", IPQESS_STAT(tx_q8_byte)},
{"tx_q9_byte", IPQESS_STAT(tx_q9_byte)},
{"tx_q10_byte", IPQESS_STAT(tx_q10_byte)},
{"tx_q11_byte", IPQESS_STAT(tx_q11_byte)},
{"tx_q12_byte", IPQESS_STAT(tx_q12_byte)},
{"tx_q13_byte", IPQESS_STAT(tx_q13_byte)},
{"tx_q14_byte", IPQESS_STAT(tx_q14_byte)},
{"tx_q15_byte", IPQESS_STAT(tx_q15_byte)},
{"rx_q0_pkt", IPQESS_STAT(rx_q0_pkt)},
{"rx_q1_pkt", IPQESS_STAT(rx_q1_pkt)},
{"rx_q2_pkt", IPQESS_STAT(rx_q2_pkt)},
{"rx_q3_pkt", IPQESS_STAT(rx_q3_pkt)},
{"rx_q4_pkt", IPQESS_STAT(rx_q4_pkt)},
{"rx_q5_pkt", IPQESS_STAT(rx_q5_pkt)},
{"rx_q6_pkt", IPQESS_STAT(rx_q6_pkt)},
{"rx_q7_pkt", IPQESS_STAT(rx_q7_pkt)},
{"rx_q0_byte", IPQESS_STAT(rx_q0_byte)},
{"rx_q1_byte", IPQESS_STAT(rx_q1_byte)},
{"rx_q2_byte", IPQESS_STAT(rx_q2_byte)},
{"rx_q3_byte", IPQESS_STAT(rx_q3_byte)},
{"rx_q4_byte", IPQESS_STAT(rx_q4_byte)},
{"rx_q5_byte", IPQESS_STAT(rx_q5_byte)},
{"rx_q6_byte", IPQESS_STAT(rx_q6_byte)},
{"rx_q7_byte", IPQESS_STAT(rx_q7_byte)},
{"tx_desc_error", IPQESS_STAT(tx_desc_error)},
};
static int ipqess_get_strset_count(struct net_device *netdev, int sset)
{
switch (sset) {
case ETH_SS_STATS:
return ARRAY_SIZE(ipqess_stats);
default:
netdev_dbg(netdev, "%s: Invalid string set", __func__);
return -EOPNOTSUPP;
}
}
static void ipqess_get_strings(struct net_device *netdev, uint32_t stringset,
uint8_t *data)
{
uint8_t *p = data;
uint32_t i;
switch (stringset) {
case ETH_SS_STATS:
for (i = 0; i < ARRAY_SIZE(ipqess_stats); i++) {
memcpy(p, ipqess_stats[i].string,
min((size_t)ETH_GSTRING_LEN,
strlen(ipqess_stats[i].string) + 1));
p += ETH_GSTRING_LEN;
}
break;
}
}
static void ipqess_get_ethtool_stats(struct net_device *netdev,
struct ethtool_stats *stats,
uint64_t *data)
{
struct ipqess *ess = netdev_priv(netdev);
u32 *essstats = (u32 *)&ess->ipqessstats;
int i;
spin_lock(&ess->stats_lock);
ipqess_update_hw_stats(ess);
for (i = 0; i < ARRAY_SIZE(ipqess_stats); i++)
data[i] = *(u32 *)(essstats + (ipqess_stats[i].offset / sizeof(u32)));
spin_unlock(&ess->stats_lock);
}
static void ipqess_get_drvinfo(struct net_device *dev,
struct ethtool_drvinfo *info)
{
strlcpy(info->driver, "qca_ipqess", DRVINFO_LEN);
strlcpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN);
}
static int ipqess_get_settings(struct net_device *netdev,
struct ethtool_link_ksettings *cmd)
{
struct ipqess *ess = netdev_priv(netdev);
return phylink_ethtool_ksettings_get(ess->phylink, cmd);
}
static int ipqess_set_settings(struct net_device *netdev,
const struct ethtool_link_ksettings *cmd)
{
struct ipqess *ess = netdev_priv(netdev);
return phylink_ethtool_ksettings_set(ess->phylink, cmd);
}
static void ipqess_get_ringparam(struct net_device *netdev,
struct ethtool_ringparam *ring)
{
ring->tx_max_pending = IPQESS_TX_RING_SIZE;
ring->rx_max_pending = IPQESS_RX_RING_SIZE;
}
static const struct ethtool_ops ipqesstool_ops = {
.get_drvinfo = &ipqess_get_drvinfo,
.get_link = &ethtool_op_get_link,
.get_link_ksettings = &ipqess_get_settings,
.set_link_ksettings = &ipqess_set_settings,
.get_strings = &ipqess_get_strings,
.get_sset_count = &ipqess_get_strset_count,
.get_ethtool_stats = &ipqess_get_ethtool_stats,
.get_ringparam = ipqess_get_ringparam,
};
void ipqess_set_ethtool_ops(struct net_device *netdev)
{
netdev->ethtool_ops = &ipqesstool_ops;
}

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target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ws-ap391x.dts Normal file
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@ -0,0 +1,344 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Extreme Networks WS-AP391x";
compatible = "extreme-networks,ws-ap391x";
aliases {
led-boot = &led_system_green;
led-failsafe = &led_system_red;
led-running = &led_system_green;
led-upgrade = &led_system_red;
};
soc {
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
};
leds {
compatible = "gpio-leds";
led_system_green: system_green {
label = "system:green";
gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
};
/*
* system:amber ==> AP3917
* system:red ==> AP3916
* */
led_system_red: system_red {
label = "system:red_or_system:amber";
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
led_wlan24_green: wlan24_green {
label = "wlan24:green";
gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
/*
* wlan24:amber ==> AP3915/AP3917
* pse:green ==> AP3912
* */
led_wlan24_amber: wlan24_amber {
label = "wlan24:amber_or_pse:green";
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
};
led_wlan5_green: wlan5_green {
label = "wlan5:green";
gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
/* iot:blue ==> AP3917 */
led_iot_green: iot_green {
label = "iot:green_or_iot:blue";
gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
};
/* eth:green ==> only AP3912/AP3916 */
led_eth_green: eth_green {
label = "eth:green";
gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
};
/*
* eth:amber ==> only AP3912/AP3916
* usb_enable ==> only AP3915e
*/
led_eth_amber: eth_amber {
label = "eth:amber_or_usb_enable";
gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
};
/*
* wlan5:amber ==> AP3915/AP3917
* cam:green ==> only AP3916
*/
led_wlan5_amber: wlan5_amber {
label = "wlan5:amber_or_cam:green";
gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART >;
};
};
};
&prng {
status = "okay";
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
&crypto {
status = "okay";
};
&watchdog {
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb3 {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&usb2 {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&gmac {
status = "okay";
};
&switch {
status = "okay";
};
&swport1 {
status = "okay";
label = "sw-eth1";
};
&swport2 {
status = "okay";
label = "sw-eth2";
};
&swport3 {
status = "okay";
label = "sw-eth3";
};
/* "GE2" on AP3917/AP3916/WiNG-AP7662 */
&swport4 {
status = "okay";
label = "sw-eth4";
};
/*
* "GE1" on AP3917/AP3916/AP3915/AP7662
* "LAN1" on EXTR-AP3912
*/
&swport5 {
status = "okay";
label = "sw-eth5";
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
serial_pins: serial_0_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Layout for 0x0 - 0xe0000 unknown */
partition@e0000 {
label = "CFG1";
compatible = "u-boot,env-redundant-bool";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "BootBAK";
reg = <0xf0000 0x70000>;
read-only;
};
partition@160000 {
label = "WINGCFG1";
reg = <0x160000 0x10000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x170000 0x10000>;
read-only;
};
partition@180000 {
label = "BootPRI";
reg = <0x180000 0x70000>;
read-only;
};
partition@1f0000 {
label = "WINGCFG2";
reg = <0x1f0000 0x10000>;
read-only;
};
partition@200000 {
label = "FS";
reg = <0x200000 0x80000>;
read-only;
};
partition@280000 {
label = "firmware";
reg = <0x280000 0xeb0000>;
};
partition@1130000 {
label = "firmware2";
reg = <0x1130000 0xeb0000>;
};
partition@1fe0000 {
label = "CFG2";
compatible = "u-boot,env-redundant-bool";
reg = <0x1fe0000 0x10000>;
read-only;
};
};
};
};

10
target/linux/ipq40xx/image/generic.mk
View file

@ -538,6 +538,16 @@ define Device/extreme-networks_ws-ap3915i
endef
TARGET_DEVICES += extreme-networks_ws-ap3915i
define Device/extreme-networks_ws-ap391x
$(call Device/FitImage)
DEVICE_VENDOR := Extreme Networks
DEVICE_MODEL := WS-AP391x
IMAGE_SIZE := 15040k
SOC := qcom-ipq4029
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | check-size | append-metadata
endef
TARGET_DEVICES += extreme-networks_ws-ap391x
define Device/ezviz_cs-w3-wd1200g-eup
$(call Device/FitImage)
DEVICE_VENDOR := EZVIZ

27
target/linux/ipq40xx/patches-5.15/100-dt-bindings-clock-qcom-ipq4019-add-missing-networkin.patch
View file

@ -1,27 +0,0 @@
From 53cac0823f86c39eb4b00e2c9a7b2483a4182008 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 14 Aug 2023 12:37:58 +0200
Subject: [PATCH 1/2] dt-bindings: clock: qcom: ipq4019: add missing networking
resets
Add bindings for the missing networking resets found in IPQ4019 GCC.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 6 ++++++
1 file changed, 6 insertions(+)
--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -165,5 +165,11 @@
#define GCC_QDSS_BCR 69
#define GCC_MPM_BCR 70
#define GCC_SPDM_BCR 71
+#define ESS_MAC1_ARES 72
+#define ESS_MAC2_ARES 73
+#define ESS_MAC3_ARES 74
+#define ESS_MAC4_ARES 75
+#define ESS_MAC5_ARES 76
+#define ESS_PSGMII_ARES 77
#endif

28
target/linux/ipq40xx/patches-5.15/101-clk-qcom-gcc-ipq4019-add-missing-networking-resets.patch
View file

@ -1,28 +0,0 @@
From 6038ba75e2aa8e57d4eaf20a90c8061c43b1117f Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 14 Aug 2023 12:39:04 +0200
Subject: [PATCH 2/2] clk: qcom: gcc-ipq4019: add missing networking resets
IPQ4019 has more networking related resets that will be required for future
wired networking support, so lets add them.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/clk/qcom/gcc-ipq4019.c | 6 ++++++
1 file changed, 6 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1707,6 +1707,12 @@ static const struct qcom_reset_map gcc_i
[GCC_TCSR_BCR] = {0x22000, 0},
[GCC_MPM_BCR] = {0x24000, 0},
[GCC_SPDM_BCR] = {0x25000, 0},
+ [ESS_MAC1_ARES] = {0x1200C, 0},
+ [ESS_MAC2_ARES] = {0x1200C, 1},
+ [ESS_MAC3_ARES] = {0x1200C, 2},
+ [ESS_MAC4_ARES] = {0x1200C, 3},
+ [ESS_MAC5_ARES] = {0x1200C, 4},
+ [ESS_PSGMII_ARES] = {0x1200C, 5},
};
static const struct regmap_config gcc_ipq4019_regmap_config = {

115
target/linux/ipq40xx/patches-5.15/104-clk-fix-apss-cpu-overclocking.patch
View file

@ -1,115 +0,0 @@
From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@googlemail.com>
Date: Sun, 11 Mar 2018 14:41:31 +0100
Subject: [PATCH 2/2] clk: fix apss cpu overclocking
There's an interaction issue between the clk changes:"
clk: qcom: ipq4019: Add the apss cpu pll divider clock node
clk: qcom: ipq4019: remove fixed clocks and add pll clocks
" and the cpufreq-dt.
cpufreq-dt is now spamming the kernel-log with the following:
[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
for freq 761142857 (-34)
This only happens on certain devices like the Compex WPJ428
and AVM FritzBox!4040. However, other devices like the Asus
RT-AC58U and Meraki MR33 work just fine.
The issue stem from the fact that all higher CPU-Clocks
are achieved by switching the clock-parent to the P_DDRPLLAPSS
(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
as part of the DDR calibration.
For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
at round 533 MHz (ddrpllsdcc = 190285714 Hz).
whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
This patch attempts to fix the issue by modifying
clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
to use a new qcom_find_freq_close() function, which returns the closest
matching frequency, instead of the next higher. This way, the SoC in
the FB4040 (with its max clock speed of 710.4 MHz) will no longer
try to overclock to 761 MHz.
Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
1 file changed, 31 insertions(+), 3 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
.reg = 0x2f020,
};
+
+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
+ unsigned long rate)
+{
+ const struct freq_tbl *last = NULL;
+
+ for ( ; f->freq; f++) {
+ if (rate == f->freq)
+ return f;
+
+ if (f->freq > rate) {
+ if (!last ||
+ (f->freq - rate) < (rate - last->freq))
+ return f;
+ else
+ return last;
+ }
+ last = f;
+ }
+
+ return last;
+}
+
/*
* Round rate function for APSS CPU PLL Clock divider.
* It looks up the frequency table and returns the next higher frequency
@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
struct clk_hw *p_hw;
const struct freq_tbl *f;
- f = qcom_find_freq(pll->freq_tbl, rate);
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
@@ -1277,7 +1300,7 @@ static int clk_cpu_div_set_rate(struct c
const struct freq_tbl *f;
u32 mask;
- f = qcom_find_freq(pll->freq_tbl, rate);
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
@@ -1304,6 +1327,7 @@ static unsigned long
clk_cpu_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
+ const struct freq_tbl *f;
struct clk_fepll *pll = to_clk_fepll(hw);
u32 cdiv, pre_div;
u64 rate;
@@ -1324,7 +1348,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
do_div(rate, pre_div);
- return rate;
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
+ if (!f)
+ return rate;
+
+ return f->freq;
};
static const struct clk_ops clk_regmap_cpu_div_ops = {

48
target/linux/ipq40xx/patches-5.15/301-arm-compressed-add-appended-DTB-section.patch
View file

@ -1,48 +0,0 @@
From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 30 Oct 2020 13:36:31 +0100
Subject: [PATCH] arm: compressed: add appended DTB section
This adds a appended_dtb section to the ARM decompressor
linker script.
This allows using the existing ARM zImage appended DTB support for
appending a DTB to the raw ELF kernel.
Its size is set to 1MB max to match the zImage appended DTB size limit.
To use it to pass the DTB to the kernel, objcopy is used:
objcopy --set-section-flags=.appended_dtb=alloc,contents \
--update-section=.appended_dtb=<target>.dtb vmlinux
This is based off the following patch:
https://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/compressed/vmlinux.lds.S
+++ b/arch/arm/boot/compressed/vmlinux.lds.S
@@ -103,6 +103,13 @@ SECTIONS
_edata = .;
+ .appended_dtb : {
+ /* leave space for appended DTB */
+ . += 0x100000;
+ }
+
+ _edata_dtb = .;
+
/*
* The image_end section appears after any additional loadable sections
* that the linker may decide to insert in the binary image. Having
@@ -140,4 +147,4 @@ SECTIONS
ARM_ASSERTS
}
-ASSERT(_edata_real == _edata, "error: zImage file size is incorrect");
+ASSERT(_edata_real == _edata_dtb, "error: zImage file size is incorrect");

66
target/linux/ipq40xx/patches-5.15/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch
View file

@ -1,66 +0,0 @@
From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001
From: John Thomson <git@johnthomson.fastmail.com.au>
Date: Fri, 23 Oct 2020 19:42:36 +1000
Subject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot
For IPQ40XX systems where the SoC watchdog is activated before linux,
the watchdog timer may be too small for linux to finish uncompress,
boot, and watchdog management start.
If the watchdog is enabled, set the timeout for it to 30 seconds.
The functionality and offsets were copied from:
drivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start
The watchdog memory address was taken from:
arch/arm/boot/dts/qcom-ipq4019.dtsi
This was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's
RouterBoot bootloader.
Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
---
arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -624,6 +624,41 @@ not_relocated: mov r0, #0
bic r4, r4, #1
blne cache_on
+/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds
+ * if it is enabled, so that there is time for kernel
+ * to decompress, boot, and take over the watchdog.
+ * data and functionality from drivers/watchdog/qcom-wdt.c
+ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi
+ */
+#ifdef CONFIG_ARCH_IPQ40XX
+watchdog_set:
+ /* offsets:
+ * 0x04 reset (=1 resets countdown)
+ * 0x08 enable (=0 disables)
+ * 0x0c status (=1 when SoC was reset by watchdog)
+ * 0x10 bark (=timeout warning in ticks)
+ * 0x14 bite (=timeout reset in ticks)
+ * clock rate is 1<<15 hertz
+ */
+ .equ watchdog, 0x0b017000 @Store watchdog base address
+ movw r0, #:lower16:watchdog
+ movt r0, #:upper16:watchdog
+ ldr r1, [r0, #0x08] @Get enabled?
+ cmp r1, #1 @If not enabled, do not change
+ bne watchdog_finished
+ mov r1, #0
+ str r1, [r0, #0x08] @Disable the watchdog
+ mov r1, #1
+ str r1, [r0, #0x04] @Pet the watchdog
+ mov r1, #30 @30 seconds timeout
+ lsl r1, r1, #15 @converted to ticks
+ str r1, [r0, #0x10] @Set the bark timeout
+ str r1, [r0, #0x14] @Set the bite timeout
+ mov r1, #1
+ str r1, [r0, #0x08] @Enable the watchdog
+watchdog_finished:
+#endif /* CONFIG_ARCH_IPQ40XX */
+
/*
* The C runtime environment should now be setup sufficiently.
* Set up some pointers, and start decompressing.

24
target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch
View file

@ -1,24 +0,0 @@
From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 14 Dec 2020 13:35:35 +0100
Subject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock
When using sdhci_msm_set_clock clock setting will fail, so lets
use the generic sdhci_set_clock.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/mmc/host/sdhci-msm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -2447,7 +2447,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
static const struct sdhci_ops sdhci_msm_ops = {
.reset = sdhci_msm_reset,
- .set_clock = sdhci_msm_set_clock,
+ .set_clock = sdhci_set_clock,
.get_min_clock = sdhci_msm_get_min_clock,
.get_max_clock = sdhci_msm_get_max_clock,
.set_bus_width = sdhci_set_bus_width,

108
target/linux/ipq40xx/patches-5.15/401-mmc-sdhci-msm-comment-unused-sdhci_msm_set_clock.patch
View file

@ -1,108 +0,0 @@
From 28edd829133766eb3cefaf2e49d3ee701968061b Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Tue, 9 May 2023 01:57:17 +0200
Subject: [PATCH] mmc: sdhci-msm: comment unused sdhci_msm_set_clock
comment unused sdhci_msm_set_clock and __sdhci_msm_set_clock as due to some
current problem, we are forced to use sdhci_set_clock.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/mmc/host/sdhci-msm.c | 86 ++++++++++++++++++------------------
1 file changed, 43 insertions(+), 43 deletions(-)
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -1751,49 +1751,49 @@ static unsigned int sdhci_msm_get_min_cl
return SDHCI_MSM_MIN_CLOCK;
}
-/*
- * __sdhci_msm_set_clock - sdhci_msm clock control.
- *
- * Description:
- * MSM controller does not use internal divider and
- * instead directly control the GCC clock as per
- * HW recommendation.
- **/
-static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
-{
- u16 clk;
-
- sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
-
- if (clock == 0)
- return;
-
- /*
- * MSM controller do not use clock divider.
- * Thus read SDHCI_CLOCK_CONTROL and only enable
- * clock with no divider value programmed.
- */
- clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
- sdhci_enable_clk(host, clk);
-}
-
-/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
-static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
-{
- struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
- struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
-
- if (!clock) {
- host->mmc->actual_clock = msm_host->clk_rate = 0;
- goto out;
- }
-
- sdhci_msm_hc_select_mode(host);
-
- msm_set_clock_rate_for_bus_mode(host, clock);
-out:
- __sdhci_msm_set_clock(host, clock);
-}
+// /*
+// * __sdhci_msm_set_clock - sdhci_msm clock control.
+// *
+// * Description:
+// * MSM controller does not use internal divider and
+// * instead directly control the GCC clock as per
+// * HW recommendation.
+// **/
+// static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
+// {
+// u16 clk;
+
+// sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+// if (clock == 0)
+// return;
+
+// /*
+// * MSM controller do not use clock divider.
+// * Thus read SDHCI_CLOCK_CONTROL and only enable
+// * clock with no divider value programmed.
+// */
+// clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+// sdhci_enable_clk(host, clk);
+// }
+
+// /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
+// static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
+// {
+// struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+// struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+
+// if (!clock) {
+// host->mmc->actual_clock = msm_host->clk_rate = 0;
+// goto out;
+// }
+
+// sdhci_msm_hc_select_mode(host);
+
+// msm_set_clock_rate_for_bus_mode(host, clock);
+// out:
+// __sdhci_msm_set_clock(host, clock);
+// }
/*****************************************************************************\
* *

60
target/linux/ipq40xx/patches-5.15/420-firmware-qcom-scm-Add-SDI-disable-support.patch
View file

@ -1,60 +0,0 @@
From b514bc3c0a5a57bc83843dc66c72788b9c9435ac Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Thu, 18 May 2023 16:02:23 +0200
Subject: [PATCH 1/3] firmware: qcom: scm: Add SDI disable support
Some SoC-s like IPQ5018 require SDI(Secure Debug Image) to be disabled
before trying to reboot, otherwise board will just hang after reboot has
been issued via PSCI.
So, provide a call to SCM that allows disabling it.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Acked-by: Mukesh Ojha <quic_mojha@quicinc.com>
---
drivers/firmware/qcom_scm.c | 23 +++++++++++++++++++++++
drivers/firmware/qcom_scm.h | 1 +
2 files changed, 24 insertions(+)
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -389,6 +389,29 @@ int qcom_scm_set_remote_state(u32 state,
}
EXPORT_SYMBOL(qcom_scm_set_remote_state);
+static int qcom_scm_disable_sdi(void)
+{
+ int ret;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_SDI_CONFIG,
+ .args[0] = 1, /* Disable watchdog debug */
+ .args[1] = 0, /* Disable SDI */
+ .arginfo = QCOM_SCM_ARGS(2),
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;
+
+ ret = qcom_scm_clk_enable();
+ if (ret)
+ return ret;
+ ret = qcom_scm_call(__scm->dev, &desc, &res);
+
+ qcom_scm_clk_disable();
+
+ return ret ? : res.result[0];
+}
+
static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
{
struct qcom_scm_desc desc = {
--- a/drivers/firmware/qcom_scm.h
+++ b/drivers/firmware/qcom_scm.h
@@ -77,6 +77,7 @@ extern int scm_legacy_call(struct device
#define QCOM_SCM_SVC_BOOT 0x01
#define QCOM_SCM_BOOT_SET_ADDR 0x01
#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
+#define QCOM_SCM_BOOT_SDI_CONFIG 0x09
#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3

34
target/linux/ipq40xx/patches-5.15/421-firmware-qcom-scm-disable-SDI-on-Google-WiFi.patch
View file

@ -1,34 +0,0 @@
From a658ad57c2b9d46eb5395c7bb8cf83b8e0f289e7 Mon Sep 17 00:00:00 2001
From: Brian Norris <computersforpeace@gmail.com>
Date: Fri, 28 Jul 2023 12:02:19 +0200
Subject: [PATCH 2/3] firmware: qcom: scm: disable SDI on Google WiFi
Google WiFi seems to have SDI (Secure Debug Image) enabled by default which
prevents normal reboot from working causing the board to just hang after
reboot is called.
So lets disable SDI during SCM probe on Google WiFi boards in order to
avoid a state where WDT will kick in and then the board will just hang
in the debug mode.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
---
drivers/firmware/qcom_scm.c | 7 +++++++
1 file changed, 7 insertions(+)
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -1337,6 +1337,13 @@ static int qcom_scm_probe(struct platfor
if (download_mode)
qcom_scm_set_download_mode(true);
+ /*
+ * Factory firmware leaves SDI (a debug interface), which prevents
+ * clean reboot.
+ */
+ if (of_machine_is_compatible("google,wifi"))
+ qcom_scm_disable_sdi();
+
return 0;
}

138
target/linux/ipq40xx/patches-5.15/422-firmware-qcom-scm-fix-SCM-cold-boot-address.patch
View file

@ -1,138 +0,0 @@
From aaa675f07e781e248fcf169ce9a917b48bc2cc9b Mon Sep 17 00:00:00 2001
From: Brian Norris <computersforpeace@gmail.com>
Date: Fri, 28 Jul 2023 12:06:23 +0200
Subject: [PATCH 3/3] firmware: qcom: scm: fix SCM cold boot address
This effectively reverts upstream Linux commit 13e77747800e ("firmware:
qcom: scm: Use atomic SCM for cold boot"), because Google WiFi boot
firmwares don't support the atomic variant.
This fixes SMP support for Google WiFi.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
---
drivers/firmware/qcom_scm-legacy.c | 62 +++++++++++++++++++++++++-----
drivers/firmware/qcom_scm.c | 11 ++++++
2 files changed, 63 insertions(+), 10 deletions(-)
--- a/drivers/firmware/qcom_scm-legacy.c
+++ b/drivers/firmware/qcom_scm-legacy.c
@@ -13,6 +13,9 @@
#include <linux/arm-smccc.h>
#include <linux/dma-mapping.h>
+#include <asm/cacheflush.h>
+#include <asm/outercache.h>
+
#include "qcom_scm.h"
static DEFINE_MUTEX(qcom_scm_lock);
@@ -117,6 +120,25 @@ static void __scm_legacy_do(const struct
} while (res->a0 == QCOM_SCM_INTERRUPTED);
}
+static void qcom_scm_inv_range(unsigned long start, unsigned long end)
+{
+ u32 cacheline_size, ctr;
+
+ asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
+ cacheline_size = 4 << ((ctr >> 16) & 0xf);
+
+ start = round_down(start, cacheline_size);
+ end = round_up(end, cacheline_size);
+ outer_inv_range(start, end);
+ while (start < end) {
+ asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
+ : "memory");
+ start += cacheline_size;
+ }
+ dsb();
+ isb();
+}
+
/**
* scm_legacy_call() - Sends a command to the SCM and waits for the command to
* finish processing.
@@ -160,10 +182,16 @@ int scm_legacy_call(struct device *dev,
rsp = scm_legacy_command_to_response(cmd);
- cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
- if (dma_mapping_error(dev, cmd_phys)) {
- kfree(cmd);
- return -ENOMEM;
+ if (dev) {
+ cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
+ if (dma_mapping_error(dev, cmd_phys)) {
+ kfree(cmd);
+ return -ENOMEM;
+ }
+ } else {
+ cmd_phys = virt_to_phys(cmd);
+ __cpuc_flush_dcache_area(cmd, alloc_len);
+ outer_flush_range(cmd_phys, cmd_phys + alloc_len);
}
smc.args[0] = 1;
@@ -179,13 +207,26 @@ int scm_legacy_call(struct device *dev,
goto out;
do {
- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
- sizeof(*rsp), DMA_FROM_DEVICE);
+ if (dev) {
+ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) +
+ cmd_len, sizeof(*rsp),
+ DMA_FROM_DEVICE);
+ } else {
+ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) +
+ cmd_len;
+ qcom_scm_inv_range(start, start + sizeof(*rsp));
+ }
} while (!rsp->is_complete);
- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
- le32_to_cpu(rsp->buf_offset),
- resp_len, DMA_FROM_DEVICE);
+ if (dev) {
+ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
+ le32_to_cpu(rsp->buf_offset),
+ resp_len, DMA_FROM_DEVICE);
+ } else {
+ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) + cmd_len +
+ le32_to_cpu(rsp->buf_offset);
+ qcom_scm_inv_range(start, start + resp_len);
+ }
if (res) {
res_buf = scm_legacy_get_response_buffer(rsp);
@@ -193,7 +234,8 @@ int scm_legacy_call(struct device *dev,
res->result[i] = le32_to_cpu(res_buf[i]);
}
out:
- dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
+ if (dev)
+ dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
kfree(cmd);
return ret;
}
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -344,6 +344,17 @@ int qcom_scm_set_cold_boot_addr(void *en
desc.args[0] = flags;
desc.args[1] = virt_to_phys(entry);
+ /*
+ * Factory firmware doesn't support the atomic variant. Non-atomic SCMs
+ * require ugly DMA invalidation support that was dropped upstream a
+ * while ago. For more info, see:
+ *
+ * [RFC] qcom_scm: IPQ4019 firmware does not support atomic API?
+ * https://lore.kernel.org/linux-arm-msm/20200913201608.GA3162100@bDebian/
+ */
+ if (of_machine_is_compatible("google,wifi"))
+ return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL);
+
return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);

29
target/linux/ipq40xx/patches-5.15/444-mtd-nand-rawnand-add-support-for-Toshiba-TC58NVG0S3H.patch
View file

@ -1,29 +0,0 @@
From 35ca7e3e6ccd120d694a3425f37fc6374ad2e11e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20B=C3=B6hler?= <dev@aboehler.at>
Date: Wed, 20 Apr 2022 12:08:38 +0200
Subject: [PATCH] mtd: rawnand: add support for Toshiba TC58NVG0S3HTA00
NAND flash
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The Toshiba TC58NVG0S3HTA00 is detected with 64 byte OOB while the flash
has 128 bytes OOB. This adds a static NAND ID entry to correct this.
Tested on FRITZ!Box 7530 flashed with OpenWrt.
Signed-off-by: Andreas Böhler <dev@aboehler.at>
(changed id_len to 8, added comment about possible counterfeits)
---
--- a/drivers/mtd/nand/raw/nand_ids.c
+++ b/drivers/mtd/nand/raw/nand_ids.c
@@ -29,6 +29,9 @@ struct nand_flash_dev nand_flash_ids[] =
{"TC58NVG0S3E 1G 3.3V 8-bit",
{ .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
+ {"TC58NVG0S3HTA00 1G 3.3V 8-bit", /* possibly counterfeit chip - see commit */
+ { .id = {0x98, 0xf1, 0x80, 0x15} }, /* should be more bytes */
+ SZ_2K, SZ_128, SZ_128K, 0, 8, 128, NAND_ECC_INFO(8, SZ_512), },
{"TC58NVG2S0F 4G 3.3V 8-bit",
{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },

43
target/linux/ipq40xx/patches-5.15/700-skbuff-add-DSA-specific-data-to-struct-skb_shared_in.patch
View file

@ -1,43 +0,0 @@
From da75807ac41175e9db8c95f7a172b4133763b744 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <j4g8y7@gmail.com>
Date: Mon, 11 Jan 2021 17:49:36 +0100
Subject: [PATCH] skbuff: add DSA specific data to struct skb_shared_info
All of the already existing DSA tagging protocol drivers
are storing the tagging data directly into the skb. In most
cases that is the only way to send the required information
to the underlying ethernet switch.
However on certain platforms (like the Qualcomm IPQ40xx
SoCs) the built-in ethernet switch is connected directly
to an ethernet MAC, and the tagging information must be
sent out-of-band which is done directly via the hardware
TX descriptors of the ethernet MAC.
In such cases, putting the information into the skb causes
unneccesary overhead, because the ethernet driver must
remove that before sending the ethernet frame towards to
the hardware.
This change adds two new DSA specific fields to struct
skb_shared_info which makes it possible to send the
tagging information via skb->shinfo. With this approach,
the twofold modifications of the skb data can be avoided.
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
---
include/linux/skbuff.h | 3 +++
1 file changed, 3 insertions(+)
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -564,6 +564,9 @@ struct skb_shared_info {
unsigned int gso_type;
u32 tskey;
+ unsigned int dsa_tag_proto;
+ unsigned char dsa_tag_data[8];
+
/*
* Warning : all fields before dataref are cleared in __alloc_skb()
*/

187
target/linux/ipq40xx/patches-5.15/701-net-dsa-tag_ipq4019-add-shinfo-based-tagging-driver-.patch
View file

@ -1,187 +0,0 @@
From 29a0c2fae991cab142575c92276c0afdeb260ebe Mon Sep 17 00:00:00 2001
From: Gabor Juhos <j4g8y7@gmail.com>
Date: Thu, 28 Oct 2021 21:44:52 +0200
Subject: [PATCH] net: dsa: tag_ipq4019: add shinfo based tagging driver for
IPQ40xx
This change adds a tagging protocol driver for the built-in
ethernet switch of the Qualcomm Atheros IPQ4019 SoCs.
In comparison to the existing tagging protocols this hardware
requires a slightly different approach because the switch does
not use in-band tags.
On the receive path, the source port information is embedded
into the RX descriptors of the ethernet MAC hardware. Similarly,
the destination port mask must be sent via the TX descriptors
of the ethernet MAC when a packet is sent towards the switch.
In order to support this special requirements, this patch
adds a new tagging protocol driver.
The driver extracts the source port information directly
from the 'receive return descriptor' of the ethernet MAC.
It is possible because that descriptor is part of the skb
received from the ethernet driver.
Unfortunatley, it is not possible to put the destination
port information directly to the TX descriptors, because
those are handled internally by the driver of the ethernet
hardware.
To overcome this limitation, this tagging driver uses the
DSA specific fields in skb->shinfo to send the destination
port information to the ethernet driver.
A similar tagging driver is exist but that uses skb
extensions which causes unnecessary overhead.
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
---
include/linux/dsa/ipq4019.h | 11 ++++++
include/net/dsa.h | 2 +
net/dsa/Kconfig | 6 +++
net/dsa/Makefile | 1 +
net/dsa/tag_ipq4019.c | 79 +++++++++++++++++++++++++++++++++++++
5 files changed, 99 insertions(+)
create mode 100644 include/linux/dsa/ipq4019.h
create mode 100644 net/dsa/tag_ipq4019.c
--- /dev/null
+++ b/include/linux/dsa/ipq4019.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DSA_IPQ40XX_H
+#define DSA_IPQ40XX_H
+
+struct ipq40xx_dsa_tag_data {
+ u8 from_cpu;
+ u8 dp;
+};
+
+#endif /* DSA_IPQ40XX_H */
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -51,6 +51,7 @@ struct phylink_link_state;
#define DSA_TAG_PROTO_SEVILLE_VALUE 21
#define DSA_TAG_PROTO_BRCM_LEGACY_VALUE 22
#define DSA_TAG_PROTO_SJA1110_VALUE 23
+#define DSA_TAG_PROTO_IPQ4019_VALUE 24
enum dsa_tag_protocol {
DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
@@ -77,6 +78,7 @@ enum dsa_tag_protocol {
DSA_TAG_PROTO_OCELOT_8021Q = DSA_TAG_PROTO_OCELOT_8021Q_VALUE,
DSA_TAG_PROTO_SEVILLE = DSA_TAG_PROTO_SEVILLE_VALUE,
DSA_TAG_PROTO_SJA1110 = DSA_TAG_PROTO_SJA1110_VALUE,
+ DSA_TAG_PROTO_IPQ4019 = DSA_TAG_PROTO_IPQ4019_VALUE,
};
struct dsa_switch;
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -57,6 +57,12 @@ config NET_DSA_TAG_HELLCREEK
Say Y or M if you want to enable support for tagging frames
for the Hirschmann Hellcreek TSN switches.
+config NET_DSA_TAG_IPQ4019
+ tristate "Tag driver for Qualcomm Atheros IPQ4019 SoC built-in switch"
+ help
+ Say Y or M if you want to enable support for tagging frames for
+ the built-in switch of the Qualcomm Atheros IPQ4019 SoC-s.
+
config NET_DSA_TAG_GSWIP
tristate "Tag driver for Lantiq / Intel GSWIP switches"
help
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_NET_DSA_TAG_AR9331) += tag_
obj-$(CONFIG_NET_DSA_TAG_BRCM_COMMON) += tag_brcm.o
obj-$(CONFIG_NET_DSA_TAG_DSA_COMMON) += tag_dsa.o
obj-$(CONFIG_NET_DSA_TAG_GSWIP) += tag_gswip.o
+obj-$(CONFIG_NET_DSA_TAG_IPQ4019) += tag_ipq4019.o
obj-$(CONFIG_NET_DSA_TAG_HELLCREEK) += tag_hellcreek.o
obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o
obj-$(CONFIG_NET_DSA_TAG_RTL4_A) += tag_rtl4_a.o
--- /dev/null
+++ b/net/dsa/tag_ipq4019.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/* Copyright (c) 2021, Gabor Juhos <j4g8y7@gmail.com> */
+
+#include <linux/bitfield.h>
+#include <linux/dsa/ipq4019.h>
+
+#include "dsa_priv.h"
+
+/* Receive Return Descriptor */
+struct edma_rrd {
+ u16 rrd0;
+ u16 rrd1;
+ u16 rrd2;
+ u16 rrd3;
+ u16 rrd4;
+ u16 rrd5;
+ u16 rrd6;
+ u16 rrd7;
+} __packed;
+
+#define EDMA_RRD_SIZE sizeof(struct edma_rrd)
+
+#define EDMA_RRD1_PORT_ID_MASK GENMASK(14, 12)
+
+static struct sk_buff *ipq4019_sh_tag_xmit(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ struct dsa_port *dp = dsa_slave_to_port(dev);
+ struct ipq40xx_dsa_tag_data *tag_data;
+
+ BUILD_BUG_ON(sizeof_field(struct skb_shared_info, dsa_tag_data) <
+ sizeof(struct ipq40xx_dsa_tag_data));
+
+ skb_shinfo(skb)->dsa_tag_proto = DSA_TAG_PROTO_IPQ4019;
+ tag_data = (struct ipq40xx_dsa_tag_data *)skb_shinfo(skb)->dsa_tag_data;
+
+ tag_data->from_cpu = 1;
+ /* set the destination port information */
+ tag_data->dp = BIT(dp->index);
+
+ return skb;
+}
+
+static struct sk_buff *ipq4019_sh_tag_rcv(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ struct edma_rrd *rrd;
+ int offset;
+ int port;
+
+ offset = EDMA_RRD_SIZE + ETH_HLEN;
+ if (unlikely(skb_headroom(skb) < offset))
+ return NULL;
+
+ rrd = (struct edma_rrd *)(skb->data - offset);
+ port = FIELD_GET(EDMA_RRD1_PORT_ID_MASK, rrd->rrd1);
+
+ skb->dev = dsa_master_find_slave(dev, 0, port);
+ if (!skb->dev)
+ return NULL;
+
+ return skb;
+}
+
+const struct dsa_device_ops ipq4019_sh_tag_dsa_ops = {
+ .name = "ipq4019-sh",
+ .proto = DSA_TAG_PROTO_IPQ4019,
+ .xmit = ipq4019_sh_tag_xmit,
+ .rcv = ipq4019_sh_tag_rcv,
+};
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("DSA tag driver for the IPQ4019 SoC built-in ethernet switch");
+MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>");
+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_IPQ4019);
+
+module_dsa_tag_driver(ipq4019_sh_tag_dsa_ops);

43
target/linux/ipq40xx/patches-5.15/702-net-ethernet-qualcomm-add-IPQESS-support.patch
View file

@ -1,43 +0,0 @@
From 4f488235f498db43f2412116dea6e02c7fb20216 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 1 Nov 2021 12:36:51 +0100
Subject: [PATCH] net: ethernet: qualcomm: add IPQESS support
Allow compiling the IPQESS driver that supports the
Qualcomm IPQ40xx SoC built-in ethernet controller.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/net/ethernet/qualcomm/Kconfig | 11 +++++++++++
drivers/net/ethernet/qualcomm/Makefile | 1 +
2 files changed, 12 insertions(+)
--- a/drivers/net/ethernet/qualcomm/Kconfig
+++ b/drivers/net/ethernet/qualcomm/Kconfig
@@ -60,6 +60,17 @@ config QCOM_EMAC
low power, Receive-Side Scaling (RSS), and IEEE 1588-2008
Precision Clock Synchronization Protocol.
+config QCOM_IPQ4019_ESS_EDMA
+ tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
+ depends on OF
+ select PHYLINK
+ help
+ This driver supports the Qualcomm Atheros IPQ40xx built-in
+ ESS EDMA ethernet controller.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ipqess.
+
source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
endif # NET_VENDOR_QUALCOMM
--- a/drivers/net/ethernet/qualcomm/Makefile
+++ b/drivers/net/ethernet/qualcomm/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o
qcauart-objs := qca_uart.o
obj-y += emac/
+obj-y += ipqess/
obj-$(CONFIG_RMNET) += rmnet/

81
target/linux/ipq40xx/patches-5.15/703-arm-dts-ipq4019-add-ethernet-controller-DT-node.patch
View file

@ -1,81 +0,0 @@
From 44327d7098d4f32c24ec8c528e5aff6e030956bc Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Wed, 20 Oct 2021 13:21:45 +0200
Subject: [PATCH] arm: dts: ipq4019: add ethernet controller DT node
Since IPQ40xx SoC built-in ethernet controller now has a driver,
add its DT node so it can be used.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -38,6 +38,7 @@
spi1 = &blsp1_spi2;
i2c0 = &blsp1_i2c3;
i2c1 = &blsp1_i2c4;
+ ethernet0 = &gmac;
};
cpus {
@@ -589,6 +590,57 @@
status = "disabled";
};
+ gmac: ethernet@c080000 {
+ compatible = "qcom,ipq4019-ess-edma";
+ reg = <0xc080000 0x8000>;
+ resets = <&gcc ESS_RESET>;
+ reset-names = "ess_rst";
+ clocks = <&gcc GCC_ESS_CLK>;
+ clock-names = "ess_clk";
+ interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
+
+ status = "disabled";
+
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ asym-pause;
+ };
+ };
+
mdio: mdio@90000 {
#address-cells = <1>;
#size-cells = <0>;

69
target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch
View file

@ -1,69 +0,0 @@
From 157ac9f52fd9b9a22cf12f7755a905fb34ef72f7 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <j4g8y7@gmail.com>
Date: Fri, 25 Dec 2020 08:02:47 +0100
Subject: [PATCH] net: phy: define PSGMII PHY interface mode
The PSGMII interface is similar to QSGMII. The main difference
is that the PSGMII interface combines five SGMII lines into a
single link while in QSGMII only four lines are combined.
Similarly to the QSGMII, this interface mode might also needs
special handling within the MAC driver.
Add definitions for the PHY layer to allow to express this type
of connection between the MAC and PHY.
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
---
Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 +
drivers/net/phy/phylink.c | 2 ++
include/linux/phy.h | 3 +++
3 files changed, 6 insertions(+)
--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
@@ -64,6 +64,7 @@ properties:
- mii
- gmii
- sgmii
+ - psgmii
- qsgmii
- tbi
- rev-mii
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -371,6 +371,7 @@ void phylink_get_linkmodes(unsigned long
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_PSGMII:
case PHY_INTERFACE_MODE_QSGMII:
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_GMII:
@@ -634,6 +635,7 @@ static int phylink_parse_mode(struct phy
switch (pl->link_config.interface) {
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_PSGMII:
case PHY_INTERFACE_MODE_QSGMII:
phylink_set(pl->supported, 10baseT_Half);
phylink_set(pl->supported, 10baseT_Full);
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -139,6 +139,7 @@ typedef enum {
PHY_INTERFACE_MODE_XGMII,
PHY_INTERFACE_MODE_XLGMII,
PHY_INTERFACE_MODE_MOCA,
+ PHY_INTERFACE_MODE_PSGMII,
PHY_INTERFACE_MODE_QSGMII,
PHY_INTERFACE_MODE_TRGMII,
PHY_INTERFACE_MODE_100BASEX,
@@ -244,6 +245,8 @@ static inline const char *phy_modes(phy_
return "xlgmii";
case PHY_INTERFACE_MODE_MOCA:
return "moca";
+ case PHY_INTERFACE_MODE_PSGMII:
+ return "psgmii";
case PHY_INTERFACE_MODE_QSGMII:
return "qsgmii";
case PHY_INTERFACE_MODE_TRGMII:

57
target/linux/ipq40xx/patches-5.15/705-net-dsa-add-Qualcomm-IPQ4019-built-in-switch-support.patch
View file

@ -1,57 +0,0 @@
From b5f71652b85a85ea53162e9e2b760b84fd0d254f Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 1 Nov 2021 18:10:28 +0100
Subject: [PATCH] net: dsa: add Qualcomm IPQ4019 built-in switch support
Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in.
It shares most of the stuff with its external counterpart, however it is
modified for the SoC.
Namely, it doesn't have second CPU port (Port 6), so it has 6 ports
instead of 7.
It also has no built-in PHY-s but rather requires external PSGMII based
companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry
out calibration before using them.
PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which
unfortunately requires some magic values as the datasheet doesnt document
the bits that are being set or the register at all.
Since its built-in it is MMIO like other peripherals and doesn't have its
own MDIO bus but depends on the SoC provided one.
CPU connection is at Port 0 and it uses some kind of a internal connection
and no traditional RGMII/SGMII.
It also doesn't use in-band tagging like other qca8k switches so a shinfo
based tagger is used.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/net/dsa/qca/Kconfig | 9 +++++++++
drivers/net/dsa/qca/Makefile | 1 +
2 files changed, 10 insertions(+)
--- a/drivers/net/dsa/qca/Kconfig
+++ b/drivers/net/dsa/qca/Kconfig
@@ -23,3 +23,13 @@ config NET_DSA_QCA8K_LEDS_SUPPORT
help
This enabled support for LEDs present on the Qualcomm Atheros
QCA8K Ethernet switch chips.
+
+config NET_DSA_QCA8K_IPQ4019
+ tristate "Qualcomm Atheros IPQ4019 built-in Ethernet switch support"
+ depends on HAS_IOMEM && NET_DSA
+ select NET_DSA_TAG_IPQ4019
+ select REGMAP
+ help
+ This enables support for the Qualcomm Atheros IPQ4019 SoC built-in
+ Ethernet switch.
+
--- a/drivers/net/dsa/qca/Makefile
+++ b/drivers/net/dsa/qca/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_NET_DSA_AR9331) += ar9331.o
+obj-$(CONFIG_NET_DSA_QCA8K_IPQ4019) += qca8k-ipq4019.o
obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o
qca8k-y += qca8k-common.o qca8k-8xxx.o
ifdef CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT

98
target/linux/ipq40xx/patches-5.15/706-arm-dts-ipq4019-add-switch-node.patch
View file

@ -1,98 +0,0 @@
From ebb62523990a27b3a25e422fa575619f7f725a20 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 1 Nov 2021 18:15:04 +0100
Subject: [PATCH] arm: dts: ipq4019: add switch node
Since the built-in IPQ40xx switch now has a driver, add the required node
for it to work.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 78 +++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -590,6 +590,82 @@
status = "disabled";
};
+ switch: switch@c000000 {
+ compatible = "qca,ipq4019-qca8337n";
+ reg = <0xc000000 0x80000>, <0x98000 0x800>;
+ reg-names = "base", "psgmii_phy";
+ resets = <&gcc ESS_PSGMII_ARES>;
+ reset-names = "psgmii_rst";
+ mdio = <&mdio>;
+ psgmii-ethphy = <&psgmiiphy>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 { /* MAC0 */
+ reg = <0>;
+ label = "cpu";
+ ethernet = <&gmac>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ asym-pause;
+ };
+ };
+
+ swport1: port@1 { /* MAC1 */
+ reg = <1>;
+ label = "lan1";
+ phy-handle = <&ethphy0>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport2: port@2 { /* MAC2 */
+ reg = <2>;
+ label = "lan2";
+ phy-handle = <&ethphy1>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport3: port@3 { /* MAC3 */
+ reg = <3>;
+ label = "lan3";
+ phy-handle = <&ethphy2>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport4: port@4 { /* MAC4 */
+ reg = <4>;
+ label = "lan4";
+ phy-handle = <&ethphy3>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+
+ swport5: port@5 { /* MAC5 */
+ reg = <5>;
+ label = "wan";
+ phy-handle = <&ethphy4>;
+ phy-mode = "psgmii";
+
+ status = "disabled";
+ };
+ };
+ };
+
gmac: ethernet@c080000 {
compatible = "qcom,ipq4019-ess-edma";
reg = <0xc080000 0x8000>;

61
target/linux/ipq40xx/patches-5.15/707-dt-bindings-net-add-QCA807x-PHY.patch
View file

@ -1,61 +0,0 @@
From c66863c1ba8995b61e6d727d78a241c734f5bb57 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Thu, 1 Oct 2020 15:05:35 +0200
Subject: [PATCH] dt-bindings: net: add QCA807x PHY
Add DT bindings for Qualcomm QCA807x PHY series.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 include/dt-bindings/net/qcom-qca807x.h
--- /dev/null
+++ b/include/dt-bindings/net/qcom-qca807x.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Device Tree constants for the Qualcomm QCA807X PHYs
+ */
+
+#ifndef _DT_BINDINGS_QCOM_QCA807X_H
+#define _DT_BINDINGS_QCOM_QCA807X_H
+
+#define PSGMII_QSGMII_TX_DRIVER_140MV 0
+#define PSGMII_QSGMII_TX_DRIVER_160MV 1
+#define PSGMII_QSGMII_TX_DRIVER_180MV 2
+#define PSGMII_QSGMII_TX_DRIVER_200MV 3
+#define PSGMII_QSGMII_TX_DRIVER_220MV 4
+#define PSGMII_QSGMII_TX_DRIVER_240MV 5
+#define PSGMII_QSGMII_TX_DRIVER_260MV 6
+#define PSGMII_QSGMII_TX_DRIVER_280MV 7
+#define PSGMII_QSGMII_TX_DRIVER_300MV 8
+#define PSGMII_QSGMII_TX_DRIVER_320MV 9
+#define PSGMII_QSGMII_TX_DRIVER_400MV 10
+#define PSGMII_QSGMII_TX_DRIVER_500MV 11
+/* Default value */
+#define PSGMII_QSGMII_TX_DRIVER_600MV 12
+
+/* Full amplitude, full bias current */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS 0
+/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS 1
+/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS 2
+/* Both amplitude and bias current follow DSP */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS 3
+/* Full amplitude, half bias current */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS 4
+/* Amplitude follow DSP setting; 1/4 bias current when cable<10m,
+ * otherwise half bias current
+ */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS 5
+/* Full amplitude; same bias current setting with “010” and “011”,
+ * but half more bias is reduced when cable <10m
+ */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT 6
+/* Amplitude follow DSP; same bias current setting with “110”, default value */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT 7
+
+#endif

50
target/linux/ipq40xx/patches-5.15/708-net-phy-Add-Qualcom-QCA807x-driver.patch
View file

@ -1,50 +0,0 @@
From f825cdc8bfde7616a14e2163f16303a8973031d2 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Wed, 7 Oct 2020 17:38:48 +0200
Subject: [PATCH] net: phy: Add Qualcom QCA807x driver
This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.
They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s.
They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber.
Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber.
Each PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s.
But some vendors used these to driver generic LED-s controlled by userspace,
so lets enable registering each PHY as GPIO controller and add driver for it.
These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/net/phy/Kconfig | 6 ++++++
drivers/net/phy/Makefile | 1 +
2 files changed, 7 insertions(+)
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -347,6 +347,12 @@ config AT803X_PHY
Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
QCA8337(Internal qca8k PHY) model
+config QCA807X_PHY
+ tristate "Qualcomm QCA807X PHYs"
+ depends on OF_MDIO
+ help
+ Currently supports the QCA8072 and QCA8075 models.
+
config QSEMI_PHY
tristate "Quality Semiconductor PHYs"
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -92,6 +92,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp-c45-tja11xx.o
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
+obj-$(CONFIG_QCA807X_PHY) += qca807x.o
obj-$(CONFIG_REALTEK_PHY) += realtek.o
obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o

61
target/linux/ipq40xx/patches-5.15/709-arm-dts-ipq4019-QCA807x-properties.patch
View file

@ -1,61 +0,0 @@
From e0fa88eaa3c176b71e563da68949ac2ab45aaa61 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Fri, 2 Oct 2020 10:43:26 +0200
Subject: [PATCH] arm: dts: ipq4019: QCA807x properties
This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/net/qcom-qca807x.h>
/ {
#address-cells = <1>;
@@ -726,22 +727,38 @@
ethphy0: ethernet-phy@0 {
reg = <0>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy3: ethernet-phy@3 {
reg = <3>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy4: ethernet-phy@4 {
reg = <4>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ psgmiiphy: psgmii-phy@5 {
+ reg = <5>;
+
+ qcom,tx-driver-strength = <PSGMII_QSGMII_TX_DRIVER_300MV>;
};
};

180
target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch
View file

@ -1,180 +0,0 @@
From: Christian Lamparter <chunkeey@googlemail.com>
Subject: SoC: add qualcomm syscon
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
obj-$(CONFIG_QCOM_SMSM) += smsm.o
obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o
obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
obj-$(CONFIG_QCOM_APR) += apr.o
obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -192,6 +192,13 @@ config QCOM_SOCINFO
Say yes here to support the Qualcomm socinfo driver, providing
information about the SoC to user space.
+config QCOM_TCSR
+ tristate "QCOM Top Control and Status Registers"
+ depends on ARCH_QCOM
+ help
+ Say y here to enable TCSR support. The TCSR provides control
+ functions for various peripherals.
+
config QCOM_WCNSS_CTRL
tristate "Qualcomm WCNSS control driver"
depends on ARCH_QCOM || COMPILE_TEST
--- /dev/null
+++ b/drivers/soc/qcom/qcom_tcsr.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License rev 2 and
+ * only rev 2 as published by the free Software foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#define TCSR_USB_PORT_SEL 0xb0
+#define TCSR_USB_HSPHY_CONFIG 0xC
+
+#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0
+#define TCSR_ESS_INTERFACE_SEL_MASK 0xf
+
+#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0
+#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4
+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4
+
+static int tcsr_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ const struct device_node *node = pdev->dev.of_node;
+ void __iomem *base;
+ u32 val;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
+ dev_err(&pdev->dev, "setting usb port select = %d\n", val);
+ writel(val, base + TCSR_USB_PORT_SEL);
+ }
+
+ if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
+ dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
+ writel(val, base + TCSR_USB_HSPHY_CONFIG);
+ }
+
+ if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
+ u32 tmp = 0;
+ dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
+ tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
+ tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
+ tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
+ writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
+ }
+
+ if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
+ dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
+ writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
+ writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
+ }
+
+ if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
+ dev_info(&pdev->dev,
+ "setting wifi_noc_memtype_m0_m2 = %x\n", val);
+ writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id tcsr_dt_match[] = {
+ { .compatible = "qcom,tcsr", },
+ { },
+};
+
+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
+
+static struct platform_driver tcsr_driver = {
+ .driver = {
+ .name = "tcsr",
+ .owner = THIS_MODULE,
+ .of_match_table = tcsr_dt_match,
+ },
+ .probe = tcsr_probe,
+};
+
+module_platform_driver(tcsr_driver);
+
+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
+MODULE_DESCRIPTION("QCOM TCSR driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+++ b/include/dt-bindings/soc/qcom,tcsr.h
@@ -0,0 +1,48 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_QCOM_TCSR_H
+#define __DT_BINDINGS_QCOM_TCSR_H
+
+#define TCSR_USB_SELECT_USB3_P0 0x1
+#define TCSR_USB_SELECT_USB3_P1 0x2
+#define TCSR_USB_SELECT_USB3_DUAL 0x3
+
+/* IPQ40xx HS PHY Mode Select */
+#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7
+#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7
+
+/* IPQ40xx ess interface mode select */
+#define TCSR_ESS_PSGMII 0
+#define TCSR_ESS_PSGMII_RGMII5 1
+#define TCSR_ESS_PSGMII_RMII0 2
+#define TCSR_ESS_PSGMII_RMII1 4
+#define TCSR_ESS_PSGMII_RMII0_RMII1 6
+#define TCSR_ESS_PSGMII_RGMII4 9
+
+/*
+ * IPQ40xx WiFi Global Config
+ * Bit 30:AXID_EN
+ * Enable AXI master bus Axid translating to confirm all txn submitted by order
+ * Bit 24: Use locally generated socslv_wxi_bvalid
+ * 1: use locally generate socslv_wxi_bvalid for performance.
+ * 0: use SNOC socslv_wxi_bvalid.
+ */
+#define TCSR_WIFI_GLB_CFG 0x41000000
+
+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222
+
+/* TCSR A/B REG */
+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0
+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1
+
+#endif

27
target/linux/ipq40xx/patches-5.15/910-Revert-firmware-qcom_scm-Clear-download-bit-during-r.patch
View file

@ -1,27 +0,0 @@
From c668fd2c4d9ad4a510fd214a2da83bd9b67a2508 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sun, 13 Aug 2023 18:13:08 +0200
Subject: [PATCH] Revert "firmware: qcom_scm: Clear download bit during reboot"
This reverts commit a3ea89b5978dbcd0fa55f675c5a1e04611093709.
It is breaking reboot on IPQ4019 boards, so revert until a proper fix
is found.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/firmware/qcom_scm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -1361,7 +1361,8 @@ static int qcom_scm_probe(struct platfor
static void qcom_scm_shutdown(struct platform_device *pdev)
{
/* Clean shutdown, disable download mode to allow normal restart */
- qcom_scm_set_download_mode(false);
+ if (download_mode)
+ qcom_scm_set_download_mode(false);
}
static const struct of_device_id qcom_scm_dt_match[] = {

43
target/linux/ipq40xx/patches-5.15/998-lantiq-atm-hacks.patch
View file

@ -1,43 +0,0 @@
From: John Crispin <blogic@openwrt.org>
Date: Fri, 3 Aug 2012 10:27:25 +0200
Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/include/uapi/linux/atm.h
+++ b/include/uapi/linux/atm.h
@@ -131,8 +131,14 @@
#define ATM_ABR 4
#define ATM_ANYCLASS 5 /* compatible with everything */
+#define ATM_VBR_NRT ATM_VBR
+#define ATM_VBR_RT 6
+#define ATM_UBR_PLUS 7
+#define ATM_GFR 8
+
#define ATM_MAX_PCR -1 /* maximum available PCR */
+
struct atm_trafprm {
unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */
int max_pcr; /* maximum PCR in cells per second */
@@ -155,6 +161,9 @@ struct atm_trafprm {
unsigned int adtf :10; /* ACR Decrease Time Factor (10-bit) */
unsigned int cdf :3; /* Cutoff Decrease Factor (3-bit) */
unsigned int spare :9; /* spare bits */
+ int scr; /* sustained rate in cells per second */
+ int mbs; /* maximum burst size (MBS) in cells */
+ int cdv; /* Cell delay variation */
};
struct atm_qos {
--- a/net/atm/proc.c
+++ b/net/atm/proc.c
@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil
static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
{
static const char *const class_name[] = {
- "off", "UBR", "CBR", "VBR", "ABR"};
+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
static const char *const aal_name[] = {
"---", "1", "2", "3/4", /* 0- 3 */
"???", "5", "???", "???", /* 4- 7 */

137
target/linux/ipq40xx/patches-5.15/999-atm-mpoa-intel-dsl-phy-support.patch
View file

@ -1,137 +0,0 @@
From: Subhra Banerjee <subhrax.banerjee@intel.com>
Date: Fri, 31 Aug 2018 12:01:19 +0530
Subject: [PATCH] UGW_SW-29163: ATM oam support
--- a/drivers/net/ppp/ppp_generic.c
+++ b/drivers/net/ppp/ppp_generic.c
@@ -2952,6 +2952,22 @@ char *ppp_dev_name(struct ppp_channel *c
return name;
}
+/*
+ * Return the PPP device interface pointer
+ */
+struct net_device *ppp_device(struct ppp_channel *chan)
+{
+ struct channel *pch = chan->ppp;
+ struct net_device *dev = NULL;
+
+ if (pch) {
+ read_lock_bh(&pch->upl);
+ if (pch->ppp && pch->ppp->dev)
+ dev = pch->ppp->dev;
+ read_unlock_bh(&pch->upl);
+ }
+ return dev;
+}
/*
* Disconnect a channel from the generic layer.
@@ -3598,6 +3614,7 @@ EXPORT_SYMBOL(ppp_unregister_channel);
EXPORT_SYMBOL(ppp_channel_index);
EXPORT_SYMBOL(ppp_unit_number);
EXPORT_SYMBOL(ppp_dev_name);
+EXPORT_SYMBOL(ppp_device);
EXPORT_SYMBOL(ppp_input);
EXPORT_SYMBOL(ppp_input_error);
EXPORT_SYMBOL(ppp_output_wakeup);
--- a/include/linux/ppp_channel.h
+++ b/include/linux/ppp_channel.h
@@ -74,6 +74,9 @@ extern int ppp_unit_number(struct ppp_ch
/* Get the device name associated with a channel, or NULL if none */
extern char *ppp_dev_name(struct ppp_channel *);
+/* Get the device pointer associated with a channel, or NULL if none */
+extern struct net_device *ppp_device(struct ppp_channel *);
+
/*
* SMP locking notes:
* The channel code must ensure that when it calls ppp_unregister_channel,
--- a/net/atm/Kconfig
+++ b/net/atm/Kconfig
@@ -56,6 +56,12 @@ config ATM_MPOA
subnetwork boundaries. These shortcut connections bypass routers
enhancing overall network performance.
+config ATM_MPOA_INTEL_DSL_PHY_SUPPORT
+ bool "Intel DSL Phy MPOA support"
+ depends on ATM && INET && ATM_MPOA!=n
+ help
+ Add support for Intel DSL Phy ATM MPOA
+
config ATM_BR2684
tristate "RFC1483/2684 Bridged protocols"
depends on ATM && INET
--- a/net/atm/br2684.c
+++ b/net/atm/br2684.c
@@ -596,6 +596,11 @@ static int br2684_regvcc(struct atm_vcc
atmvcc->push = br2684_push;
atmvcc->pop = br2684_pop;
atmvcc->release_cb = br2684_release_cb;
+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
+ if (atm_hook_mpoa_setup) /* IPoA or EoA w/o FCS */
+ atm_hook_mpoa_setup(atmvcc, brdev->payload == p_routed ? 3 : 0,
+ brvcc->encaps == BR2684_ENCAPS_LLC ? 1 : 0, net_dev);
+#endif
atmvcc->owner = THIS_MODULE;
/* initialize netdev carrier state */
--- a/net/atm/common.c
+++ b/net/atm/common.c
@@ -137,6 +137,11 @@ static struct proto vcc_proto = {
.release_cb = vcc_release_cb,
};
+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
+void (*atm_hook_mpoa_setup)(struct atm_vcc *, int, int, struct net_device *) = NULL;
+EXPORT_SYMBOL(atm_hook_mpoa_setup);
+#endif
+
int vcc_create(struct net *net, struct socket *sock, int protocol, int family, int kern)
{
struct sock *sk;
--- a/net/atm/common.h
+++ b/net/atm/common.h
@@ -53,4 +53,6 @@ int svc_change_qos(struct atm_vcc *vcc,s
void atm_dev_release_vccs(struct atm_dev *dev);
+extern void (*atm_hook_mpoa_setup)(struct atm_vcc *, int, int, struct net_device *);
+
#endif
--- a/net/atm/mpc.c
+++ b/net/atm/mpc.c
@@ -31,6 +31,7 @@
/* Modular too */
#include <linux/module.h>
+#include "common.h"
#include "lec.h"
#include "mpc.h"
#include "resources.h"
@@ -645,6 +646,10 @@ static int atm_mpoa_vcc_attach(struct at
vcc->proto_data = mpc->dev;
vcc->push = mpc_push;
+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
+ if (atm_hook_mpoa_setup) /* IPoA, LLC */
+ atm_hook_mpoa_setup(vcc, 3, 1, mpc->dev);
+#endif
return 0;
}
--- a/net/atm/pppoatm.c
+++ b/net/atm/pppoatm.c
@@ -422,6 +422,12 @@ static int pppoatm_assign_vcc(struct atm
atmvcc->user_back = pvcc;
atmvcc->push = pppoatm_push;
atmvcc->pop = pppoatm_pop;
+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
+ if (atm_hook_mpoa_setup) /* PPPoA */
+ atm_hook_mpoa_setup(atmvcc, 2,
+ pvcc->encaps == e_llc ? 1 : 0,
+ ppp_device(&pvcc->chan));
+#endif
atmvcc->release_cb = pppoatm_release_cb;
__module_get(THIS_MODULE);
atmvcc->owner = THIS_MODULE;

306
target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts Normal file
View file

@ -0,0 +1,306 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "mt7986a.dtsi"
/ {
model = "GL.iNet GL-MT6000";
compatible = "glinet,gl-mt6000", "mediatek,mt7986a";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=PARTLABEL=rootfs rootwait";
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1.8vd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led_run: led@0 {
label = "blue:run";
gpios = <&pio 38 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led@1 {
label = "white:system";
gpios = <&pio 37 GPIO_ACTIVE_LOW>;
};
};
usb_vbus: regulator-usb-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpios = <&pio 24 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-mode = "2500base-x";
phy-handle = <&phy1>;
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
phy1: phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <1>;
reset-assert-us = <100000>;
reset-deassert-us = <100000>;
reset-gpios = <&pio 10 GPIO_ACTIVE_LOW>;
interrupt-parent = <&pio>;
interrupts = <46 IRQ_TYPE_LEVEL_LOW>;
realtek,aldps-enable;
};
phy7: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <7>;
reset-assert-us = <100000>;
reset-deassert-us = <100000>;
reset-gpios = <&pio 19 GPIO_ACTIVE_LOW>;
interrupt-parent = <&pio>;
interrupts = <47 IRQ_TYPE_LEVEL_LOW>;
realtek,aldps-enable;
};
switch: switch@31 {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 18 GPIO_ACTIVE_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan2";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan4";
};
port@3 {
reg = <3>;
label = "lan5";
};
port@5 {
reg = <5>;
label = "lan1";
phy-handle = <&phy7>;
phy-mode = "2500base-x";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
};
};
&pio {
wf_2g_5g_pins: wf_2g_5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
mmc0_pins_default: mmc0-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
};
&crypto {
status = "okay";
};
&ssusb {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&usb_vbus>;
status = "okay";
};
&trng {
status = "okay";
};
&uart0 {
status = "okay";
};
&usb_phy {
status = "okay";
};
&watchdog {
status = "okay";
};
&wifi {
pinctrl-names = "default";
pinctrl-0 = <&wf_2g_5g_pins>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <8>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x14014>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
no-sd;
no-sdio;
status = "okay";
};

6
target/linux/mediatek/filogic/base-files/etc/board.d/02_network
View file

@ -48,6 +48,7 @@ mediatek_setup_interfaces()
qihoo,360t7)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" wan
;;
glinet,gl-mt6000|\
tplink,tl-xdr4288|\
tplink,tl-xdr6088)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" eth1
@ -90,6 +91,11 @@ mediatek_setup_macs()
wan_mac=$(macaddr_add "$lan_mac" 3)
label_mac=$lan_mac
;;
glinet,gl-mt6000)
label_mac=$(mmc_get_mac_binary factory 0x0a)
wan_mac=$label_mac
lan_mac=$(macaddr_add "$label_mac" 2)
;;
h3c,magic-nx30-pro)
wan_mac=$(mtd_get_mac_ascii pdt_data_1 ethaddr)
lan_mac=$(macaddr_add "$wan_mac" 1)

7
target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata
View file

@ -36,6 +36,13 @@ case "$FIRMWARE" in
;;
esac
;;
"mediatek/mt7986_eeprom_mt7976_dual.bin")
case "$board" in
glinet,gl-mt6000)
caldata_extract_mmc "factory" 0x0 0x1000
;;
esac
;;
*)
exit 1
;;

5
target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
View file

@ -43,6 +43,11 @@ case "$board" in
[ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress
;;
glinet,gl-mt6000)
addr=$(mmc_get_mac_binary factory 0x04)
[ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress
;;
h3c,magic-nx30-pro)
addr=$(mtd_get_mac_ascii pdt_data_1 ethaddr)
[ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress

6
target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh
View file

@ -84,6 +84,11 @@ platform_do_upgrade() {
cudy,wr3000-v1)
default_do_upgrade "$1"
;;
glinet,gl-mt6000)
CI_KERNPART="kernel"
CI_ROOTPART="rootfs"
emmc_do_upgrade "$1"
;;
mercusys,mr90x-v1)
CI_UBIPART="ubi0"
nand_do_upgrade "$1"
@ -150,6 +155,7 @@ platform_copy_config() {
;;
esac
;;
glinet,gl-mt6000|\
ubnt,unifi-6-plus)
emmc_copy_config
;;

15
target/linux/mediatek/image/filogic.mk
View file

@ -239,6 +239,21 @@ define Device/glinet_gl-mt3000
endef
TARGET_DEVICES += glinet_gl-mt3000
define Device/glinet_gl-mt6000
DEVICE_VENDOR := GL.iNet
DEVICE_MODEL := GL-MT6000
DEVICE_DTS := mt7986a-glinet-gl-mt6000
DEVICE_DTS_DIR := ../dts
DEVICE_PACKAGES := kmod-usb2 kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware e2fsprogs f2fsck mkf2fs
IMAGES += factory.bin
IMAGE/factory.bin := append-kernel | pad-to 32M | append-rootfs
IMAGE/sysupgrade.bin := sysupgrade-tar | append-gl-metadata
ARTIFACTS := preloader.bin bl31-uboot.fip
ARTIFACT/preloader.bin := mt7986-bl2 emmc-ddr4
ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot glinet_gl-mt6000
endef
TARGET_DEVICES += glinet_gl-mt6000
define Device/h3c_magic-nx30-pro
DEVICE_VENDOR := H3C
DEVICE_MODEL := Magic NX30 Pro

12
target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later or MIT
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/include/ "fsl/p1010si-pre.dtsi"
@ -13,7 +14,6 @@
led-failsafe = &led_power_red;
led-running = &led_power_green;
led-upgrade = &led_power_red;
label-mac-device = &enet0;
};
chosen {
@ -71,6 +71,16 @@
};
};
keys {
compatible = "gpio-keys";
reset {
label = "Reset button";
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;

192
target/linux/ramips/dts/mt7621_comfast_cf-ew72-v2.dts Normal file
View file

@ -0,0 +1,192 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "mt7621.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
compatible = "comfast,cf-ew72-v2", "mediatek,mt7621-soc";
model = "COMFAST CF-EW72 V2";
// There are at least two HW variants of cf-ew72-v2:
// With external RAM chip and with integrated RAM (RAM chip not soldered).
// Both act same.
chosen {
bootargs = "console=ttyS0,115200";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
// The only both visible and controllable indicator is wifi LED.
// CF-EW72 have 8 LEDs:
// "wlan" is the only LED is controllable with GPIO and have proper hole in shell.
// "power", "wan" and "lan" LEDs have proper holes in shell, but can not be controlled with GPIO
// "hidden_led_2" and "hidden_led_4" can be controlled with GPIO, but have no proper holes in shell
// "hidden_led_2" is between POWER and WAN LEDs
// "hidden_led_4" is between WAN and LAN LEDs
// "noconn_led_6" and "noconn_led_8" exist, but have no proper holes in shell and not controlled:
// "noconn_led_6" is between LAN and WLAN LEDs
// "noconn_led_8" is after WLAN LED
// LED "hidden_led_2" between POWER and WAN LEDs is controllable with GPIO, but it has no proper hole in shell;
// LED "hidden_led_4" between WAN and LAN LEDs is controllable with GPIO, but it has no proper hole in shell;
// TABLE of LEDs. All leds are blue.
//
// Place (WAN->ANT) | Num | GPIO | LED name (LuCI) | Note
// -----------------|-----|-----------------------------------------------------------------------------------------
// power | 1 | | | POWER LED. Not controlled with GPIO.
// hidden_led_2 | 2 | 13 | blue:hidden_led_2 | This LED does not have proper hole in shell.
// wan | 3 | | | WAN LED. Not controlled with GPIO.
// hidden_led_4 | 4 | 16 | blue:hidden_led_4 | This LED does not have proper hole in shell.
// lan | 5 | | | LAN LED. Not controlled with GPIO.
// noconn_led_6 | 6 | | | Not controlled with GPIO, possibly not connected
// wlan | 7 | 15 | blue:wlan | WLAN LED. Wireless indicator.
// noconn_led_8 | 8 | | | Not controlled with GPIO, possibly not connected
hidden_led_2_blue {
label = "blue:hidden_led_2";
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
};
hidden_led_4_blue {
label = "blue:hidden_led_4";
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
wlan_blue {
label = "blue:wlan";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};
};
aliases {
label-mac-device = &wan;
};
};
&spi0 {
status = "okay";
flash@0 {
compatible = "w25q128";
reg = <0>;
spi-max-frequency = <10000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Bootloader";
reg = <0x0 0x30000>;
read-only;
};
partition@30000 {
label = "Config";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@40000 {
label = "factory";
compatible = "nvmem-cells";
reg = <0x40000 0x10000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_e000: macaddr@e000 {
compatible = "mac-base";
reg = <0xe000 0x6>;
#nvmem-cell-cells = <1>;
};
// Serial number can be found in "factory" at 0xE100.
// it starts and ends with double quotes `"` and is ASCII string
};
};
partition@50000 {
label = "firmware";
compatible = "denx,uimage";
reg = <0x50000 0xfb0000>;
};
};
};
};
&gpio {
groups = "i2c", "uart2", "uart3", "sdhci", "jtag";
function = "gpio";
};
&gmac0 {
nvmem-cells = <&macaddr_factory_e000 0>;
nvmem-cell-names = "mac-address";
};
&pcie {
status = "okay";
};
&pcie0 {
wifi_2_4_ghz: wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x0000>;
// Wi-Fi device reads it's MAC address from EEPROM (&factory + 4)
// adding anything related to mac-address here will cause use random MAC
};
};
&pcie1 {
wifi_5_0_ghz: wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x8000>;
// Wi-Fi device reads it's MAC address from EEPROM, (&factory + 0x8000 + 4)
// adding anything related to mac-address here will cause use random MAC.
};
};
&pcie2 {
status = "disabled";
};
&switch0 {
mediatek,mcm;
ports {
wan: port@0 {
status = "okay";
label = "wan";
nvmem-cells = <&macaddr_factory_e000 1>;
nvmem-cell-names = "mac-address";
};
lan: port@1 {
status = "okay";
label = "lan";
nvmem-cells = <&macaddr_factory_e000 0>;
nvmem-cell-names = "mac-address";
};
};
};

15
target/linux/ramips/image/mt7621.mk
View file

@ -558,6 +558,21 @@ define Device/comfast_cf-e390ax
endef
TARGET_DEVICES += comfast_cf-e390ax
define Device/comfast_cf-ew72-v2
$(Device/dsa-migration)
$(Device/uimage-lzma-loader)
IMAGE_SIZE := 15808k
DEVICE_VENDOR := ComFast
DEVICE_MODEL := CF-EW72 V2
DEVICE_PACKAGES := kmod-mt7603 kmod-mt7615e kmod-mt7663-firmware-ap \
-uboot-envtools
IMAGES += factory.bin
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | \
check-size | append-metadata
IMAGE/factory.bin := append-kernel | append-rootfs | pad-rootfs | check-size
endef
TARGET_DEVICES += comfast_cf-ew72-v2
define Device/cudy_m1800
$(Device/dsa-migration)
DEVICE_VENDOR := Cudy

3
target/linux/ramips/mt7621/base-files/etc/board.d/02_network
View file

@ -152,7 +152,8 @@ ramips_setup_interfaces()
ucidef_set_interface_lan "lan1 lan2 lan3 lan4"
ucidef_set_interface "qtn" ifname "eth1" protocol "static" ipaddr "1.1.1.1" netmask "255.255.255.0"
;;
comfast,cf-e390ax)
comfast,cf-e390ax|\
comfast,cf-ew72-v2)
ucidef_set_interfaces_lan_wan "lan" "wan"
;;
*)

1
target/linux/sifiveu/Makefile
View file

@ -12,6 +12,7 @@ KERNELNAME:=Image dtbs
SUBTARGETS:=generic
KERNEL_PATCHVER:=5.15
KERNEL_TESTING_PATCHVER:=6.1
include $(INCLUDE_DIR)/target.mk

377
target/linux/sifiveu/config-6.1 Normal file
View file

@ -0,0 +1,377 @@
CONFIG_64BIT=y
CONFIG_ARCH_CLOCKSOURCE_INIT=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_RV64I=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_ATA=y
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_CAVIUM_PTP=y
CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y
CONFIG_CLK_SIFIVE=y
CONFIG_CLK_SIFIVE_PRCI=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CLZ_TAB=y
CONFIG_CMODEL_MEDANY=y
# CONFIG_CMODEL_MEDLOW is not set
CONFIG_COMMON_CLK=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
# CONFIG_COMPAT_32BIT_TIME is not set
CONFIG_COMPAT_BRK=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_COREDUMP=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_CPU_ISOLATION=y
CONFIG_CPU_RMAP=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRC7=y
CONFIG_CRC_ITU_T=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DNOTIFY=y
CONFIG_DTC=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_EDAC=y
# CONFIG_EDAC_DEBUG is not set
CONFIG_EDAC_LEGACY_SYSFS=y
CONFIG_EDAC_SIFIVE=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EFI=y
CONFIG_EFIVAR_FS=m
# CONFIG_EFI_BOOTLOADER_CONTROL is not set
# CONFIG_EFI_CAPSULE_LOADER is not set
# CONFIG_EFI_COCO_SECRET is not set
# CONFIG_EFI_DISABLE_PCI_DMA is not set
# CONFIG_EFI_DISABLE_RUNTIME is not set
CONFIG_EFI_EARLYCON=y
CONFIG_EFI_ESRT=y
CONFIG_EFI_GENERIC_STUB=y
CONFIG_EFI_PARAMS_FROM_FDT=y
CONFIG_EFI_RUNTIME_WRAPPERS=y
CONFIG_EFI_STUB=y
# CONFIG_EFI_TEST is not set
# CONFIG_EFI_ZBOOT is not set
CONFIG_ELF_CORE=y
CONFIG_ERRATA_SIFIVE=y
CONFIG_ERRATA_SIFIVE_CIP_1200=y
CONFIG_ERRATA_SIFIVE_CIP_453=y
# CONFIG_ERRATA_THEAD is not set
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_EXT4_FS=y
CONFIG_FAILOVER=y
CONFIG_FAT_FS=y
CONFIG_FHANDLE=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FONT_8x16=y
CONFIG_FONT_AUTOSELECT=y
CONFIG_FONT_SUPPORT=y
CONFIG_FPU=y
CONFIG_FRAME_POINTER=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_INJECTION=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GLOB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_SIFIVE=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HID=y
CONFIG_HID_GENERIC=y
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_CPCI is not set
CONFIG_HOTPLUG_PCI_PCIE=y
CONFIG_HOTPLUG_PCI_SHPC=y
CONFIG_HVC_DRIVER=y
CONFIG_HVC_RISCV_SBI=y
CONFIG_HW_CONSOLE=y
CONFIG_HZ_PERIODIC=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_OCORES=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INPUT=y
# CONFIG_IOMMU_DEBUGFS is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_IO_URING=y
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_KALLSYMS=y
CONFIG_KEYS=y
CONFIG_LEDS_PWM=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_LIBFDT=y
CONFIG_LOCALVERSION_AUTO=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_MACB=y
# CONFIG_MACB_PCI is not set
CONFIG_MACB_USE_HWSTAMP=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MEMFD_CREATE=y
CONFIG_MFD_SYSCON=y
CONFIG_MICROSEMI_PHY=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_CADENCE=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SPI=y
CONFIG_MMIOWB=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MODULE_SECTIONS=y
CONFIG_MPILIB=y
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NET_FAILOVER=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NET_SELFTESTS=y
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_NONPORTABLE is not set
CONFIG_NR_CPUS=8
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_DMA_DEFAULT_COHERENT=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OID_REGISTRY=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xff60000000000000
CONFIG_PAGE_POOL=y
CONFIG_PAGE_REPORTING=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEAER_INJECT=m
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DPC=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_FU740=y
CONFIG_PCIE_PTM=y
CONFIG_PCIE_XILINX=y
CONFIG_PCI_DEBUG=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_ECAM=y
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_SW_SWITCHTEC=y
CONFIG_PGTABLE_LEVELS=5
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_PORTABLE=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_POWER_RESET_RESTART=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_PPS=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_SIFIVE=y
CONFIG_PWM_SYSFS=y
CONFIG_RATIONAL=y
CONFIG_RCU_TRACE=y
CONFIG_RD_GZIP=y
CONFIG_REALTEK_PHY=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
# CONFIG_RESET_ATTACK_MITIGATION is not set
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_SIMPLE=y
CONFIG_RISCV=y
CONFIG_RISCV_ALTERNATIVE=y
# CONFIG_RISCV_BOOT_SPINWAIT is not set
CONFIG_RISCV_DMA_NONCOHERENT=y
CONFIG_RISCV_INTC=y
CONFIG_RISCV_ISA_C=y
CONFIG_RISCV_ISA_SVPBMT=y
CONFIG_RISCV_ISA_ZICBOM=y
CONFIG_RISCV_SBI=y
CONFIG_RISCV_SBI_V01=y
CONFIG_RISCV_TIMER=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_DRV_EFI is not set
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SCHED_DEBUG=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_EXAR=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_SIFIVE=y
CONFIG_SERIAL_SIFIVE_CONSOLE=y
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
CONFIG_SG_POOL=y
CONFIG_SIFIVE_CCACHE=y
CONFIG_SIFIVE_PLIC=y
CONFIG_SLUB_DEBUG=y
CONFIG_SMP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
# CONFIG_SOC_MICROCHIP_POLARFIRE is not set
CONFIG_SOC_SIFIVE=y
# CONFIG_SOC_STARFIVE is not set
# CONFIG_SOC_VIRT is not set
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_SIFIVE=y
CONFIG_SRCU=y
CONFIG_STACKTRACE=y
CONFIG_SWIOTLB=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
# CONFIG_SYSFB_SIMPLEFB is not set
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TOOLCHAIN_HAS_ZICBOM=y
CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y
CONFIG_TRACE_CLOCK=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_TUNE_GENERIC=y
CONFIG_UCS2_STRING=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_HCD_PLATFORM is not set
CONFIG_USB_EHCI_PCI=y
CONFIG_USB_HID=y
CONFIG_USB_NET_DRIVERS=y
CONFIG_USB_PCI=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SUPPORT=y
# CONFIG_USB_UHCI_HCD is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
# CONFIG_USB_XHCI_PLATFORM is not set
CONFIG_VFAT_FS=y
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
CONFIG_VMAP_STACK=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZONE_DMA32=y

49
target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch Normal file
View file

@ -0,0 +1,49 @@
From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
Date: Wed, 17 Feb 2021 06:06:14 -0800
Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to
sifive,u74-mc
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
---
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -39,7 +39,7 @@
};
};
cpu1: cpu@1 {
- compatible = "sifive,bullet0", "riscv";
+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
@@ -63,7 +63,7 @@
};
};
cpu2: cpu@2 {
- compatible = "sifive,bullet0", "riscv";
+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
@@ -87,7 +87,7 @@
};
};
cpu3: cpu@3 {
- compatible = "sifive,bullet0", "riscv";
+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
@@ -111,7 +111,7 @@
};
};
cpu4: cpu@4 {
- compatible = "sifive,bullet0", "riscv";
+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;

26
target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch Normal file
View file

@ -0,0 +1,26 @@
From 14ede57943bc4209755d08daf93ac7be967d7fbe Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
Date: Mon, 13 Sep 2021 02:18:30 -0700
Subject: [PATCH 4/7] riscv: sifive: unmatched: add gpio-poweroff node
Add gpio-poweroff node to allow powering off the system.
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
---
arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
@@ -86,6 +86,11 @@
};
};
};
+
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ };
};
&uart0 {

116
target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch Normal file
View file

@ -0,0 +1,116 @@
From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
Date: Fri, 14 May 2021 05:27:51 -0700
Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq)
Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
---
arch/riscv/Kconfig | 8 +++++
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 ++++
.../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++
3 files changed, 47 insertions(+)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -711,6 +711,14 @@ config PORTABLE
select OF
select MMU
+menu "CPU Power Management"
+
+source "drivers/cpuidle/Kconfig"
+
+source "drivers/cpufreq/Kconfig"
+
+endmenu
+
menu "Power management options"
source "kernel/power/Kconfig"
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -30,6 +30,7 @@
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -54,6 +55,7 @@
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -78,6 +80,7 @@
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -102,6 +105,7 @@
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -126,6 +130,7 @@
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -80,6 +80,40 @@
label = "d4";
};
};
+
+ fu540_c000_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-350000000 {
+ opp-hz = /bits/ 64 <350000000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ };
+ opp-999999999 {
+ opp-hz = /bits/ 64 <999999999>;
+ };
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu1 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu2 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu3 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu4 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
};
&uart0 {

2
target/linux/x86/config-6.1
View file

@ -92,11 +92,13 @@ CONFIG_DEBUG_MISC=y
# CONFIG_DEBUG_TLBFLUSH is not set
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_GZIP=y
# CONFIG_DEVTMPFS_SAFE is not set
CONFIG_DMADEVICES=y
CONFIG_DMI=y
CONFIG_DMIID=y
CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
CONFIG_DMI_SYSFS=y
# CONFIG_DM_AUDIT is not set
CONFIG_DNOTIFY=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_DYNAMIC_SIGFRAME=y