From 9e8bbd4265271612732c0804065ce8bf4939e8c0 Mon Sep 17 00:00:00 2001 From: "Leon M. Busch-George" Date: Fri, 16 Jun 2023 14:53:09 +0200 Subject: [PATCH 01/30] base-files: ipcalc.sh: correctly interpret num parameter The start and end addresses are inclusive. Thus, adding num without substracting one results in num + 1 addresses. Add the substraction and to implement the documented behaviour. Signed-off-by: Leon M. Busch-George --- package/base-files/files/bin/ipcalc.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/base-files/files/bin/ipcalc.sh b/package/base-files/files/bin/ipcalc.sh index 56854b41041..21f84bcaf2e 100755 --- a/package/base-files/files/bin/ipcalc.sh +++ b/package/base-files/files/bin/ipcalc.sh @@ -69,7 +69,7 @@ BEGIN { if (startlimit) end=limit if (end==ipaddr) end=ipaddr-1 From 9b2f8a33b6b247d4232d48a1d18aea3769590083 Mon Sep 17 00:00:00 2001 From: "Leon M. Busch-George" Date: Fri, 16 Jun 2023 14:56:39 +0200 Subject: [PATCH 02/30] base-files: ipcalc.sh: correctly set limit for prefix > 30 For /31 and /32 prefixes, there are only host addresses - no network and broadcast address with all-zero and all-one bits. Reflect this when setting the limit. Signed-off-by: Leon M. Busch-George --- package/base-files/files/bin/ipcalc.sh | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/package/base-files/files/bin/ipcalc.sh b/package/base-files/files/bin/ipcalc.sh index 21f84bcaf2e..c852b5163f4 100755 --- a/package/base-files/files/bin/ipcalc.sh +++ b/package/base-files/files/bin/ipcalc.sh @@ -64,13 +64,21 @@ BEGIN { if (ARGC <= 3) exit(0) + if (prefix<=30) + limit=network+1 + else + limit=network + start=or(network,and(ip2int(ARGV[3]),compl32(netmask))) - limit=network+1 if (startlimit) end=limit if (end==ipaddr) end=ipaddr-1 From 59e681eea1fbf969ff6f2da315f18142b70424bd Mon Sep 17 00:00:00 2001 From: "Leon M. Busch-George" Date: Fri, 16 Jun 2023 14:58:48 +0200 Subject: [PATCH 03/30] base-files: ipcalc.sh: don't print broadcast addr for prefix > 30 Printing a broadcast address doesn't make any sense for /31 and /32 prefixes. Strictly speaking, the same goes for the network address but it is useful to get the first address in the prefix, e.g. to create a canonical CIDR notation "$NETWORK/$PREFIX". Signed-off-by: Leon M. Busch-George --- package/base-files/files/bin/ipcalc.sh | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/package/base-files/files/bin/ipcalc.sh b/package/base-files/files/bin/ipcalc.sh index c852b5163f4..ffcdfc02d8b 100755 --- a/package/base-files/files/bin/ipcalc.sh +++ b/package/base-files/files/bin/ipcalc.sh @@ -50,12 +50,14 @@ BEGIN { network=and(ipaddr,netmask) prefix=32-bitcount(compl32(netmask)) - broadcast=or(network,compl32(netmask)) print "IP="int2ip(ipaddr) print "NETMASK="int2ip(netmask) - print "BROADCAST="int2ip(broadcast) print "NETWORK="int2ip(network) + if (prefix<=30) { + broadcast=or(network,compl32(netmask)) + print "BROADCAST="int2ip(broadcast) + } print "PREFIX="prefix # range calculations: From 6b23836071b171499f3983286a37a8d5c15eeab9 Mon Sep 17 00:00:00 2001 From: "Leon M. Busch-George" Date: Sun, 18 Jun 2023 20:17:27 +0200 Subject: [PATCH 04/30] package: avoid the use of eval to parse ipcalc.sh output Add a function 'ipcalc' to /lib/functions.sh that sets variables more safely using export. With this new function, dnsmasq also handles the return value of ipcalc correctly. Fixes: e4bd3de1be8e ("dnsmasq: refuse to add empty DHCP range") Co-Authored-By: Philip Prindeville Signed-off-by: Leon M. Busch-George --- package/base-files/files/lib/functions.sh | 5 +++++ package/network/config/netifd/Makefile | 2 +- package/network/config/netifd/files/lib/netifd/dhcp.script | 6 +++--- package/network/ipv6/6rd/Makefile | 2 +- package/network/ipv6/6rd/files/6rd.sh | 4 ++-- package/network/services/dnsmasq/Makefile | 2 +- package/network/services/dnsmasq/files/dnsmasq.init | 5 +++-- 7 files changed, 16 insertions(+), 10 deletions(-) diff --git a/package/base-files/files/lib/functions.sh b/package/base-files/files/lib/functions.sh index 4b1b838572a..bbdecbbc475 100644 --- a/package/base-files/files/lib/functions.sh +++ b/package/base-files/files/lib/functions.sh @@ -315,6 +315,11 @@ include() { done } +ipcalc() { + set -- $(ipcalc.sh "$@") + [ $? -eq 0 ] && export -- "$@" +} + find_mtd_index() { local PART="$(grep "\"$1\"" /proc/mtd | awk -F: '{print $1}')" local INDEX="${PART##mtd}" diff --git a/package/network/config/netifd/Makefile b/package/network/config/netifd/Makefile index e60e5920983..811d745a6fc 100644 --- a/package/network/config/netifd/Makefile +++ b/package/network/config/netifd/Makefile @@ -1,7 +1,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=netifd -PKG_RELEASE:=1 +PKG_RELEASE:=2 PKG_SOURCE_PROTO:=git PKG_SOURCE_URL=$(PROJECT_GIT)/project/netifd.git diff --git a/package/network/config/netifd/files/lib/netifd/dhcp.script b/package/network/config/netifd/files/lib/netifd/dhcp.script index 6fcf139beba..db8deac9e67 100755 --- a/package/network/config/netifd/files/lib/netifd/dhcp.script +++ b/package/network/config/netifd/files/lib/netifd/dhcp.script @@ -18,13 +18,13 @@ setup_interface () { proto_add_ipv4_address "$ip" "${subnet:-255.255.255.0}" # TODO: apply $broadcast - local ip_net - eval "$(ipcalc.sh "$ip/$mask")";ip_net="$NETWORK" + local ip_net IP PREFIX NETWORK NETMASK BROADCAST + ipcalc "$ip/$mask" && ip_net="$NETWORK" local i for i in $router; do local gw_net - eval "$(ipcalc.sh "$i/$mask")";gw_net="$NETWORK" + ipcalc "$i/$mask" && gw_net="$NETWORK" [ "$ip_net" != "$gw_net" ] && proto_add_ipv4_route "$i" 32 "" "$ip" proto_add_ipv4_route 0.0.0.0 0 "$i" "$ip" diff --git a/package/network/ipv6/6rd/Makefile b/package/network/ipv6/6rd/Makefile index e2ca4e12003..3ab8198ef31 100644 --- a/package/network/ipv6/6rd/Makefile +++ b/package/network/ipv6/6rd/Makefile @@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=6rd -PKG_RELEASE:=12 +PKG_RELEASE:=13 PKG_LICENSE:=GPL-2.0 include $(INCLUDE_DIR)/package.mk diff --git a/package/network/ipv6/6rd/files/6rd.sh b/package/network/ipv6/6rd/files/6rd.sh index 62a20314d93..dad61118fe6 100644 --- a/package/network/ipv6/6rd/files/6rd.sh +++ b/package/network/ipv6/6rd/files/6rd.sh @@ -40,8 +40,8 @@ proto_6rd_setup() { # Determine the relay prefix. local ip4prefixlen="${ip4prefixlen:-0}" - local ip4prefix - eval "$(ipcalc.sh "$ipaddr/$ip4prefixlen")";ip4prefix=$NETWORK + local ip4prefix IP PREFIX NETWORK NETMASK BROADCAST + ipcalc "$ipaddr/$ip4prefixlen" && ip4prefix="$NETWORK" # Determine our IPv6 address. local ip6subnet=$(6rdcalc "$ip6prefix/$ip6prefixlen" "$ipaddr/$ip4prefixlen") diff --git a/package/network/services/dnsmasq/Makefile b/package/network/services/dnsmasq/Makefile index 4272398a927..54b95d414de 100644 --- a/package/network/services/dnsmasq/Makefile +++ b/package/network/services/dnsmasq/Makefile @@ -10,7 +10,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=dnsmasq PKG_UPSTREAM_VERSION:=2.89 PKG_VERSION:=$(subst test,~~test,$(subst rc,~rc,$(PKG_UPSTREAM_VERSION))) -PKG_RELEASE:=4 +PKG_RELEASE:=5 PKG_SOURCE:=$(PKG_NAME)-$(PKG_UPSTREAM_VERSION).tar.xz PKG_SOURCE_URL:=https://thekelleys.org.uk/dnsmasq/ diff --git a/package/network/services/dnsmasq/files/dnsmasq.init b/package/network/services/dnsmasq/files/dnsmasq.init index 2a3327b0c6f..184e7ff0ed5 100755 --- a/package/network/services/dnsmasq/files/dnsmasq.init +++ b/package/network/services/dnsmasq/files/dnsmasq.init @@ -1,6 +1,8 @@ #!/bin/sh /etc/rc.common # Copyright (C) 2007-2012 OpenWrt.org +. /lib/functions.sh + START=19 USE_PROCD=1 @@ -509,7 +511,6 @@ dhcp_boot_add() { dhcp_option_add "$cfg" "$networkid" "$force" } - dhcp_add() { local cfg="$1" local dhcp6range="::" @@ -587,7 +588,7 @@ dhcp_add() { fi # make sure the DHCP range is not empty - if [ "$dhcpv4" != "disabled" ] && eval "$(ipcalc.sh "${subnet%%/*}" "$netmask" "$start" "$limit")" ; then + if [ "$dhcpv4" != "disabled" ] && ipcalc "${subnet%%/*}" "$netmask" "$start" "$limit" ; then [ "$dynamicdhcpv4" = "0" ] && END="static" xappend "--dhcp-range=$tags$nettag$START,$END,$NETMASK,$leasetime${options:+ $options}" From 9f52a57c99594d70313959d3fc2d36f1529507fe Mon Sep 17 00:00:00 2001 From: "Leon M. Busch-George" Date: Fri, 16 Jun 2023 15:12:18 +0200 Subject: [PATCH 05/30] package: dnsmasq: remove off-by-one mitigation for limit In the dnsmasq init script, an off-by-one in the range calculation of ipcalc.sh was mitigated by passing the limit as if its counting started at zero. This patch removes the mitigation as the off-by-one has been fixed. Signed-off-by: Leon M. Busch-George --- package/network/services/dnsmasq/Makefile | 2 +- package/network/services/dnsmasq/files/dnsmasq.init | 4 ---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/package/network/services/dnsmasq/Makefile b/package/network/services/dnsmasq/Makefile index 54b95d414de..e442d0005b9 100644 --- a/package/network/services/dnsmasq/Makefile +++ b/package/network/services/dnsmasq/Makefile @@ -10,7 +10,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=dnsmasq PKG_UPSTREAM_VERSION:=2.89 PKG_VERSION:=$(subst test,~~test,$(subst rc,~rc,$(PKG_UPSTREAM_VERSION))) -PKG_RELEASE:=5 +PKG_RELEASE:=6 PKG_SOURCE:=$(PKG_NAME)-$(PKG_UPSTREAM_VERSION).tar.xz PKG_SOURCE_URL:=https://thekelleys.org.uk/dnsmasq/ diff --git a/package/network/services/dnsmasq/files/dnsmasq.init b/package/network/services/dnsmasq/files/dnsmasq.init index 184e7ff0ed5..af5ca5822ea 100755 --- a/package/network/services/dnsmasq/files/dnsmasq.init +++ b/package/network/services/dnsmasq/files/dnsmasq.init @@ -583,10 +583,6 @@ dhcp_add() { nettag="${networkid:+set:${networkid},}" - if [ "$limit" -gt 0 ] ; then - limit=$((limit-1)) - fi - # make sure the DHCP range is not empty if [ "$dhcpv4" != "disabled" ] && ipcalc "${subnet%%/*}" "$netmask" "$start" "$limit" ; then [ "$dynamicdhcpv4" = "0" ] && END="static" From d7978e1f39aa91c4c99cab4f13372050afad2438 Mon Sep 17 00:00:00 2001 From: "Leon M. Busch-George" Date: Tue, 27 Jun 2023 16:01:09 +0200 Subject: [PATCH 06/30] base-files: ipcalc.sh clarify range parameters in comment To avoid confusion when working with ipcalc.sh, clarify that the last two parameters belong to the range calculation and rename 'num' to the slightly less ambiguous 'size'. Signed-off-by: Leon M. Busch-George --- package/base-files/files/bin/ipcalc.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/base-files/files/bin/ipcalc.sh b/package/base-files/files/bin/ipcalc.sh index ffcdfc02d8b..0132e8d9bf4 100755 --- a/package/base-files/files/bin/ipcalc.sh +++ b/package/base-files/files/bin/ipcalc.sh @@ -61,7 +61,7 @@ BEGIN { print "PREFIX="prefix # range calculations: - # ipcalc + # ipcalc if (ARGC <= 3) exit(0) From 270f694f1198248109f32cb8867f2673f82072f8 Mon Sep 17 00:00:00 2001 From: "Leon M. Busch-George" Date: Sun, 20 Aug 2023 21:08:20 +0200 Subject: [PATCH 07/30] base-files: ipcalc.sh: turn error into warning Some users have their routers configured to supply a DHCP range that includes the local interface address. That worked with dnsmasq because it automatically skips the local address. Re-enable those existing configurations for the release and hint at possible future problems. Signed-off-by: Leon M. Busch-George [ wrap commit description and remove unecessary text ] Signed-off-by: Christian Marangi --- package/base-files/files/bin/ipcalc.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/package/base-files/files/bin/ipcalc.sh b/package/base-files/files/bin/ipcalc.sh index 0132e8d9bf4..25114219a10 100755 --- a/package/base-files/files/bin/ipcalc.sh +++ b/package/base-files/files/bin/ipcalc.sh @@ -90,8 +90,9 @@ BEGIN { } if (ipaddr > start && ipaddr < end) { - print "ipaddr inside range" > "/dev/stderr" - exit(1) + print "warning: ipaddr inside range - this might not be supported in future releases of Openwrt" > "/dev/stderr" + # turn this into an error after Openwrt 24 has been released + # exit(1) } print "START="int2ip(start) From 25aab738efac8a4e3176012becb7500c8cb09509 Mon Sep 17 00:00:00 2001 From: "Leon M. Busch-George" Date: Wed, 20 Sep 2023 23:42:08 +0200 Subject: [PATCH 08/30] base-files: ipcalc.sh: make check slightly more future-proof The previous code handling the equal-condition might be removed or altered in the future and the case might be overlooked. Signed-off-by: Leon M. Busch-George --- package/base-files/files/bin/ipcalc.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/base-files/files/bin/ipcalc.sh b/package/base-files/files/bin/ipcalc.sh index 25114219a10..827cb5dc2ea 100755 --- a/package/base-files/files/bin/ipcalc.sh +++ b/package/base-files/files/bin/ipcalc.sh @@ -89,7 +89,7 @@ BEGIN { exit(1) } - if (ipaddr > start && ipaddr < end) { + if (ipaddr >= start && ipaddr <= end) { print "warning: ipaddr inside range - this might not be supported in future releases of Openwrt" > "/dev/stderr" # turn this into an error after Openwrt 24 has been released # exit(1) From e26e088203303d79eb87056f8ca74b1a5f585206 Mon Sep 17 00:00:00 2001 From: Oskari Rauta Date: Sun, 24 Sep 2023 08:25:03 +0300 Subject: [PATCH 09/30] kernel: add missing symbols CONFIG_DEVTMPFS_SAFE and CONFIG_DM_AUDIT were not set and had to be manually selected during build everytime kernel was updated. Signed-off-by: Oskari Rauta --- target/linux/x86/config-6.1 | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/linux/x86/config-6.1 b/target/linux/x86/config-6.1 index d9c8546cb14..6776d05be38 100644 --- a/target/linux/x86/config-6.1 +++ b/target/linux/x86/config-6.1 @@ -92,11 +92,13 @@ CONFIG_DEBUG_MISC=y # CONFIG_DEBUG_TLBFLUSH is not set CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_GZIP=y +# CONFIG_DEVTMPFS_SAFE is not set CONFIG_DMADEVICES=y CONFIG_DMI=y CONFIG_DMIID=y CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y CONFIG_DMI_SYSFS=y +# CONFIG_DM_AUDIT is not set CONFIG_DNOTIFY=y CONFIG_DUMMY_CONSOLE=y CONFIG_DYNAMIC_SIGFRAME=y From f1bb528ae7631c60b95499b7e8a1948c3e6a42f0 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Mon, 25 Sep 2023 15:36:29 +0200 Subject: [PATCH 10/30] hostapd: fix rare crash with AP+STA and ACS enabled Ensure that the iface disable in uc_hostapd_iface_start also clears the ACS state. Signed-off-by: Felix Fietkau --- .../services/hostapd/src/src/ap/ucode.c | 27 ++++++++++--------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/package/network/services/hostapd/src/src/ap/ucode.c b/package/network/services/hostapd/src/src/ap/ucode.c index ac3222b03f8..af97091be55 100644 --- a/package/network/services/hostapd/src/src/ap/ucode.c +++ b/package/network/services/hostapd/src/src/ap/ucode.c @@ -465,17 +465,10 @@ uc_hostapd_bss_ctrl(uc_vm_t *vm, size_t nargs) return ucv_string_new_length(reply, reply_len); } -static uc_value_t * -uc_hostapd_iface_stop(uc_vm_t *vm, size_t nargs) +static void +uc_hostapd_disable_iface(struct hostapd_iface *iface) { - struct hostapd_iface *iface = uc_fn_thisval("hostapd.iface"); - int i; - - if (!iface) - return NULL; - switch (iface->state) { - case HAPD_IFACE_ENABLED: case HAPD_IFACE_DISABLED: break; #ifdef CONFIG_ACS @@ -488,9 +481,19 @@ uc_hostapd_iface_stop(uc_vm_t *vm, size_t nargs) hostapd_disable_iface(iface); break; } +} + +static uc_value_t * +uc_hostapd_iface_stop(uc_vm_t *vm, size_t nargs) +{ + struct hostapd_iface *iface = uc_fn_thisval("hostapd.iface"); + int i; + + if (!iface) + return NULL; if (iface->state != HAPD_IFACE_ENABLED) - hostapd_disable_iface(iface); + uc_hostapd_disable_iface(iface); for (i = 0; i < iface->num_bss; i++) { struct hostapd_data *hapd = iface->bss[i]; @@ -561,8 +564,6 @@ uc_hostapd_iface_start(uc_vm_t *vm, size_t nargs) out: switch (iface->state) { - case HAPD_IFACE_DISABLED: - break; case HAPD_IFACE_ENABLED: if (!hostapd_is_dfs_required(iface) || hostapd_is_dfs_chan_available(iface)) @@ -570,7 +571,7 @@ out: wpa_printf(MSG_INFO, "DFS CAC required on new channel, restart interface"); /* fallthrough */ default: - hostapd_disable_iface(iface); + uc_hostapd_disable_iface(iface); break; } From e89373bc2308630f09f911b445fae330a627dd1d Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 25 Sep 2023 18:04:51 +0200 Subject: [PATCH 11/30] generic: 6.1: add missing config TRUSTED_KEYS_TEE Add missing config TRUSTED_KEYS_TEE for kernel 6.1 triggered when TRUSTED_KEYS is enabled. Signed-off-by: Christian Marangi --- target/linux/generic/config-6.1 | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/generic/config-6.1 b/target/linux/generic/config-6.1 index be0e56f869d..5796cbb67c8 100644 --- a/target/linux/generic/config-6.1 +++ b/target/linux/generic/config-6.1 @@ -6989,6 +6989,7 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_TRUSTED_FOUNDATIONS is not set # CONFIG_TRUSTED_KEYS is not set # CONFIG_TRUSTED_KEYS_TPM is not set +# CONFIG_TRUSTED_KEYS_TEE is not set # CONFIG_TSL2583 is not set # CONFIG_TSL2591 is not set # CONFIG_TSL2772 is not set From d686f2153ca2fd30ff9ad1e022e084b4e891106f Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 25 Sep 2023 17:37:38 +0200 Subject: [PATCH 12/30] ipq40xx: move to kernel 6.1 by default Move ipq40xx to kernel 6.1 by default. Signed-off-by: Christian Marangi --- target/linux/ipq40xx/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/linux/ipq40xx/Makefile b/target/linux/ipq40xx/Makefile index 9af7b7d256a..b494e66e5d4 100644 --- a/target/linux/ipq40xx/Makefile +++ b/target/linux/ipq40xx/Makefile @@ -8,8 +8,7 @@ CPU_TYPE:=cortex-a7 CPU_SUBTYPE:=neon-vfpv4 SUBTARGETS:=generic chromium mikrotik -KERNEL_PATCHVER:=5.15 -KERNEL_TESTING_PATCHVER:=6.1 +KERNEL_PATCHVER:=6.1 KERNELNAME:=zImage Image dtbs From ab015abd4a03b8e9ef83d1b01cc2038d9ced9dec Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 25 Sep 2023 17:38:00 +0200 Subject: [PATCH 13/30] ipq40xx: drop patches/files/config for kernel 5.15 Drop patches/files/config for kernel 5.15 now that they are not used anymore. Signed-off-by: Christian Marangi --- target/linux/ipq40xx/config-5.15 | 509 ----- .../drivers/net/dsa/qca/qca8k-ipq4019.c | 1687 ----------------- .../drivers/net/dsa/qca/qca8k-ipq4019.h | 293 --- .../net/ethernet/qualcomm/ipqess/Makefile | 8 - .../net/ethernet/qualcomm/ipqess/ipqess.c | 1336 ------------- .../net/ethernet/qualcomm/ipqess/ipqess.h | 530 ------ .../ethernet/qualcomm/ipqess/ipqess_ethtool.c | 175 -- ...k-qcom-ipq4019-add-missing-networkin.patch | 27 - ...pq4019-add-missing-networking-resets.patch | 28 - .../104-clk-fix-apss-cpu-overclocking.patch | 115 -- ...-compressed-add-appended-DTB-section.patch | 48 - ...d-set-ipq40xx-watchdog-to-allow-boot.patch | 66 - ...msm-use-sdhci_set_clock-instead-of-s.patch | 24 - ...m-comment-unused-sdhci_msm_set_clock.patch | 108 -- ...are-qcom-scm-Add-SDI-disable-support.patch | 60 - ...-qcom-scm-disable-SDI-on-Google-WiFi.patch | 34 - ...e-qcom-scm-fix-SCM-cold-boot-address.patch | 138 -- ...-add-support-for-Toshiba-TC58NVG0S3H.patch | 29 - ...pecific-data-to-struct-skb_shared_in.patch | 43 - ...019-add-shinfo-based-tagging-driver-.patch | 187 -- ...ethernet-qualcomm-add-IPQESS-support.patch | 43 - ...4019-add-ethernet-controller-DT-node.patch | 81 - ...phy-define-PSGMII-PHY-interface-mode.patch | 69 - ...comm-IPQ4019-built-in-switch-support.patch | 57 - .../706-arm-dts-ipq4019-add-switch-node.patch | 98 - .../707-dt-bindings-net-add-QCA807x-PHY.patch | 61 - ...8-net-phy-Add-Qualcom-QCA807x-driver.patch | 50 - ...9-arm-dts-ipq4019-QCA807x-properties.patch | 61 - .../850-soc-add-qualcomm-syscon.patch | 180 -- ...qcom_scm-Clear-download-bit-during-r.patch | 27 - .../patches-5.15/998-lantiq-atm-hacks.patch | 43 - .../999-atm-mpoa-intel-dsl-phy-support.patch | 137 -- 32 files changed, 6352 deletions(-) delete mode 100644 target/linux/ipq40xx/config-5.15 delete mode 100644 target/linux/ipq40xx/files-5.15/drivers/net/dsa/qca/qca8k-ipq4019.c delete mode 100644 target/linux/ipq40xx/files-5.15/drivers/net/dsa/qca/qca8k-ipq4019.h delete mode 100644 target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/Makefile delete mode 100644 target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess.c delete mode 100644 target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess.h delete mode 100644 target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess_ethtool.c delete mode 100644 target/linux/ipq40xx/patches-5.15/100-dt-bindings-clock-qcom-ipq4019-add-missing-networkin.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/101-clk-qcom-gcc-ipq4019-add-missing-networking-resets.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/104-clk-fix-apss-cpu-overclocking.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/301-arm-compressed-add-appended-DTB-section.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/401-mmc-sdhci-msm-comment-unused-sdhci_msm_set_clock.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/420-firmware-qcom-scm-Add-SDI-disable-support.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/421-firmware-qcom-scm-disable-SDI-on-Google-WiFi.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/422-firmware-qcom-scm-fix-SCM-cold-boot-address.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/444-mtd-nand-rawnand-add-support-for-Toshiba-TC58NVG0S3H.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/700-skbuff-add-DSA-specific-data-to-struct-skb_shared_in.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/701-net-dsa-tag_ipq4019-add-shinfo-based-tagging-driver-.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/702-net-ethernet-qualcomm-add-IPQESS-support.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/703-arm-dts-ipq4019-add-ethernet-controller-DT-node.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/705-net-dsa-add-Qualcomm-IPQ4019-built-in-switch-support.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/706-arm-dts-ipq4019-add-switch-node.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/707-dt-bindings-net-add-QCA807x-PHY.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/708-net-phy-Add-Qualcom-QCA807x-driver.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/709-arm-dts-ipq4019-QCA807x-properties.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/910-Revert-firmware-qcom_scm-Clear-download-bit-during-r.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/998-lantiq-atm-hacks.patch delete mode 100644 target/linux/ipq40xx/patches-5.15/999-atm-mpoa-intel-dsl-phy-support.patch diff --git a/target/linux/ipq40xx/config-5.15 b/target/linux/ipq40xx/config-5.15 deleted file mode 100644 index f1fc501010d..00000000000 --- a/target/linux/ipq40xx/config-5.15 +++ /dev/null @@ -1,509 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_APQ_GCC_8084 is not set -# CONFIG_APQ_MMCC_8084 is not set -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_IPQ40XX=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -# CONFIG_ARCH_MDM9615 is not set -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -# CONFIG_ARCH_MSM8960 is not set -# CONFIG_ARCH_MSM8974 is not set -# CONFIG_ARCH_MSM8X60 is not set -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -# CONFIG_ARM_ATAG_DTB_COMPAT is not set -CONFIG_ARM_CPUIDLE=y -# CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_ARM_CRYPTO=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_QCOM_CPUFREQ_HW is not set -# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set -# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_AT803X_PHY=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BCH=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_CLKSRC_QCOM=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE_PARTITION=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_QCOM=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRC8=y -CONFIG_CRYPTO_AES_ARM=y -CONFIG_CRYPTO_AES_ARM_BS=y -CONFIG_CRYPTO_BLAKE2S_ARM=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEV_QCE=y -# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set -# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set -# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set -CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y -CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y -CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512 -CONFIG_CRYPTO_DEV_QCOM_RNG=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_XTS=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MISC=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_DT_IDLE_STATES=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_AT24=y -CONFIG_EXTCON=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_74X164=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_WATCHDOG=y -CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HIGHMEM=y -# CONFIG_HIGHPTE is not set -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_OPTEE=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y -# CONFIG_I2C_QCOM_CCI is not set -CONFIG_I2C_QUP=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -# CONFIG_IPQ_APSS_PLL is not set -CONFIG_IPQ_GCC_4019=y -# CONFIG_IPQ_GCC_6018 is not set -# CONFIG_IPQ_GCC_806X is not set -# CONFIG_IPQ_GCC_8074 is not set -# CONFIG_IPQ_LCC_806X is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_KMAP_LOCAL=y -CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y -# CONFIG_KPSS_XCC is not set -# CONFIG_KRAITCC is not set -CONFIG_LEDS_LP5523=y -CONFIG_LEDS_LP5562=y -CONFIG_LEDS_LP55XX_COMMON=y -CONFIG_LEDS_TLC591XX=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_GPIO=y -CONFIG_MDIO_IPQ4019=y -# CONFIG_MDM_GCC_9615 is not set -# CONFIG_MDM_LCC_9615 is not set -CONFIG_MEMFD_CREATE=y -# CONFIG_MFD_HI6421_SPMI is not set -# CONFIG_MFD_QCOM_RPM is not set -# CONFIG_MFD_SPMI_PMIC is not set -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -CONFIG_MMC_SDHCI_MSM=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MSM_GCC_8660 is not set -# CONFIG_MSM_GCC_8916 is not set -# CONFIG_MSM_GCC_8939 is not set -# CONFIG_MSM_GCC_8960 is not set -# CONFIG_MSM_GCC_8974 is not set -# CONFIG_MSM_GCC_8994 is not set -# CONFIG_MSM_GCC_8996 is not set -# CONFIG_MSM_GCC_8998 is not set -# CONFIG_MSM_GPUCC_8998 is not set -# CONFIG_MSM_LCC_8960 is not set -# CONFIG_MSM_MMCC_8960 is not set -# CONFIG_MSM_MMCC_8974 is not set -# CONFIG_MSM_MMCC_8996 is not set -# CONFIG_MSM_MMCC_8998 is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_BCH=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_QCOM=y -# CONFIG_MTD_QCOMSMEM_PARTS is not set -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_SPLIT_WRGG_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_QCA8K_IPQ4019=y -CONFIG_NET_DSA_TAG_IPQ4019=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVMEM_QCOM_QFPROM=y -# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set -# CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OPTEE=y -CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1 -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_QCOM=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_QCOM_APQ8064_SATA is not set -CONFIG_PHY_QCOM_IPQ4019_USB=y -# CONFIG_PHY_QCOM_IPQ806X_SATA is not set -# CONFIG_PHY_QCOM_IPQ806X_USB is not set -# CONFIG_PHY_QCOM_PCIE2 is not set -# CONFIG_PHY_QCOM_QMP is not set -# CONFIG_PHY_QCOM_QUSB2 is not set -# CONFIG_PHY_QCOM_USB_HS_28NM is not set -# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set -# CONFIG_PHY_QCOM_USB_SS is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_APQ8064 is not set -# CONFIG_PINCTRL_APQ8084 is not set -CONFIG_PINCTRL_IPQ4019=y -# CONFIG_PINCTRL_IPQ6018 is not set -# CONFIG_PINCTRL_IPQ8064 is not set -# CONFIG_PINCTRL_IPQ8074 is not set -# CONFIG_PINCTRL_MDM9615 is not set -CONFIG_PINCTRL_MSM=y -# CONFIG_PINCTRL_MSM8226 is not set -# CONFIG_PINCTRL_MSM8660 is not set -# CONFIG_PINCTRL_MSM8916 is not set -# CONFIG_PINCTRL_MSM8960 is not set -# CONFIG_PINCTRL_MSM8976 is not set -# CONFIG_PINCTRL_MSM8994 is not set -# CONFIG_PINCTRL_MSM8996 is not set -# CONFIG_PINCTRL_MSM8998 is not set -# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set -# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set -# CONFIG_PINCTRL_QCS404 is not set -# CONFIG_PINCTRL_SC7180 is not set -# CONFIG_PINCTRL_SDM660 is not set -# CONFIG_PINCTRL_SDM845 is not set -# CONFIG_PINCTRL_SM8150 is not set -# CONFIG_PINCTRL_SM8250 is not set -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO_RESTART=y -CONFIG_POWER_RESET_MSM=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PRINTK_TIME=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_QCA807X_PHY=y -CONFIG_QCOM_A53PLL=y -# CONFIG_QCOM_ADM is not set -CONFIG_QCOM_BAM_DMA=y -# CONFIG_QCOM_COMMAND_DB is not set -# CONFIG_QCOM_CPR is not set -# CONFIG_QCOM_EBI2 is not set -# CONFIG_QCOM_GENI_SE is not set -# CONFIG_QCOM_GSBI is not set -# CONFIG_QCOM_HFPLL is not set -# CONFIG_QCOM_IOMMU is not set -CONFIG_QCOM_IPQ4019_ESS_EDMA=y -# CONFIG_QCOM_LLCC is not set -# CONFIG_QCOM_OCMEM is not set -# CONFIG_QCOM_PDC is not set -# CONFIG_QCOM_RMTFS_MEM is not set -# CONFIG_QCOM_RPMH is not set -CONFIG_QCOM_SCM=y -# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set -CONFIG_QCOM_SMEM=y -# CONFIG_QCOM_SMSM is not set -# CONFIG_QCOM_SOCINFO is not set -CONFIG_QCOM_TCSR=y -# CONFIG_QCOM_TSENS is not set -CONFIG_QCOM_WDT=y -# CONFIG_QCS_GCC_404 is not set -# CONFIG_QCS_Q6SSTOP_404 is not set -# CONFIG_QCS_TURING_404 is not set -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -# CONFIG_REGULATOR_QCOM_LABIBB is not set -# CONFIG_REGULATOR_QCOM_SPMI is not set -# CONFIG_REGULATOR_QCOM_USB_VBUS is not set -CONFIG_REGULATOR_VCTRL=y -CONFIG_REGULATOR_VQMMC_IPQ4019=y -CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_QCOM_AOSS is not set -# CONFIG_RESET_QCOM_PDC is not set -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SC_DISPCC_7180 is not set -# CONFIG_SC_GCC_7180 is not set -# CONFIG_SC_GPUCC_7180 is not set -# CONFIG_SC_LPASS_CORECC_7180 is not set -# CONFIG_SC_MSS_7180 is not set -# CONFIG_SC_VIDEOCC_7180 is not set -# CONFIG_SDM_CAMCC_845 is not set -# CONFIG_SDM_DISPCC_845 is not set -# CONFIG_SDM_GCC_660 is not set -# CONFIG_SDM_GCC_845 is not set -# CONFIG_SDM_GPUCC_845 is not set -# CONFIG_SDM_LPASSCC_845 is not set -# CONFIG_SDM_VIDEOCC_845 is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -# CONFIG_SM_GCC_8150 is not set -# CONFIG_SM_GCC_8250 is not set -# CONFIG_SM_GPUCC_8150 is not set -# CONFIG_SM_GPUCC_8250 is not set -# CONFIG_SM_VIDEOCC_8150 is not set -# CONFIG_SM_VIDEOCC_8250 is not set -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_QUP=y -CONFIG_SPMI=y -# CONFIG_SPMI_HISI3670 is not set -CONFIG_SPMI_MSM_PMIC_ARB=y -# CONFIG_SPMI_PMIC_CLKDIV is not set -CONFIG_SRCU=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_TEE=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/ipq40xx/files-5.15/drivers/net/dsa/qca/qca8k-ipq4019.c b/target/linux/ipq40xx/files-5.15/drivers/net/dsa/qca/qca8k-ipq4019.c deleted file mode 100644 index 0526445d653..00000000000 --- a/target/linux/ipq40xx/files-5.15/drivers/net/dsa/qca/qca8k-ipq4019.c +++ /dev/null @@ -1,1687 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2009 Felix Fietkau - * Copyright (C) 2011-2012, 2020-2021 Gabor Juhos - * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2016 John Crispin - * Copyright (c) 2021 Robert Marko - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "qca8k-ipq4019.h" - -#define MIB_DESC(_s, _o, _n) \ - { \ - .size = (_s), \ - .offset = (_o), \ - .name = (_n), \ - } - -static const struct qca8k_mib_desc ar8327_mib[] = { - MIB_DESC(1, 0x00, "RxBroad"), - MIB_DESC(1, 0x04, "RxPause"), - MIB_DESC(1, 0x08, "RxMulti"), - MIB_DESC(1, 0x0c, "RxFcsErr"), - MIB_DESC(1, 0x10, "RxAlignErr"), - MIB_DESC(1, 0x14, "RxRunt"), - MIB_DESC(1, 0x18, "RxFragment"), - MIB_DESC(1, 0x1c, "Rx64Byte"), - MIB_DESC(1, 0x20, "Rx128Byte"), - MIB_DESC(1, 0x24, "Rx256Byte"), - MIB_DESC(1, 0x28, "Rx512Byte"), - MIB_DESC(1, 0x2c, "Rx1024Byte"), - MIB_DESC(1, 0x30, "Rx1518Byte"), - MIB_DESC(1, 0x34, "RxMaxByte"), - MIB_DESC(1, 0x38, "RxTooLong"), - MIB_DESC(2, 0x3c, "RxGoodByte"), - MIB_DESC(2, 0x44, "RxBadByte"), - MIB_DESC(1, 0x4c, "RxOverFlow"), - MIB_DESC(1, 0x50, "Filtered"), - MIB_DESC(1, 0x54, "TxBroad"), - MIB_DESC(1, 0x58, "TxPause"), - MIB_DESC(1, 0x5c, "TxMulti"), - MIB_DESC(1, 0x60, "TxUnderRun"), - MIB_DESC(1, 0x64, "Tx64Byte"), - MIB_DESC(1, 0x68, "Tx128Byte"), - MIB_DESC(1, 0x6c, "Tx256Byte"), - MIB_DESC(1, 0x70, "Tx512Byte"), - MIB_DESC(1, 0x74, "Tx1024Byte"), - MIB_DESC(1, 0x78, "Tx1518Byte"), - MIB_DESC(1, 0x7c, "TxMaxByte"), - MIB_DESC(1, 0x80, "TxOverSize"), - MIB_DESC(2, 0x84, "TxByte"), - MIB_DESC(1, 0x8c, "TxCollision"), - MIB_DESC(1, 0x90, "TxAbortCol"), - MIB_DESC(1, 0x94, "TxMultiCol"), - MIB_DESC(1, 0x98, "TxSingleCol"), - MIB_DESC(1, 0x9c, "TxExcDefer"), - MIB_DESC(1, 0xa0, "TxDefer"), - MIB_DESC(1, 0xa4, "TxLateCol"), - MIB_DESC(1, 0xa8, "RXUnicast"), - MIB_DESC(1, 0xac, "TXunicast"), -}; - -static int -qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val) -{ - return regmap_read(priv->regmap, reg, val); -} - -static int -qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) -{ - return regmap_write(priv->regmap, reg, val); -} - -static int -qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val) -{ - return regmap_update_bits(priv->regmap, reg, mask, write_val); -} - -static int -qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val) -{ - return regmap_set_bits(priv->regmap, reg, val); -} - -static int -qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val) -{ - return regmap_clear_bits(priv->regmap, reg, val); -} - -static const struct regmap_range qca8k_readable_ranges[] = { - regmap_reg_range(0x0000, 0x00e4), /* Global control */ - regmap_reg_range(0x0100, 0x0168), /* EEE control */ - regmap_reg_range(0x0200, 0x0270), /* Parser control */ - regmap_reg_range(0x0400, 0x0454), /* ACL */ - regmap_reg_range(0x0600, 0x0718), /* Lookup */ - regmap_reg_range(0x0800, 0x0b70), /* QM */ - regmap_reg_range(0x0c00, 0x0c80), /* PKT */ - regmap_reg_range(0x0e00, 0x0e98), /* L3 */ - regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */ - regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */ - regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */ - regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */ - regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */ - regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */ - regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */ - -}; - -static const struct regmap_access_table qca8k_readable_table = { - .yes_ranges = qca8k_readable_ranges, - .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges), -}; - -static struct regmap_config qca8k_ipq4019_regmap_config = { - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = 0x16ac, /* end MIB - Port6 range */ - .rd_table = &qca8k_readable_table, -}; - -static struct regmap_config qca8k_ipq4019_psgmii_phy_regmap_config = { - .name = "psgmii-phy", - .reg_bits = 32, - .val_bits = 32, - .reg_stride = 4, - .max_register = 0x7fc, -}; - -static int -qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) -{ - u32 val; - - return regmap_read_poll_timeout(priv->regmap, reg, val, - !(val & mask), - 0, - QCA8K_BUSY_WAIT_TIMEOUT); -} - -static int -qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) -{ - u32 reg[4], val; - int i, ret; - - /* load the ARL table into an array */ - for (i = 0; i < 4; i++) { - ret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val); - if (ret < 0) - return ret; - - reg[i] = val; - } - - /* vid - 83:72 */ - fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M; - /* aging - 67:64 */ - fdb->aging = reg[2] & QCA8K_ATU_STATUS_M; - /* portmask - 54:48 */ - fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M; - /* mac - 47:0 */ - fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff; - fdb->mac[1] = reg[1] & 0xff; - fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff; - fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff; - fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff; - fdb->mac[5] = reg[0] & 0xff; - - return 0; -} - -static void -qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac, - u8 aging) -{ - u32 reg[3] = { 0 }; - int i; - - /* vid - 83:72 */ - reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S; - /* aging - 67:64 */ - reg[2] |= aging & QCA8K_ATU_STATUS_M; - /* portmask - 54:48 */ - reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S; - /* mac - 47:0 */ - reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S; - reg[1] |= mac[1]; - reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S; - reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S; - reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S; - reg[0] |= mac[5]; - - /* load the array into the ARL table */ - for (i = 0; i < 3; i++) - qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]); -} - -static int -qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) -{ - u32 reg; - int ret; - - /* Set the command and FDB index */ - reg = QCA8K_ATU_FUNC_BUSY; - reg |= cmd; - if (port >= 0) { - reg |= QCA8K_ATU_FUNC_PORT_EN; - reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S; - } - - /* Write the function register triggering the table access */ - ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg); - if (ret) - return ret; - - /* wait for completion */ - ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY); - if (ret) - return ret; - - /* Check for table full violation when adding an entry */ - if (cmd == QCA8K_FDB_LOAD) { - ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, ®); - if (ret < 0) - return ret; - if (reg & QCA8K_ATU_FUNC_FULL) - return -1; - } - - return 0; -} - -static int -qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port) -{ - int ret; - - qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging); - ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port); - if (ret < 0) - return ret; - - return qca8k_fdb_read(priv, fdb); -} - -static int -qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, - u16 vid, u8 aging) -{ - int ret; - - mutex_lock(&priv->reg_mutex); - qca8k_fdb_write(priv, vid, port_mask, mac, aging); - ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); - mutex_unlock(&priv->reg_mutex); - - return ret; -} - -static int -qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid) -{ - int ret; - - mutex_lock(&priv->reg_mutex); - qca8k_fdb_write(priv, vid, port_mask, mac, 0); - ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); - mutex_unlock(&priv->reg_mutex); - - return ret; -} - -static void -qca8k_fdb_flush(struct qca8k_priv *priv) -{ - mutex_lock(&priv->reg_mutex); - qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1); - mutex_unlock(&priv->reg_mutex); -} - -static int -qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid) -{ - u32 reg; - int ret; - - /* Set the command and VLAN index */ - reg = QCA8K_VTU_FUNC1_BUSY; - reg |= cmd; - reg |= vid << QCA8K_VTU_FUNC1_VID_S; - - /* Write the function register triggering the table access */ - ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg); - if (ret) - return ret; - - /* wait for completion */ - ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY); - if (ret) - return ret; - - /* Check for table full violation when adding an entry */ - if (cmd == QCA8K_VLAN_LOAD) { - ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, ®); - if (ret < 0) - return ret; - if (reg & QCA8K_VTU_FUNC1_FULL) - return -ENOMEM; - } - - return 0; -} - -static int -qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged) -{ - u32 reg; - int ret; - - /* - We do the right thing with VLAN 0 and treat it as untagged while - preserving the tag on egress. - */ - if (vid == 0) - return 0; - - mutex_lock(&priv->reg_mutex); - ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid); - if (ret < 0) - goto out; - - ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); - if (ret < 0) - goto out; - reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN; - reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port)); - if (untagged) - reg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG << - QCA8K_VTU_FUNC0_EG_MODE_S(port); - else - reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG << - QCA8K_VTU_FUNC0_EG_MODE_S(port); - - ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); - if (ret) - goto out; - ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); - -out: - mutex_unlock(&priv->reg_mutex); - - return ret; -} - -static int -qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid) -{ - u32 reg, mask; - int ret, i; - bool del; - - mutex_lock(&priv->reg_mutex); - ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid); - if (ret < 0) - goto out; - - ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); - if (ret < 0) - goto out; - reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port)); - reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT << - QCA8K_VTU_FUNC0_EG_MODE_S(port); - - /* Check if we're the last member to be removed */ - del = true; - for (i = 0; i < QCA8K_NUM_PORTS; i++) { - mask = QCA8K_VTU_FUNC0_EG_MODE_NOT; - mask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i); - - if ((reg & mask) != mask) { - del = false; - break; - } - } - - if (del) { - ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid); - } else { - ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); - if (ret) - goto out; - ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); - } - -out: - mutex_unlock(&priv->reg_mutex); - - return ret; -} - -static int -qca8k_mib_init(struct qca8k_priv *priv) -{ - int ret; - - mutex_lock(&priv->reg_mutex); - ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY); - if (ret) - goto exit; - - ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); - if (ret) - goto exit; - - ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); - if (ret) - goto exit; - - ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB); - -exit: - mutex_unlock(&priv->reg_mutex); - return ret; -} - -static void -qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable) -{ - u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC; - - /* Port 0 is internally connected to the CPU - * TODO: Probably check for RGMII as well if it doesnt work - * in RGMII mode. - */ - if (port > QCA8K_CPU_PORT) - mask |= QCA8K_PORT_STATUS_LINK_AUTO; - - if (enable) - qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask); - else - qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask); -} - -static int -qca8k_setup_port(struct dsa_switch *ds, int port) -{ - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - int ret; - - /* CPU port gets connected to all user ports of the switch */ - if (dsa_is_cpu_port(ds, port)) { - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT), - QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); - if (ret) - return ret; - - /* Disable CPU ARP Auto-learning by default */ - ret = qca8k_reg_clear(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT), - QCA8K_PORT_LOOKUP_LEARN); - if (ret) - return ret; - } - - /* Individual user ports get connected to CPU port only */ - if (dsa_is_user_port(ds, port)) { - int shift = 16 * (port % 2); - - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_MEMBER, - BIT(QCA8K_CPU_PORT)); - if (ret) - return ret; - - /* Enable ARP Auto-learning by default */ - ret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_LEARN); - if (ret) - return ret; - - /* For port based vlans to work we need to set the - * default egress vid - */ - ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), - 0xfff << shift, - QCA8K_PORT_VID_DEF << shift); - if (ret) - return ret; - - ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), - QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) | - QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF)); - if (ret) - return ret; - } - - return 0; -} - -static int -qca8k_setup(struct dsa_switch *ds) -{ - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - int ret, i; - - /* Make sure that port 0 is the cpu port */ - if (!dsa_is_cpu_port(ds, 0)) { - dev_err(priv->dev, "port 0 is not the CPU port"); - return -EINVAL; - } - - /* Enable CPU Port */ - ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, - QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); - if (ret) { - dev_err(priv->dev, "failed enabling CPU port"); - return ret; - } - - /* Enable MIB counters */ - ret = qca8k_mib_init(priv); - if (ret) - dev_warn(priv->dev, "MIB init failed"); - - /* Enable QCA header mode on the cpu port */ - ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT), - QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | - QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); - if (ret) { - dev_err(priv->dev, "failed enabling QCA header mode"); - return ret; - } - - /* Disable forwarding by default on all ports */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) { - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), - QCA8K_PORT_LOOKUP_MEMBER, 0); - if (ret) - return ret; - } - - /* Disable MAC by default on all ports */ - for (i = 1; i < QCA8K_NUM_PORTS; i++) - qca8k_port_set_status(priv, i, 0); - - /* Forward all unknown frames to CPU port for Linux processing */ - ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, - BIT(QCA8K_CPU_PORT) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | - BIT(QCA8K_CPU_PORT) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | - BIT(QCA8K_CPU_PORT) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | - BIT(QCA8K_CPU_PORT) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); - if (ret) - return ret; - - /* Setup connection between CPU port & user ports */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) { - ret = qca8k_setup_port(ds, i); - if (ret) - return ret; - } - - /* Setup our port MTUs to match power on defaults */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) - /* Set per port MTU to 1500 as the MTU change function - * will add the overhead and if its set to 1518 then it - * will apply the overhead again and we will end up with - * MTU of 1536 instead of 1518 - */ - priv->port_mtu[i] = ETH_DATA_LEN; - ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN); - if (ret) - dev_warn(priv->dev, "failed setting MTU settings"); - - /* Flush the FDB table */ - qca8k_fdb_flush(priv); - - /* We don't have interrupts for link changes, so we need to poll */ - ds->pcs_poll = true; - - /* CPU port HW learning doesnt work correctly, so let DSA handle it */ - ds->assisted_learning_on_cpu_port = true; - - return 0; -} - -static int psgmii_vco_calibrate(struct qca8k_priv *priv) -{ - int val, ret; - - if (!priv->psgmii_ethphy) { - dev_err(priv->dev, "PSGMII eth PHY missing, calibration failed!\n"); - return -ENODEV; - } - - /* Fix PSGMII RX 20bit */ - ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5b); - /* Reset PHY PSGMII */ - ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x1b); - /* Release PHY PSGMII reset */ - ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5b); - - /* Poll for VCO PLL calibration finish - Malibu(QCA8075) */ - ret = phy_read_mmd_poll_timeout(priv->psgmii_ethphy, - MDIO_MMD_PMAPMD, - 0x28, val, - (val & BIT(0)), - 10000, 1000000, - false); - if (ret) { - dev_err(priv->dev, "QCA807x PSGMII VCO calibration PLL not ready\n"); - return ret; - } - mdelay(50); - - /* Freeze PSGMII RX CDR */ - ret = phy_write(priv->psgmii_ethphy, MII_RESV2, 0x2230); - - /* Start PSGMIIPHY VCO PLL calibration */ - ret = regmap_set_bits(priv->psgmii, - PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1, - PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART); - - /* Poll for PSGMIIPHY PLL calibration finish - Dakota(IPQ40xx) */ - ret = regmap_read_poll_timeout(priv->psgmii, - PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2, - val, val & PSGMIIPHY_REG_PLL_VCO_CALIB_READY, - 10000, 1000000); - if (ret) { - dev_err(priv->dev, "IPQ PSGMIIPHY VCO calibration PLL not ready\n"); - return ret; - } - mdelay(50); - - /* Release PSGMII RX CDR */ - ret = phy_write(priv->psgmii_ethphy, MII_RESV2, 0x3230); - /* Release PSGMII RX 20bit */ - ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5f); - mdelay(200); - - return ret; -} - -static void -qca8k_switch_port_loopback_on_off(struct qca8k_priv *priv, int port, int on) -{ - u32 val = QCA8K_PORT_LOOKUP_LOOPBACK; - - if (on == 0) - val = 0; - - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_LOOPBACK, val); -} - -static int -qca8k_wait_for_phy_link_state(struct phy_device *phy, int need_status) -{ - int a; - u16 status; - - for (a = 0; a < 100; a++) { - status = phy_read(phy, MII_QCA8075_SSTATUS); - status &= QCA8075_PHY_SPEC_STATUS_LINK; - status = !!status; - if (status == need_status) - return 0; - mdelay(8); - } - - return -1; -} - -static void -qca8k_phy_loopback_on_off(struct qca8k_priv *priv, struct phy_device *phy, - int sw_port, int on) -{ - if (on) { - phy_write(phy, MII_BMCR, BMCR_ANENABLE | BMCR_RESET); - phy_modify(phy, MII_BMCR, BMCR_PDOWN, BMCR_PDOWN); - qca8k_wait_for_phy_link_state(phy, 0); - qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), 0); - phy_write(phy, MII_BMCR, - BMCR_SPEED1000 | - BMCR_FULLDPLX | - BMCR_LOOPBACK); - qca8k_wait_for_phy_link_state(phy, 1); - qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), - QCA8K_PORT_STATUS_SPEED_1000 | - QCA8K_PORT_STATUS_TXMAC | - QCA8K_PORT_STATUS_RXMAC | - QCA8K_PORT_STATUS_DUPLEX); - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(sw_port), - QCA8K_PORT_LOOKUP_STATE_FORWARD, - QCA8K_PORT_LOOKUP_STATE_FORWARD); - } else { /* off */ - qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), 0); - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(sw_port), - QCA8K_PORT_LOOKUP_STATE_DISABLED, - QCA8K_PORT_LOOKUP_STATE_DISABLED); - phy_write(phy, MII_BMCR, BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_RESET); - /* turn off the power of the phys - so that unused - ports do not raise links */ - phy_modify(phy, MII_BMCR, BMCR_PDOWN, BMCR_PDOWN); - } -} - -static void -qca8k_phy_pkt_gen_prep(struct qca8k_priv *priv, struct phy_device *phy, - int pkts_num, int on) -{ - if (on) { - /* enable CRC checker and packets counters */ - phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, 0); - phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, - QCA8075_MMD7_CNT_FRAME_CHK_EN | QCA8075_MMD7_CNT_SELFCLR); - qca8k_wait_for_phy_link_state(phy, 1); - /* packet number */ - phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_NUMB, pkts_num); - /* pkt size - 1504 bytes + 20 bytes */ - phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_SIZE, 1504); - } else { /* off */ - /* packet number */ - phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_NUMB, 0); - /* disable CRC checker and packet counter */ - phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, 0); - /* disable traffic gen */ - phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL, 0); - } -} - -static void -qca8k_wait_for_phy_pkt_gen_fin(struct qca8k_priv *priv, struct phy_device *phy) -{ - int val; - /* wait for all traffic end: 4096(pkt num)*1524(size)*8ns(125MHz)=49938us */ - phy_read_mmd_poll_timeout(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL, - val, !(val & QCA8075_MMD7_PKT_GEN_INPROGR), - 50000, 1000000, true); -} - -static void -qca8k_start_phy_pkt_gen(struct phy_device *phy) -{ - /* start traffic gen */ - phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL, - QCA8075_MMD7_PKT_GEN_START | QCA8075_MMD7_PKT_GEN_INPROGR); -} - -static int -qca8k_start_all_phys_pkt_gens(struct qca8k_priv *priv) -{ - struct phy_device *phy; - phy = phy_device_create(priv->bus, QCA8075_MDIO_BRDCST_PHY_ADDR, - 0, 0, NULL); - if (!phy) { - dev_err(priv->dev, "unable to create mdio broadcast PHY(0x%x)\n", - QCA8075_MDIO_BRDCST_PHY_ADDR); - return -ENODEV; - } - - qca8k_start_phy_pkt_gen(phy); - - phy_device_free(phy); - return 0; -} - -static int -qca8k_get_phy_pkt_gen_test_result(struct phy_device *phy, int pkts_num) -{ - u32 tx_ok, tx_error; - u32 rx_ok, rx_error; - u32 tx_ok_high16; - u32 rx_ok_high16; - u32 tx_all_ok, rx_all_ok; - - /* check counters */ - tx_ok = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_RECV_CNT_LO); - tx_ok_high16 = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_RECV_CNT_HI); - tx_error = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_ERR_CNT); - rx_ok = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_RECV_CNT_LO); - rx_ok_high16 = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_RECV_CNT_HI); - rx_error = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_ERR_CNT); - tx_all_ok = tx_ok + (tx_ok_high16 << 16); - rx_all_ok = rx_ok + (rx_ok_high16 << 16); - - if (tx_all_ok < pkts_num) - return -1; - if(rx_all_ok < pkts_num) - return -2; - if(tx_error) - return -3; - if(rx_error) - return -4; - return 0; /* test is ok */ -} - -static -void qca8k_phy_broadcast_write_on_off(struct qca8k_priv *priv, - struct phy_device *phy, int on) -{ - u32 val; - - val = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_MDIO_BRDCST_WRITE); - - if (on == 0) - val &= ~QCA8075_MMD7_MDIO_BRDCST_WRITE_EN; - else - val |= QCA8075_MMD7_MDIO_BRDCST_WRITE_EN; - - phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_MDIO_BRDCST_WRITE, val); -} - -static int -qca8k_test_dsa_port_for_errors(struct qca8k_priv *priv, struct phy_device *phy, - int port, int test_phase) -{ - int res = 0; - const int test_pkts_num = QCA8075_PKT_GEN_PKTS_COUNT; - - if (test_phase == 1) { /* start test preps */ - qca8k_phy_loopback_on_off(priv, phy, port, 1); - qca8k_switch_port_loopback_on_off(priv, port, 1); - qca8k_phy_broadcast_write_on_off(priv, phy, 1); - qca8k_phy_pkt_gen_prep(priv, phy, test_pkts_num, 1); - } else if (test_phase == 2) { - /* wait for test results, collect it and cleanup */ - qca8k_wait_for_phy_pkt_gen_fin(priv, phy); - res = qca8k_get_phy_pkt_gen_test_result(phy, test_pkts_num); - qca8k_phy_pkt_gen_prep(priv, phy, test_pkts_num, 0); - qca8k_phy_broadcast_write_on_off(priv, phy, 0); - qca8k_switch_port_loopback_on_off(priv, port, 0); - qca8k_phy_loopback_on_off(priv, phy, port, 0); - } - - return res; -} - -static int -qca8k_do_dsa_sw_ports_self_test(struct qca8k_priv *priv, int parallel_test) -{ - struct device_node *dn = priv->dev->of_node; - struct device_node *ports, *port; - struct device_node *phy_dn; - struct phy_device *phy; - int reg, err = 0, test_phase; - u32 tests_result = 0; - - ports = of_get_child_by_name(dn, "ports"); - if (!ports) { - dev_err(priv->dev, "no ports child node found\n"); - return -EINVAL; - } - - for (test_phase = 1; test_phase <= 2; test_phase++) { - if (parallel_test && test_phase == 2) { - err = qca8k_start_all_phys_pkt_gens(priv); - if (err) - goto error; - } - for_each_available_child_of_node(ports, port) { - err = of_property_read_u32(port, "reg", ®); - if (err) - goto error; - if (reg >= QCA8K_NUM_PORTS) { - err = -EINVAL; - goto error; - } - phy_dn = of_parse_phandle(port, "phy-handle", 0); - if (phy_dn) { - phy = of_phy_find_device(phy_dn); - of_node_put(phy_dn); - if (phy) { - int result; - result = qca8k_test_dsa_port_for_errors(priv, - phy, reg, test_phase); - if (!parallel_test && test_phase == 1) - qca8k_start_phy_pkt_gen(phy); - put_device(&phy->mdio.dev); - if (test_phase == 2) { - tests_result <<= 1; - if (result) - tests_result |= 1; - } - } - } - } - } - -end: - of_node_put(ports); - qca8k_fdb_flush(priv); - return tests_result; -error: - tests_result |= 0xf000; - goto end; -} - -static int -psgmii_vco_calibrate_and_test(struct dsa_switch *ds) -{ - int ret, a, test_result; - struct qca8k_priv *priv = ds->priv; - - for (a = 0; a <= QCA8K_PSGMII_CALB_NUM; a++) { - ret = psgmii_vco_calibrate(priv); - if (ret) - return ret; - /* first we run serial test */ - test_result = qca8k_do_dsa_sw_ports_self_test(priv, 0); - /* and if it is ok then we run the test in parallel */ - if (!test_result) - test_result = qca8k_do_dsa_sw_ports_self_test(priv, 1); - if (!test_result) { - if (a > 0) { - dev_warn(priv->dev, "PSGMII work was stabilized after %d " - "calibration retries !\n", a); - } - return 0; - } else { - schedule(); - if (a > 0 && a % 10 == 0) { - dev_err(priv->dev, "PSGMII work is unstable !!! " - "Let's try to wait a bit ... %d\n", a); - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(msecs_to_jiffies(a * 100)); - } - } - } - - panic("PSGMII work is unstable !!! " - "Repeated recalibration attempts did not help(0x%x) !\n", - test_result); - - return -EFAULT; -} - -static int -ipq4019_psgmii_configure(struct dsa_switch *ds) -{ - struct qca8k_priv *priv = ds->priv; - int ret; - - if (!priv->psgmii_calibrated) { - ret = psgmii_vco_calibrate_and_test(ds); - - ret = regmap_clear_bits(priv->psgmii, PSGMIIPHY_MODE_CONTROL, - PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M); - ret = regmap_write(priv->psgmii, PSGMIIPHY_TX_CONTROL, - PSGMIIPHY_TX_CONTROL_MAGIC_VALUE); - - priv->psgmii_calibrated = true; - - return ret; - } - - return 0; -} - -static void -qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, - const struct phylink_link_state *state) -{ - struct qca8k_priv *priv = ds->priv; - - switch (port) { - case 0: - /* CPU port, no configuration needed */ - return; - case 1: - case 2: - case 3: - if (state->interface == PHY_INTERFACE_MODE_PSGMII) - if (ipq4019_psgmii_configure(ds)) - dev_err(ds->dev, "PSGMII configuration failed!\n"); - return; - case 4: - case 5: - if (state->interface == PHY_INTERFACE_MODE_RGMII || - state->interface == PHY_INTERFACE_MODE_RGMII_ID || - state->interface == PHY_INTERFACE_MODE_RGMII_RXID || - state->interface == PHY_INTERFACE_MODE_RGMII_TXID) { - qca8k_reg_set(priv, QCA8K_REG_RGMII_CTRL, QCA8K_RGMII_CTRL_CLK); - } - - if (state->interface == PHY_INTERFACE_MODE_PSGMII) - if (ipq4019_psgmii_configure(ds)) - dev_err(ds->dev, "PSGMII configuration failed!\n"); - return; - default: - dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port); - return; - } -} - -static void -qca8k_phylink_validate(struct dsa_switch *ds, int port, - unsigned long *supported, - struct phylink_link_state *state) -{ - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; - - switch (port) { - case 0: /* CPU port */ - if (state->interface != PHY_INTERFACE_MODE_INTERNAL) - goto unsupported; - break; - case 1: - case 2: - case 3: - /* Only PSGMII mode is supported */ - if (state->interface != PHY_INTERFACE_MODE_PSGMII) - goto unsupported; - break; - case 4: - case 5: - /* PSGMII and RGMII modes are supported */ - if (state->interface != PHY_INTERFACE_MODE_PSGMII && - state->interface != PHY_INTERFACE_MODE_RGMII && - state->interface != PHY_INTERFACE_MODE_RGMII_ID && - state->interface != PHY_INTERFACE_MODE_RGMII_RXID && - state->interface != PHY_INTERFACE_MODE_RGMII_TXID) - goto unsupported; - break; - default: -unsupported: - dev_warn(ds->dev, "interface '%s' (%d) on port %d is not supported\n", - phy_modes(state->interface), state->interface, port); - linkmode_zero(supported); - return; - } - - if (port == 0) { - phylink_set_port_modes(mask); - - phylink_set(mask, 1000baseT_Full); - - phylink_set(mask, Pause); - phylink_set(mask, Asym_Pause); - - linkmode_and(supported, supported, mask); - linkmode_and(state->advertising, state->advertising, mask); - } else { - /* Simply copy what PHYs tell us */ - linkmode_copy(state->advertising, supported); - } -} - -static int -qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port, - struct phylink_link_state *state) -{ - struct qca8k_priv *priv = ds->priv; - u32 reg; - int ret; - - ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), ®); - if (ret < 0) - return ret; - - state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP); - state->an_complete = state->link; - state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO); - state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL : - DUPLEX_HALF; - - switch (reg & QCA8K_PORT_STATUS_SPEED) { - case QCA8K_PORT_STATUS_SPEED_10: - state->speed = SPEED_10; - break; - case QCA8K_PORT_STATUS_SPEED_100: - state->speed = SPEED_100; - break; - case QCA8K_PORT_STATUS_SPEED_1000: - state->speed = SPEED_1000; - break; - default: - state->speed = SPEED_UNKNOWN; - break; - } - - state->pause = MLO_PAUSE_NONE; - if (reg & QCA8K_PORT_STATUS_RXFLOW) - state->pause |= MLO_PAUSE_RX; - if (reg & QCA8K_PORT_STATUS_TXFLOW) - state->pause |= MLO_PAUSE_TX; - - return 1; -} - -static void -qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode, - phy_interface_t interface) -{ - struct qca8k_priv *priv = ds->priv; - - qca8k_port_set_status(priv, port, 0); -} - -static void -qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode, - phy_interface_t interface, struct phy_device *phydev, - int speed, int duplex, bool tx_pause, bool rx_pause) -{ - struct qca8k_priv *priv = ds->priv; - u32 reg; - - if (phylink_autoneg_inband(mode)) { - reg = QCA8K_PORT_STATUS_LINK_AUTO; - } else { - switch (speed) { - case SPEED_10: - reg = QCA8K_PORT_STATUS_SPEED_10; - break; - case SPEED_100: - reg = QCA8K_PORT_STATUS_SPEED_100; - break; - case SPEED_1000: - reg = QCA8K_PORT_STATUS_SPEED_1000; - break; - default: - reg = QCA8K_PORT_STATUS_LINK_AUTO; - break; - } - - if (duplex == DUPLEX_FULL) - reg |= QCA8K_PORT_STATUS_DUPLEX; - - if (rx_pause || dsa_is_cpu_port(ds, port)) - reg |= QCA8K_PORT_STATUS_RXFLOW; - - if (tx_pause || dsa_is_cpu_port(ds, port)) - reg |= QCA8K_PORT_STATUS_TXFLOW; - } - - reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC; - - qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg); -} - -static void -qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data) -{ - int i; - - if (stringset != ETH_SS_STATS) - return; - - for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) - strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name, - ETH_GSTRING_LEN); -} - -static void -qca8k_get_ethtool_stats(struct dsa_switch *ds, int port, - uint64_t *data) -{ - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - const struct qca8k_mib_desc *mib; - u32 reg, i, val; - u32 hi = 0; - int ret; - - for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) { - mib = &ar8327_mib[i]; - reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset; - - ret = qca8k_read(priv, reg, &val); - if (ret < 0) - continue; - - if (mib->size == 2) { - ret = qca8k_read(priv, reg + 4, &hi); - if (ret < 0) - continue; - } - - data[i] = val; - if (mib->size == 2) - data[i] |= (u64)hi << 32; - } -} - -static int -qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset) -{ - if (sset != ETH_SS_STATS) - return 0; - - return ARRAY_SIZE(ar8327_mib); -} - -static int -qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee) -{ - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port); - u32 reg; - int ret; - - mutex_lock(&priv->reg_mutex); - ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, ®); - if (ret < 0) - goto exit; - - if (eee->eee_enabled) - reg |= lpi_en; - else - reg &= ~lpi_en; - ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); - -exit: - mutex_unlock(&priv->reg_mutex); - return ret; -} - -static int -qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) -{ - /* Nothing to do on the port's MAC */ - return 0; -} - -static void -qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) -{ - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - u32 stp_state; - - switch (state) { - case BR_STATE_DISABLED: - stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED; - break; - case BR_STATE_BLOCKING: - stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING; - break; - case BR_STATE_LISTENING: - stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING; - break; - case BR_STATE_LEARNING: - stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING; - break; - case BR_STATE_FORWARDING: - default: - stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD; - break; - } - - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_STATE_MASK, stp_state); -} - -static int -qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br) -{ - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - int port_mask, cpu_port; - int i, ret; - - cpu_port = dsa_to_port(ds, port)->cpu_dp->index; - port_mask = BIT(cpu_port); - - for (i = 0; i < QCA8K_NUM_PORTS; i++) { - if (dsa_is_cpu_port(ds, i)) - continue; - if (dsa_to_port(ds, i)->bridge_dev != br) - continue; - /* Add this port to the portvlan mask of the other ports - * in the bridge - */ - ret = qca8k_reg_set(priv, - QCA8K_PORT_LOOKUP_CTRL(i), - BIT(port)); - if (ret) - return ret; - if (i != port) - port_mask |= BIT(i); - } - - /* Add all other ports to this ports portvlan mask */ - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_MEMBER, port_mask); - - return ret; -} - -static void -qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br) -{ - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - int cpu_port, i; - - cpu_port = dsa_to_port(ds, port)->cpu_dp->index; - - for (i = 0; i < QCA8K_NUM_PORTS; i++) { - if (dsa_is_cpu_port(ds, i)) - continue; - if (dsa_to_port(ds, i)->bridge_dev != br) - continue; - /* Remove this port to the portvlan mask of the other ports - * in the bridge - */ - qca8k_reg_clear(priv, - QCA8K_PORT_LOOKUP_CTRL(i), - BIT(port)); - } - - /* Set the cpu port to be the only one in the portvlan mask of - * this port - */ - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port)); -} - -void qca8k_port_fast_age(struct dsa_switch *ds, int port) -{ - struct qca8k_priv *priv = ds->priv; - - mutex_lock(&priv->reg_mutex); - qca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port); - mutex_unlock(&priv->reg_mutex); -} - -int qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) -{ - struct qca8k_priv *priv = ds->priv; - unsigned int secs = msecs / 1000; - u32 val; - - /* AGE_TIME reg is set in 7s step */ - val = secs / 7; - - /* Handle case with 0 as val to NOT disable - * learning - */ - if (!val) - val = 1; - - return qca8k_rmw(priv, QCA8K_REG_ATU_CTRL, - QCA8K_ATU_AGE_TIME_MASK, - QCA8K_ATU_AGE_TIME(val)); -} - -static int -qca8k_port_enable(struct dsa_switch *ds, int port, - struct phy_device *phy) -{ - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - - qca8k_port_set_status(priv, port, 1); - priv->port_sts[port].enabled = 1; - - if (dsa_is_user_port(ds, port)) - phy_support_asym_pause(phy); - - return 0; -} - -static void -qca8k_port_disable(struct dsa_switch *ds, int port) -{ - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - - qca8k_port_set_status(priv, port, 0); - priv->port_sts[port].enabled = 0; -} - -static int -qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) -{ - struct qca8k_priv *priv = ds->priv; - int i, mtu = 0; - - priv->port_mtu[port] = new_mtu; - - for (i = 0; i < QCA8K_NUM_PORTS; i++) - if (priv->port_mtu[i] > mtu) - mtu = priv->port_mtu[i]; - - /* Include L2 header / FCS length */ - return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN); -} - -static int -qca8k_port_max_mtu(struct dsa_switch *ds, int port) -{ - return QCA8K_MAX_MTU; -} - -static int -qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr, - u16 port_mask, u16 vid) -{ - /* Set the vid to the port vlan id if no vid is set */ - if (!vid) - vid = QCA8K_PORT_VID_DEF; - - return qca8k_fdb_add(priv, addr, port_mask, vid, - QCA8K_ATU_STATUS_STATIC); -} - -static int -qca8k_port_fdb_add(struct dsa_switch *ds, int port, - const unsigned char *addr, u16 vid) -{ - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - u16 port_mask = BIT(port); - - return qca8k_port_fdb_insert(priv, addr, port_mask, vid); -} - -static int -qca8k_port_fdb_del(struct dsa_switch *ds, int port, - const unsigned char *addr, u16 vid) -{ - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - u16 port_mask = BIT(port); - - if (!vid) - vid = QCA8K_PORT_VID_DEF; - - return qca8k_fdb_del(priv, addr, port_mask, vid); -} - -static int -qca8k_port_fdb_dump(struct dsa_switch *ds, int port, - dsa_fdb_dump_cb_t *cb, void *data) -{ - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - struct qca8k_fdb _fdb = { 0 }; - int cnt = QCA8K_NUM_FDB_RECORDS; - bool is_static; - int ret = 0; - - mutex_lock(&priv->reg_mutex); - while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) { - if (!_fdb.aging) - break; - is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC); - ret = cb(_fdb.mac, _fdb.vid, is_static, data); - if (ret) - break; - } - mutex_unlock(&priv->reg_mutex); - - return 0; -} - -static int -qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, - struct netlink_ext_ack *extack) -{ - struct qca8k_priv *priv = ds->priv; - - if (vlan_filtering) { - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_VLAN_MODE, - QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE); - } else { - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), - QCA8K_PORT_LOOKUP_VLAN_MODE, - QCA8K_PORT_LOOKUP_VLAN_MODE_NONE); - } - - return 0; -} - -static int -qca8k_port_vlan_add(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_vlan *vlan, - struct netlink_ext_ack *extack) -{ - bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; - bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; - struct qca8k_priv *priv = ds->priv; - int ret = 0; - - ret = qca8k_vlan_add(priv, port, vlan->vid, untagged); - if (ret) { - dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret); - return ret; - } - - if (pvid) { - int shift = 16 * (port % 2); - - qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), - 0xfff << shift, vlan->vid << shift); - qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), - QCA8K_PORT_VLAN_CVID(vlan->vid) | - QCA8K_PORT_VLAN_SVID(vlan->vid)); - } - return 0; -} - -static int -qca8k_port_vlan_del(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_vlan *vlan) -{ - struct qca8k_priv *priv = ds->priv; - int ret = 0; - - ret = qca8k_vlan_del(priv, port, vlan->vid); - if (ret) - dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret); - - return ret; -} - -static enum dsa_tag_protocol -qca8k_get_tag_protocol(struct dsa_switch *ds, int port, - enum dsa_tag_protocol mp) -{ - return DSA_TAG_PROTO_IPQ4019; -} - -static const struct dsa_switch_ops qca8k_switch_ops = { - .get_tag_protocol = qca8k_get_tag_protocol, - .setup = qca8k_setup, - .get_strings = qca8k_get_strings, - .get_ethtool_stats = qca8k_get_ethtool_stats, - .get_sset_count = qca8k_get_sset_count, - .set_ageing_time = qca8k_set_ageing_time, - .get_mac_eee = qca8k_get_mac_eee, - .set_mac_eee = qca8k_set_mac_eee, - .port_enable = qca8k_port_enable, - .port_disable = qca8k_port_disable, - .port_change_mtu = qca8k_port_change_mtu, - .port_max_mtu = qca8k_port_max_mtu, - .port_stp_state_set = qca8k_port_stp_state_set, - .port_bridge_join = qca8k_port_bridge_join, - .port_bridge_leave = qca8k_port_bridge_leave, - .port_fast_age = qca8k_port_fast_age, - .port_fdb_add = qca8k_port_fdb_add, - .port_fdb_del = qca8k_port_fdb_del, - .port_fdb_dump = qca8k_port_fdb_dump, - .port_vlan_filtering = qca8k_port_vlan_filtering, - .port_vlan_add = qca8k_port_vlan_add, - .port_vlan_del = qca8k_port_vlan_del, - .phylink_validate = qca8k_phylink_validate, - .phylink_mac_link_state = qca8k_phylink_mac_link_state, - .phylink_mac_config = qca8k_phylink_mac_config, - .phylink_mac_link_down = qca8k_phylink_mac_link_down, - .phylink_mac_link_up = qca8k_phylink_mac_link_up, -}; - -static int -qca8k_ipq4019_probe(struct platform_device *pdev) -{ - struct qca8k_priv *priv; - void __iomem *base, *psgmii; - struct device_node *np = pdev->dev.of_node, *mdio_np, *psgmii_ethphy_np; - int ret; - - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->dev = &pdev->dev; - - base = devm_platform_ioremap_resource_byname(pdev, "base"); - if (IS_ERR(base)) - return PTR_ERR(base); - - priv->regmap = devm_regmap_init_mmio(priv->dev, base, - &qca8k_ipq4019_regmap_config); - if (IS_ERR(priv->regmap)) { - ret = PTR_ERR(priv->regmap); - dev_err(priv->dev, "base regmap initialization failed, %d\n", ret); - return ret; - } - - psgmii = devm_platform_ioremap_resource_byname(pdev, "psgmii_phy"); - if (IS_ERR(psgmii)) - return PTR_ERR(psgmii); - - priv->psgmii = devm_regmap_init_mmio(priv->dev, psgmii, - &qca8k_ipq4019_psgmii_phy_regmap_config); - if (IS_ERR(priv->psgmii)) { - ret = PTR_ERR(priv->psgmii); - dev_err(priv->dev, "PSGMII regmap initialization failed, %d\n", ret); - return ret; - } - - mdio_np = of_parse_phandle(np, "mdio", 0); - if (!mdio_np) { - dev_err(&pdev->dev, "unable to get MDIO bus phandle\n"); - of_node_put(mdio_np); - return -EINVAL; - } - - priv->bus = of_mdio_find_bus(mdio_np); - of_node_put(mdio_np); - if (!priv->bus) { - dev_err(&pdev->dev, "unable to find MDIO bus\n"); - return -EPROBE_DEFER; - } - - psgmii_ethphy_np = of_parse_phandle(np, "psgmii-ethphy", 0); - if (!psgmii_ethphy_np) { - dev_dbg(&pdev->dev, "unable to get PSGMII eth PHY phandle\n"); - of_node_put(psgmii_ethphy_np); - } - - if (psgmii_ethphy_np) { - priv->psgmii_ethphy = of_phy_find_device(psgmii_ethphy_np); - of_node_put(psgmii_ethphy_np); - if (!priv->psgmii_ethphy) { - dev_err(&pdev->dev, "unable to get PSGMII eth PHY\n"); - return -ENODEV; - } - } - - priv->ds = devm_kzalloc(priv->dev, sizeof(*priv->ds), GFP_KERNEL); - if (!priv->ds) - return -ENOMEM; - - priv->ds->dev = priv->dev; - priv->ds->num_ports = QCA8K_NUM_PORTS; - priv->ds->priv = priv; - priv->ops = qca8k_switch_ops; - priv->ds->ops = &priv->ops; - - mutex_init(&priv->reg_mutex); - platform_set_drvdata(pdev, priv); - - return dsa_register_switch(priv->ds); -} - -static int -qca8k_ipq4019_remove(struct platform_device *pdev) -{ - struct qca8k_priv *priv = dev_get_drvdata(&pdev->dev); - int i; - - if (!priv) - return 0; - - for (i = 0; i < QCA8K_NUM_PORTS; i++) - qca8k_port_set_status(priv, i, 0); - - dsa_unregister_switch(priv->ds); - - dev_set_drvdata(&pdev->dev, NULL); - - return 0; -} - -static const struct of_device_id qca8k_ipq4019_of_match[] = { - { .compatible = "qca,ipq4019-qca8337n" }, - { /* sentinel */ }, -}; - -static struct platform_driver qca8k_ipq4019_driver = { - .probe = qca8k_ipq4019_probe, - .remove = qca8k_ipq4019_remove, - .driver = { - .name = "qca8k-ipq4019", - .of_match_table = qca8k_ipq4019_of_match, - }, -}; - -module_platform_driver(qca8k_ipq4019_driver); - -MODULE_AUTHOR("Mathieu Olivari, John Crispin "); -MODULE_AUTHOR("Gabor Juhos , Robert Marko "); -MODULE_DESCRIPTION("Qualcomm IPQ4019 built-in switch driver"); -MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq40xx/files-5.15/drivers/net/dsa/qca/qca8k-ipq4019.h b/target/linux/ipq40xx/files-5.15/drivers/net/dsa/qca/qca8k-ipq4019.h deleted file mode 100644 index 1e1f45a443e..00000000000 --- a/target/linux/ipq40xx/files-5.15/drivers/net/dsa/qca/qca8k-ipq4019.h +++ /dev/null @@ -1,293 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2009 Felix Fietkau - * Copyright (C) 2011-2012 Gabor Juhos - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - */ - -#ifndef __QCA8K_H -#define __QCA8K_H - -#include - -#define QCA8K_NUM_PORTS 6 -#define QCA8K_CPU_PORT 0 -#define QCA8K_MAX_MTU 9000 - -#define QCA8K_BUSY_WAIT_TIMEOUT 2000 - -#define QCA8K_NUM_FDB_RECORDS 2048 - -#define QCA8K_PORT_VID_DEF 1 - -/* Global control registers */ -#define QCA8K_REG_MASK_CTRL 0x000 -#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0) -#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0) -#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) -#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) -#define QCA8K_REG_RGMII_CTRL 0x004 -#define QCA8K_RGMII_CTRL_RGMII_RXC GENMASK(1, 0) -#define QCA8K_RGMII_CTRL_RGMII_TXC GENMASK(9, 8) -/* Some kind of CLK selection - * 0: gcc_ess_dly2ns - * 1: gcc_ess_clk - */ -#define QCA8K_RGMII_CTRL_CLK BIT(10) -#define QCA8K_RGMII_CTRL_DELAY_RMII0 GENMASK(17, 16) -#define QCA8K_RGMII_CTRL_INVERT_RMII0_REF_CLK BIT(18) -#define QCA8K_RGMII_CTRL_DELAY_RMII1 GENMASK(20, 19) -#define QCA8K_RGMII_CTRL_INVERT_RMII1_REF_CLK BIT(21) -#define QCA8K_RGMII_CTRL_INVERT_RMII0_MASTER_EN BIT(24) -#define QCA8K_RGMII_CTRL_INVERT_RMII1_MASTER_EN BIT(25) -#define QCA8K_REG_MODULE_EN 0x030 -#define QCA8K_MODULE_EN_MIB BIT(0) -#define QCA8K_REG_MIB 0x034 -#define QCA8K_MIB_FLUSH BIT(24) -#define QCA8K_MIB_CPU_KEEP BIT(20) -#define QCA8K_MIB_BUSY BIT(17) -#define QCA8K_GOL_MAC_ADDR0 0x60 -#define QCA8K_GOL_MAC_ADDR1 0x64 -#define QCA8K_MAX_FRAME_SIZE 0x78 -#define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) -#define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0) -#define QCA8K_PORT_STATUS_SPEED_10 0 -#define QCA8K_PORT_STATUS_SPEED_100 0x1 -#define QCA8K_PORT_STATUS_SPEED_1000 0x2 -#define QCA8K_PORT_STATUS_TXMAC BIT(2) -#define QCA8K_PORT_STATUS_RXMAC BIT(3) -#define QCA8K_PORT_STATUS_TXFLOW BIT(4) -#define QCA8K_PORT_STATUS_RXFLOW BIT(5) -#define QCA8K_PORT_STATUS_DUPLEX BIT(6) -#define QCA8K_PORT_STATUS_LINK_UP BIT(8) -#define QCA8K_PORT_STATUS_LINK_AUTO BIT(9) -#define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10) -#define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12) -#define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4)) -#define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2) -#define QCA8K_PORT_HDR_CTRL_RX_S 2 -#define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0) -#define QCA8K_PORT_HDR_CTRL_TX_S 0 -#define QCA8K_PORT_HDR_CTRL_ALL 2 -#define QCA8K_PORT_HDR_CTRL_MGMT 1 -#define QCA8K_PORT_HDR_CTRL_NONE 0 -#define QCA8K_REG_SGMII_CTRL 0x0e0 -#define QCA8K_SGMII_EN_PLL BIT(1) -#define QCA8K_SGMII_EN_RX BIT(2) -#define QCA8K_SGMII_EN_TX BIT(3) -#define QCA8K_SGMII_EN_SD BIT(4) -#define QCA8K_SGMII_CLK125M_DELAY BIT(7) -#define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23)) -#define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22) -#define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22) -#define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22) - -/* EEE control registers */ -#define QCA8K_REG_EEE_CTRL 0x100 -#define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2) - -/* ACL registers */ -#define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8)) -#define QCA8K_PORT_VLAN_CVID(x) (x << 16) -#define QCA8K_PORT_VLAN_SVID(x) x -#define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8)) -#define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470 -#define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474 - -/* Lookup registers */ -#define QCA8K_REG_ATU_DATA0 0x600 -#define QCA8K_ATU_ADDR2_S 24 -#define QCA8K_ATU_ADDR3_S 16 -#define QCA8K_ATU_ADDR4_S 8 -#define QCA8K_REG_ATU_DATA1 0x604 -#define QCA8K_ATU_PORT_M 0x7f -#define QCA8K_ATU_PORT_S 16 -#define QCA8K_ATU_ADDR0_S 8 -#define QCA8K_REG_ATU_DATA2 0x608 -#define QCA8K_ATU_VID_M 0xfff -#define QCA8K_ATU_VID_S 8 -#define QCA8K_ATU_STATUS_M 0xf -#define QCA8K_ATU_STATUS_STATIC 0xf -#define QCA8K_REG_ATU_FUNC 0x60c -#define QCA8K_ATU_FUNC_BUSY BIT(31) -#define QCA8K_ATU_FUNC_PORT_EN BIT(14) -#define QCA8K_ATU_FUNC_MULTI_EN BIT(13) -#define QCA8K_ATU_FUNC_FULL BIT(12) -#define QCA8K_ATU_FUNC_PORT_M 0xf -#define QCA8K_ATU_FUNC_PORT_S 8 -#define QCA8K_REG_VTU_FUNC0 0x610 -#define QCA8K_VTU_FUNC0_VALID BIT(20) -#define QCA8K_VTU_FUNC0_IVL_EN BIT(19) -#define QCA8K_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) -#define QCA8K_VTU_FUNC0_EG_MODE_MASK 3 -#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0 -#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG 1 -#define QCA8K_VTU_FUNC0_EG_MODE_TAG 2 -#define QCA8K_VTU_FUNC0_EG_MODE_NOT 3 -#define QCA8K_REG_VTU_FUNC1 0x614 -#define QCA8K_VTU_FUNC1_BUSY BIT(31) -#define QCA8K_VTU_FUNC1_VID_S 16 -#define QCA8K_VTU_FUNC1_FULL BIT(4) -#define QCA8K_REG_ATU_CTRL 0x618 -#define QCA8K_ATU_AGE_TIME_MASK GENMASK(15, 0) -#define QCA8K_ATU_AGE_TIME(x) FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x)) -#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620 -#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10) -#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624 -#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24 -#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16 -#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8 -#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0 -#define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc) -#define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0) -#define QCA8K_PORT_LOOKUP_VLAN_MODE GENMASK(9, 8) -#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8) -#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK (1 << 8) -#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK (2 << 8) -#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE (3 << 8) -#define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16) -#define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16) -#define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16) -#define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16) -#define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16) -#define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16) -#define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) -#define QCA8K_PORT_LOOKUP_LEARN BIT(20) -#define QCA8K_PORT_LOOKUP_LOOPBACK BIT(21) - -#define QCA8K_REG_GLOBAL_FC_THRESH 0x800 -#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16) -#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16) -#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0) -#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0) - -#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) -#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0) -#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0) -#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4) -#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4) -#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8) -#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8) -#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12) -#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12) -#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16) -#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16) -#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20) -#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20) -#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24) -#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24) - -#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) -#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0) -#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0) -#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6) -#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7) -#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8) -#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) - -/* Pkt edit registers */ -#define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2))) - -/* L3 registers */ -#define QCA8K_HROUTER_CONTROL 0xe00 -#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16) -#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S 16 -#define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE 1 -#define QCA8K_HROUTER_PBASED_CONTROL1 0xe08 -#define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c -#define QCA8K_HNAT_CONTROL 0xe38 - -/* MIB registers */ -#define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100) - -/* IPQ4019 PSGMII PHY registers */ -#define PSGMIIPHY_MODE_CONTROL 0x1b4 -#define PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M BIT(0) -#define PSGMIIPHY_TX_CONTROL 0x288 -#define PSGMIIPHY_TX_CONTROL_MAGIC_VALUE 0x8380 -#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1 0x9c -#define PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART BIT(14) -#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2 0xa0 -#define PSGMIIPHY_REG_PLL_VCO_CALIB_READY BIT(0) - -#define QCA8K_PSGMII_CALB_NUM 100 -#define MII_QCA8075_SSTATUS 0x11 -#define QCA8075_PHY_SPEC_STATUS_LINK BIT(10) -#define QCA8075_MMD7_CRC_AND_PKTS_COUNT 0x8029 -#define QCA8075_MMD7_PKT_GEN_PKT_NUMB 0x8021 -#define QCA8075_MMD7_PKT_GEN_PKT_SIZE 0x8062 -#define QCA8075_MMD7_PKT_GEN_CTRL 0x8020 -#define QCA8075_MMD7_CNT_SELFCLR BIT(1) -#define QCA8075_MMD7_CNT_FRAME_CHK_EN BIT(0) -#define QCA8075_MMD7_PKT_GEN_START BIT(13) -#define QCA8075_MMD7_PKT_GEN_INPROGR BIT(15) -#define QCA8075_MMD7_IG_FRAME_RECV_CNT_HI 0x802a -#define QCA8075_MMD7_IG_FRAME_RECV_CNT_LO 0x802b -#define QCA8075_MMD7_IG_FRAME_ERR_CNT 0x802c -#define QCA8075_MMD7_EG_FRAME_RECV_CNT_HI 0x802d -#define QCA8075_MMD7_EG_FRAME_RECV_CNT_LO 0x802e -#define QCA8075_MMD7_EG_FRAME_ERR_CNT 0x802f -#define QCA8075_MMD7_MDIO_BRDCST_WRITE 0x8028 -#define QCA8075_MMD7_MDIO_BRDCST_WRITE_EN BIT(15) -#define QCA8075_MDIO_BRDCST_PHY_ADDR 0x1f -#define QCA8075_PKT_GEN_PKTS_COUNT 4096 - -enum { - QCA8K_PORT_SPEED_10M = 0, - QCA8K_PORT_SPEED_100M = 1, - QCA8K_PORT_SPEED_1000M = 2, - QCA8K_PORT_SPEED_ERR = 3, -}; - -enum qca8k_fdb_cmd { - QCA8K_FDB_FLUSH = 1, - QCA8K_FDB_LOAD = 2, - QCA8K_FDB_PURGE = 3, - QCA8K_FDB_FLUSH_PORT = 5, - QCA8K_FDB_NEXT = 6, - QCA8K_FDB_SEARCH = 7, -}; - -enum qca8k_vlan_cmd { - QCA8K_VLAN_FLUSH = 1, - QCA8K_VLAN_LOAD = 2, - QCA8K_VLAN_PURGE = 3, - QCA8K_VLAN_REMOVE_PORT = 4, - QCA8K_VLAN_NEXT = 5, - QCA8K_VLAN_READ = 6, -}; - -struct ar8xxx_port_status { - int enabled; -}; - -struct qca8k_priv { - struct regmap *regmap; - struct mii_bus *bus; - struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; - struct dsa_switch *ds; - struct mutex reg_mutex; - struct device *dev; - struct dsa_switch_ops ops; - unsigned int port_mtu[QCA8K_NUM_PORTS]; - - /* IPQ4019 specific */ - struct regmap *psgmii; - bool psgmii_calibrated; - struct phy_device *psgmii_ethphy; -}; - -struct qca8k_mib_desc { - unsigned int size; - unsigned int offset; - const char *name; -}; - -struct qca8k_fdb { - u16 vid; - u8 port_mask; - u8 aging; - u8 mac[6]; -}; - -#endif /* __QCA8K_H */ diff --git a/target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/Makefile b/target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/Makefile deleted file mode 100644 index 4f2db7283eb..00000000000 --- a/target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for the IPQ ESS driver -# - -obj-$(CONFIG_QCOM_IPQ4019_ESS_EDMA) += ipq_ess.o - -ipq_ess-objs := ipqess.o ipqess_ethtool.o diff --git a/target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess.c b/target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess.c deleted file mode 100644 index ee33bb01667..00000000000 --- a/target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess.c +++ /dev/null @@ -1,1336 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR ISC) -/* Copyright (c) 2014 - 2017, The Linux Foundation. All rights reserved. - * Copyright (c) 2017 - 2018, John Crispin - * Copyright (c) 2018 - 2019, Christian Lamparter - * Copyright (c) 2020 - 2021, Gabor Juhos - * - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ipqess.h" - -#define IPQESS_RRD_SIZE 16 -#define IPQESS_NEXT_IDX(X, Y) (((X) + 1) & ((Y) - 1)) -#define IPQESS_TX_DMA_BUF_LEN 0x3fff - -static void ipqess_w32(struct ipqess *ess, u32 reg, u32 val) -{ - writel(val, ess->hw_addr + reg); -} - -static u32 ipqess_r32(struct ipqess *ess, u16 reg) -{ - return readl(ess->hw_addr + reg); -} - -static void ipqess_m32(struct ipqess *ess, u32 mask, u32 val, u16 reg) -{ - u32 _val = ipqess_r32(ess, reg); - _val &= ~mask; - _val |= val; - ipqess_w32(ess, reg, _val); -} - -void ipqess_update_hw_stats(struct ipqess *ess) -{ - uint32_t *p; - u32 stat; - int i; - - lockdep_assert_held(&ess->stats_lock); - - p = (uint32_t *)&(ess->ipqessstats); - for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++) { - stat = ipqess_r32(ess, IPQESS_REG_TX_STAT_PKT_Q(i)); - *p += stat; - p++; - } - - for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++) { - stat = ipqess_r32(ess, IPQESS_REG_TX_STAT_BYTE_Q(i)); - *p += stat; - p++; - } - - for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++) { - stat = ipqess_r32(ess, IPQESS_REG_RX_STAT_PKT_Q(i)); - *p += stat; - p++; - } - - for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++) { - stat = ipqess_r32(ess, IPQESS_REG_RX_STAT_BYTE_Q(i)); - *p += stat; - p++; - } -} - -static int ipqess_tx_ring_alloc(struct ipqess *ess) -{ - struct device *dev = &ess->pdev->dev; - int i; - - for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) { - struct ipqess_tx_ring *tx_ring = &ess->tx_ring[i]; - size_t size; - u32 idx; - - tx_ring->ess = ess; - tx_ring->ring_id = i; - tx_ring->idx = i * 4; - tx_ring->count = IPQESS_TX_RING_SIZE; - tx_ring->nq = netdev_get_tx_queue(ess->netdev, i); - - size = sizeof(struct ipqess_buf) * IPQESS_TX_RING_SIZE; - tx_ring->buf = devm_kzalloc(dev, size, GFP_KERNEL); - if (!tx_ring->buf) { - netdev_err(ess->netdev, "buffer alloc of tx ring failed"); - return -ENOMEM; - } - - size = sizeof(struct ipqess_tx_desc) * IPQESS_TX_RING_SIZE; - tx_ring->hw_desc = dmam_alloc_coherent(dev, size, &tx_ring->dma, - GFP_KERNEL | __GFP_ZERO); - if (!tx_ring->hw_desc) { - netdev_err(ess->netdev, "descriptor allocation for tx ring failed"); - return -ENOMEM; - } - - ipqess_w32(ess, IPQESS_REG_TPD_BASE_ADDR_Q(tx_ring->idx), - (u32)tx_ring->dma); - - idx = ipqess_r32(ess, IPQESS_REG_TPD_IDX_Q(tx_ring->idx)); - idx >>= IPQESS_TPD_CONS_IDX_SHIFT; /* need u32 here */ - idx &= 0xffff; - tx_ring->head = tx_ring->tail = idx; - - ipqess_m32(ess, IPQESS_TPD_PROD_IDX_MASK << IPQESS_TPD_PROD_IDX_SHIFT, - idx, IPQESS_REG_TPD_IDX_Q(tx_ring->idx)); - ipqess_w32(ess, IPQESS_REG_TX_SW_CONS_IDX_Q(tx_ring->idx), idx); - ipqess_w32(ess, IPQESS_REG_TPD_RING_SIZE, IPQESS_TX_RING_SIZE); - } - - return 0; -} - -static int ipqess_tx_unmap_and_free(struct device *dev, struct ipqess_buf *buf) -{ - int len = 0; - - if (buf->flags & IPQESS_DESC_SINGLE) - dma_unmap_single(dev, buf->dma, buf->length, DMA_TO_DEVICE); - else if (buf->flags & IPQESS_DESC_PAGE) - dma_unmap_page(dev, buf->dma, buf->length, DMA_TO_DEVICE); - - if (buf->flags & IPQESS_DESC_LAST) { - len = buf->skb->len; - dev_kfree_skb_any(buf->skb); - } - - buf->flags = 0; - - return len; -} - -static void ipqess_tx_ring_free(struct ipqess *ess) -{ - int i; - - for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) { - int j; - - if (ess->tx_ring[i].hw_desc) - continue; - - for (j = 0; j < IPQESS_TX_RING_SIZE; j++) { - struct ipqess_buf *buf = &ess->tx_ring[i].buf[j]; - - ipqess_tx_unmap_and_free(&ess->pdev->dev, buf); - } - - ess->tx_ring[i].buf = NULL; - } -} - -static int ipqess_rx_buf_prepare(struct ipqess_buf *buf, - struct ipqess_rx_ring *rx_ring) -{ - /* Clean the HW DESC header, otherwise we might end up - * with a spurious desc because of random garbage */ - memset(buf->skb->data, 0, sizeof(struct ipqess_rx_desc)); - - buf->dma = dma_map_single(rx_ring->ppdev, buf->skb->data, - IPQESS_RX_HEAD_BUFF_SIZE, DMA_FROM_DEVICE); - if (dma_mapping_error(rx_ring->ppdev, buf->dma)) { - dev_err_once(rx_ring->ppdev, - "IPQESS DMA mapping failed for linear address %x", - buf->dma); - dev_kfree_skb_any(buf->skb); - buf->skb = NULL; - return -EFAULT; - } - - buf->length = IPQESS_RX_HEAD_BUFF_SIZE; - rx_ring->hw_desc[rx_ring->head] = (struct ipqess_rx_desc *)buf->dma; - rx_ring->head = (rx_ring->head + 1) % IPQESS_RX_RING_SIZE; - - ipqess_m32(rx_ring->ess, IPQESS_RFD_PROD_IDX_BITS, - (rx_ring->head + IPQESS_RX_RING_SIZE - 1) % IPQESS_RX_RING_SIZE, - IPQESS_REG_RFD_IDX_Q(rx_ring->idx)); - - return 0; -} - -/* locking is handled by the caller */ -static int ipqess_rx_buf_alloc_napi(struct ipqess_rx_ring *rx_ring) -{ - struct ipqess_buf *buf = &rx_ring->buf[rx_ring->head]; - - buf->skb = napi_alloc_skb(&rx_ring->napi_rx, - IPQESS_RX_HEAD_BUFF_SIZE); - if (!buf->skb) - return -ENOMEM; - - return ipqess_rx_buf_prepare(buf, rx_ring); -} - -static int ipqess_rx_buf_alloc(struct ipqess_rx_ring *rx_ring) -{ - struct ipqess_buf *buf = &rx_ring->buf[rx_ring->head]; - - buf->skb = netdev_alloc_skb_ip_align(rx_ring->ess->netdev, - IPQESS_RX_HEAD_BUFF_SIZE); - if (!buf->skb) - return -ENOMEM; - - return ipqess_rx_buf_prepare(buf, rx_ring); -} - -static void ipqess_refill_work(struct work_struct *work) -{ - struct ipqess_rx_ring_refill *rx_refill = container_of(work, - struct ipqess_rx_ring_refill, refill_work); - struct ipqess_rx_ring *rx_ring = rx_refill->rx_ring; - int refill = 0; - - /* don't let this loop by accident. */ - while (atomic_dec_and_test(&rx_ring->refill_count)) { - napi_disable(&rx_ring->napi_rx); - if (ipqess_rx_buf_alloc(rx_ring)) { - refill++; - dev_dbg(rx_ring->ppdev, - "Not all buffers were reallocated"); - } - napi_enable(&rx_ring->napi_rx); - } - - if (atomic_add_return(refill, &rx_ring->refill_count)) - schedule_work(&rx_refill->refill_work); -} - - -static int ipqess_rx_ring_alloc(struct ipqess *ess) -{ - int i; - - for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) { - int j; - - ess->rx_ring[i].ess = ess; - ess->rx_ring[i].ppdev = &ess->pdev->dev; - ess->rx_ring[i].ring_id = i; - ess->rx_ring[i].idx = i * 2; - - ess->rx_ring[i].buf = devm_kzalloc(&ess->pdev->dev, - sizeof(struct ipqess_buf) * IPQESS_RX_RING_SIZE, - GFP_KERNEL); - if (!ess->rx_ring[i].buf) - return -ENOMEM; - - ess->rx_ring[i].hw_desc = dmam_alloc_coherent(&ess->pdev->dev, - sizeof(struct ipqess_rx_desc) * IPQESS_RX_RING_SIZE, - &ess->rx_ring[i].dma, GFP_KERNEL); - if (!ess->rx_ring[i].hw_desc) - return -ENOMEM; - - for (j = 0; j < IPQESS_RX_RING_SIZE; j++) - if (ipqess_rx_buf_alloc(&ess->rx_ring[i]) < 0) - return -ENOMEM; - - ess->rx_refill[i].rx_ring = &ess->rx_ring[i]; - INIT_WORK(&ess->rx_refill[i].refill_work, ipqess_refill_work); - - ipqess_w32(ess, IPQESS_REG_RFD_BASE_ADDR_Q(ess->rx_ring[i].idx), - (u32)(ess->rx_ring[i].dma)); - } - - ipqess_w32(ess, IPQESS_REG_RX_DESC0, - (IPQESS_RX_HEAD_BUFF_SIZE << IPQESS_RX_BUF_SIZE_SHIFT) | - (IPQESS_RX_RING_SIZE << IPQESS_RFD_RING_SIZE_SHIFT)); - - return 0; -} - -static void ipqess_rx_ring_free(struct ipqess *ess) -{ - int i; - - for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) { - int j; - - atomic_set(&ess->rx_ring[i].refill_count, 0); - cancel_work_sync(&ess->rx_refill[i].refill_work); - - for (j = 0; j < IPQESS_RX_RING_SIZE; j++) { - dma_unmap_single(&ess->pdev->dev, - ess->rx_ring[i].buf[j].dma, - ess->rx_ring[i].buf[j].length, - DMA_FROM_DEVICE); - dev_kfree_skb_any(ess->rx_ring[i].buf[j].skb); - } - } -} - -static struct net_device_stats *ipqess_get_stats(struct net_device *netdev) -{ - struct ipqess *ess = netdev_priv(netdev); - - spin_lock(&ess->stats_lock); - ipqess_update_hw_stats(ess); - spin_unlock(&ess->stats_lock); - - return &ess->stats; -} - -static int ipqess_rx_poll(struct ipqess_rx_ring *rx_ring, int budget) -{ - u32 length = 0, num_desc, tail, rx_ring_tail; - int done = 0; - - rx_ring_tail = rx_ring->tail; - - tail = ipqess_r32(rx_ring->ess, IPQESS_REG_RFD_IDX_Q(rx_ring->idx)); - tail >>= IPQESS_RFD_CONS_IDX_SHIFT; - tail &= IPQESS_RFD_CONS_IDX_MASK; - - while (done < budget) { - struct sk_buff *skb; - struct ipqess_rx_desc *rd; - - if (rx_ring_tail == tail) - break; - - dma_unmap_single(rx_ring->ppdev, - rx_ring->buf[rx_ring_tail].dma, - rx_ring->buf[rx_ring_tail].length, - DMA_FROM_DEVICE); - - skb = xchg(&rx_ring->buf[rx_ring_tail].skb, NULL); - rd = (struct ipqess_rx_desc *)skb->data; - rx_ring_tail = IPQESS_NEXT_IDX(rx_ring_tail, IPQESS_RX_RING_SIZE); - - /* Check if RRD is valid */ - if (!(rd->rrd7 & IPQESS_RRD_DESC_VALID)) { - num_desc = 1; - dev_kfree_skb_any(skb); - goto skip; - } - - num_desc = rd->rrd1 & IPQESS_RRD_NUM_RFD_MASK; - length = rd->rrd6 & IPQESS_RRD_PKT_SIZE_MASK; - - skb_reserve(skb, IPQESS_RRD_SIZE); - if (num_desc > 1) { - /* can we use build_skb here ? */ - struct sk_buff *skb_prev = NULL; - int size_remaining; - int i; - - skb->data_len = 0; - skb->tail += (IPQESS_RX_HEAD_BUFF_SIZE - IPQESS_RRD_SIZE); - skb->len = skb->truesize = length; - size_remaining = length - (IPQESS_RX_HEAD_BUFF_SIZE - IPQESS_RRD_SIZE); - - for (i = 1; i < num_desc; i++) { - /* TODO: use build_skb ? */ - struct sk_buff *skb_temp = rx_ring->buf[rx_ring_tail].skb; - - dma_unmap_single(rx_ring->ppdev, - rx_ring->buf[rx_ring_tail].dma, - rx_ring->buf[rx_ring_tail].length, - DMA_FROM_DEVICE); - - skb_put(skb_temp, min(size_remaining, IPQESS_RX_HEAD_BUFF_SIZE)); - if (skb_prev) - skb_prev->next = rx_ring->buf[rx_ring_tail].skb; - else - skb_shinfo(skb)->frag_list = rx_ring->buf[rx_ring_tail].skb; - skb_prev = rx_ring->buf[rx_ring_tail].skb; - rx_ring->buf[rx_ring_tail].skb->next = NULL; - - skb->data_len += rx_ring->buf[rx_ring_tail].skb->len; - size_remaining -= rx_ring->buf[rx_ring_tail].skb->len; - - rx_ring_tail = IPQESS_NEXT_IDX(rx_ring_tail, IPQESS_RX_RING_SIZE); - } - - } else { - skb_put(skb, length); - } - - skb->dev = rx_ring->ess->netdev; - skb->protocol = eth_type_trans(skb, rx_ring->ess->netdev); - skb_record_rx_queue(skb, rx_ring->ring_id); - - if (rd->rrd6 & IPQESS_RRD_CSUM_FAIL_MASK) - skb_checksum_none_assert(skb); - else - skb->ip_summed = CHECKSUM_UNNECESSARY; - - if (rd->rrd7 & IPQESS_RRD_CVLAN) { - __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rd->rrd4); - } else if (rd->rrd1 & IPQESS_RRD_SVLAN) { - __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), rd->rrd4); - } - napi_gro_receive(&rx_ring->napi_rx, skb); - - /* TODO: do we need to have these here ? */ - rx_ring->ess->stats.rx_packets++; - rx_ring->ess->stats.rx_bytes += length; - - done++; -skip: - - num_desc += atomic_xchg(&rx_ring->refill_count, 0); - while (num_desc) { - if (ipqess_rx_buf_alloc_napi(rx_ring)) { - num_desc = atomic_add_return(num_desc, - &rx_ring->refill_count); - if (num_desc >= ((4 * IPQESS_RX_RING_SIZE + 6) / 7)) - schedule_work(&rx_ring->ess->rx_refill[rx_ring->ring_id].refill_work); - break; - } - num_desc--; - } - } - - ipqess_w32(rx_ring->ess, IPQESS_REG_RX_SW_CONS_IDX_Q(rx_ring->idx), - rx_ring_tail); - rx_ring->tail = rx_ring_tail; - - return done; -} - -static int ipqess_tx_complete(struct ipqess_tx_ring *tx_ring, int budget) -{ - u32 tail; - int done = 0; - int total = 0, ret; - - tail = ipqess_r32(tx_ring->ess, IPQESS_REG_TPD_IDX_Q(tx_ring->idx)); - tail >>= IPQESS_TPD_CONS_IDX_SHIFT; - tail &= IPQESS_TPD_CONS_IDX_MASK; - - while ((tx_ring->tail != tail) && (done < budget)) { - //pr_info("freeing txq:%d tail:%d tailbuf:%p\n", tx_ring->idx, tx_ring->tail, &tx_ring->buf[tx_ring->tail]); - ret = ipqess_tx_unmap_and_free(&tx_ring->ess->pdev->dev, - &tx_ring->buf[tx_ring->tail]); - tx_ring->tail = IPQESS_NEXT_IDX(tx_ring->tail, tx_ring->count); - if (ret) { - total += ret; - done++; - } - } - - ipqess_w32(tx_ring->ess, - IPQESS_REG_TX_SW_CONS_IDX_Q(tx_ring->idx), - tx_ring->tail); - - if (netif_tx_queue_stopped(tx_ring->nq)) { - netdev_dbg(tx_ring->ess->netdev, "waking up tx queue %d\n", - tx_ring->idx); - netif_tx_wake_queue(tx_ring->nq); - } - - netdev_tx_completed_queue(tx_ring->nq, done, total); - - return done; -} - -static int ipqess_tx_napi(struct napi_struct *napi, int budget) -{ - struct ipqess_tx_ring *tx_ring = container_of(napi, struct ipqess_tx_ring, - napi_tx); - u32 tx_status; - int work_done = 0; - - tx_status = ipqess_r32(tx_ring->ess, IPQESS_REG_TX_ISR); - tx_status &= BIT(tx_ring->idx); - - work_done = ipqess_tx_complete(tx_ring, budget); - - ipqess_w32(tx_ring->ess, IPQESS_REG_TX_ISR, tx_status); - - if (likely(work_done < budget)) { - if (napi_complete_done(napi, work_done)) - ipqess_w32(tx_ring->ess, - IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx), 0x1); - } - - return work_done; -} - -static int ipqess_rx_napi(struct napi_struct *napi, int budget) -{ - struct ipqess_rx_ring *rx_ring = container_of(napi, struct ipqess_rx_ring, - napi_rx); - struct ipqess *ess = rx_ring->ess; - int remain_budget = budget; - int rx_done; - u32 rx_mask = BIT(rx_ring->idx); - u32 status; - -poll_again: - ipqess_w32(ess, IPQESS_REG_RX_ISR, rx_mask); - rx_done = ipqess_rx_poll(rx_ring, remain_budget); - - if (rx_done == remain_budget) - return budget; - - status = ipqess_r32(ess, IPQESS_REG_RX_ISR); - if (status & rx_mask) { - remain_budget -= rx_done; - goto poll_again; - } - - if (napi_complete_done(napi, rx_done + budget - remain_budget)) - ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(rx_ring->idx), 0x1); - - return rx_done + budget - remain_budget; -} - -static irqreturn_t ipqess_interrupt_tx(int irq, void *priv) -{ - struct ipqess_tx_ring *tx_ring = (struct ipqess_tx_ring *) priv; - - if (likely(napi_schedule_prep(&tx_ring->napi_tx))) { - ipqess_w32(tx_ring->ess, - IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx), - 0x0); - __napi_schedule(&tx_ring->napi_tx); - } - - return IRQ_HANDLED; -} - -static irqreturn_t ipqess_interrupt_rx(int irq, void *priv) -{ - struct ipqess_rx_ring *rx_ring = (struct ipqess_rx_ring *) priv; - - if (likely(napi_schedule_prep(&rx_ring->napi_rx))) { - ipqess_w32(rx_ring->ess, - IPQESS_REG_RX_INT_MASK_Q(rx_ring->idx), - 0x0); - __napi_schedule(&rx_ring->napi_rx); - } - - return IRQ_HANDLED; -} - -static void ipqess_irq_enable(struct ipqess *ess) -{ - int i; - - ipqess_w32(ess, IPQESS_REG_RX_ISR, 0xff); - ipqess_w32(ess, IPQESS_REG_TX_ISR, 0xffff); - for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) { - ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(ess->rx_ring[i].idx), 1); - ipqess_w32(ess, IPQESS_REG_TX_INT_MASK_Q(ess->tx_ring[i].idx), 1); - } -} - -static void ipqess_irq_disable(struct ipqess *ess) -{ - int i; - - for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) { - ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(ess->rx_ring[i].idx), 0); - ipqess_w32(ess, IPQESS_REG_TX_INT_MASK_Q(ess->tx_ring[i].idx), 0); - } -} - -static int __init ipqess_init(struct net_device *netdev) -{ - struct ipqess *ess = netdev_priv(netdev); - struct device_node *of_node = ess->pdev->dev.of_node; - return phylink_of_phy_connect(ess->phylink, of_node, 0); -} - -static void ipqess_uninit(struct net_device *netdev) -{ - struct ipqess *ess = netdev_priv(netdev); - - phylink_disconnect_phy(ess->phylink); -} - -static int ipqess_open(struct net_device *netdev) -{ - struct ipqess *ess = netdev_priv(netdev); - int i; - - for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) { - napi_enable(&ess->tx_ring[i].napi_tx); - napi_enable(&ess->rx_ring[i].napi_rx); - } - ipqess_irq_enable(ess); - phylink_start(ess->phylink); - netif_tx_start_all_queues(netdev); - - return 0; -} - -static int ipqess_stop(struct net_device *netdev) -{ - struct ipqess *ess = netdev_priv(netdev); - int i; - - netif_tx_stop_all_queues(netdev); - phylink_stop(ess->phylink); - ipqess_irq_disable(ess); - for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) { - napi_disable(&ess->tx_ring[i].napi_tx); - napi_disable(&ess->rx_ring[i].napi_rx); - } - - return 0; -} - -static int ipqess_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) -{ - struct ipqess *ess = netdev_priv(netdev); - - switch (cmd) { - case SIOCGMIIPHY: - case SIOCGMIIREG: - case SIOCSMIIREG: - return phylink_mii_ioctl(ess->phylink, ifr, cmd); - default: - break; - } - - return -EOPNOTSUPP; -} - - -static inline u16 ipqess_tx_desc_available(struct ipqess_tx_ring *tx_ring) -{ - u16 count = 0; - - if (tx_ring->tail <= tx_ring->head) - count = IPQESS_TX_RING_SIZE; - - count += tx_ring->tail - tx_ring->head - 1; - - return count; -} - -static inline int ipqess_cal_txd_req(struct sk_buff *skb) -{ - int tpds; - - /* one TPD for the header, and one for each fragments */ - tpds = 1 + skb_shinfo(skb)->nr_frags; - if (skb_is_gso(skb) && skb_is_gso_v6(skb)) { - /* for LSOv2 one extra TPD is needed */ - tpds++; - } - - return tpds; -} - -static struct ipqess_buf *ipqess_get_tx_buffer(struct ipqess_tx_ring *tx_ring, - struct ipqess_tx_desc *desc) -{ - return &tx_ring->buf[desc - tx_ring->hw_desc]; -} - -static struct ipqess_tx_desc *ipqess_tx_desc_next(struct ipqess_tx_ring *tx_ring) -{ - struct ipqess_tx_desc *desc; - - desc = &tx_ring->hw_desc[tx_ring->head]; - tx_ring->head = IPQESS_NEXT_IDX(tx_ring->head, tx_ring->count); - - return desc; -} - -static void ipqess_rollback_tx(struct ipqess *eth, - struct ipqess_tx_desc *first_desc, int ring_id) -{ - struct ipqess_tx_ring *tx_ring = ð->tx_ring[ring_id]; - struct ipqess_buf *buf; - struct ipqess_tx_desc *desc = NULL; - u16 start_index, index; - - start_index = first_desc - tx_ring->hw_desc; - - index = start_index; - while (index != tx_ring->head) { - desc = &tx_ring->hw_desc[index]; - buf = &tx_ring->buf[index]; - ipqess_tx_unmap_and_free(ð->pdev->dev, buf); - memset(desc, 0, sizeof(struct ipqess_tx_desc)); - if (++index == tx_ring->count) - index = 0; - } - tx_ring->head = start_index; -} - -static bool ipqess_process_dsa_tag_sh(struct sk_buff *skb, u32 *word3) -{ - struct skb_shared_info *shinfo = skb_shinfo(skb); - struct ipq40xx_dsa_tag_data *tag_data; - - if (shinfo->dsa_tag_proto != DSA_TAG_PROTO_IPQ4019) - return false; - - tag_data = (struct ipq40xx_dsa_tag_data *)shinfo->dsa_tag_data; - - pr_debug("SH tag @ %08x, dp:%02x from_cpu:%u\n", - (u32)tag_data, tag_data->dp, tag_data->from_cpu); - - *word3 |= tag_data->dp << IPQESS_TPD_PORT_BITMAP_SHIFT; - if (tag_data->from_cpu) - *word3 |= BIT(IPQESS_TPD_FROM_CPU_SHIFT); - - return true; -} - -static void ipqess_get_dp_info(struct ipqess *ess, struct sk_buff *skb, - u32 *word3) -{ - if (netdev_uses_dsa(ess->netdev)) { - - if (ipqess_process_dsa_tag_sh(skb, word3)) - return; - } - - *word3 |= 0x3e << IPQESS_TPD_PORT_BITMAP_SHIFT; -} - -static int ipqess_tx_map_and_fill(struct ipqess_tx_ring *tx_ring, struct sk_buff *skb) -{ - struct ipqess_buf *buf = NULL; - struct platform_device *pdev = tx_ring->ess->pdev; - struct ipqess_tx_desc *desc = NULL, *first_desc = NULL; - u32 word1 = 0, word3 = 0, lso_word1 = 0, svlan_tag = 0; - u16 len; - int i; - - ipqess_get_dp_info(tx_ring->ess, skb, &word3); - - if (skb_is_gso(skb)) { - if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) { - lso_word1 |= IPQESS_TPD_IPV4_EN; - ip_hdr(skb)->check = 0; - tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr, - ip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0); - } else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { - lso_word1 |= IPQESS_TPD_LSO_V2_EN; - ipv6_hdr(skb)->payload_len = 0; - tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, - &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0); - } - - lso_word1 |= IPQESS_TPD_LSO_EN | - ((skb_shinfo(skb)->gso_size & IPQESS_TPD_MSS_MASK) << IPQESS_TPD_MSS_SHIFT) | - (skb_transport_offset(skb) << IPQESS_TPD_HDR_SHIFT); - } else if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { - u8 css, cso; - cso = skb_checksum_start_offset(skb); - css = cso + skb->csum_offset; - - word1 |= (IPQESS_TPD_CUSTOM_CSUM_EN); - word1 |= (cso >> 1) << IPQESS_TPD_HDR_SHIFT; - word1 |= ((css >> 1) << IPQESS_TPD_CUSTOM_CSUM_SHIFT); - } - - if (skb_vlan_tag_present(skb)) { - switch (skb->vlan_proto) { - case htons(ETH_P_8021Q): - word3 |= BIT(IPQESS_TX_INS_CVLAN); - word3 |= skb_vlan_tag_get(skb) << IPQESS_TX_CVLAN_TAG_SHIFT; - break; - case htons(ETH_P_8021AD): - word1 |= BIT(IPQESS_TX_INS_SVLAN); - svlan_tag = skb_vlan_tag_get(skb); - break; - default: - dev_err(&pdev->dev, "no ctag or stag present\n"); - goto vlan_tag_error; - } - } - - if (eth_type_vlan(skb->protocol)) - word1 |= IPQESS_TPD_VLAN_TAGGED; - - if (skb->protocol == htons(ETH_P_PPP_SES)) - word1 |= IPQESS_TPD_PPPOE_EN; - - len = skb_headlen(skb); - - first_desc = desc = ipqess_tx_desc_next(tx_ring); - if (lso_word1 & IPQESS_TPD_LSO_V2_EN) { - desc->addr = cpu_to_le16(skb->len); - desc->word1 = word1 | lso_word1; - desc->svlan_tag = svlan_tag; - desc->word3 = word3; - desc = ipqess_tx_desc_next(tx_ring); - } - - buf = ipqess_get_tx_buffer(tx_ring, desc); - buf->length = len; - buf->dma = dma_map_single(&pdev->dev, - skb->data, len, DMA_TO_DEVICE); - if (dma_mapping_error(&pdev->dev, buf->dma)) - goto dma_error; - - desc->addr = cpu_to_le32(buf->dma); - desc->len = cpu_to_le16(len); - - buf->flags |= IPQESS_DESC_SINGLE; - desc->word1 = word1 | lso_word1; - desc->svlan_tag = svlan_tag; - desc->word3 = word3; - - for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { - skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; - len = skb_frag_size(frag); - desc = ipqess_tx_desc_next(tx_ring); - buf = ipqess_get_tx_buffer(tx_ring, desc); - buf->length = len; - buf->flags |= IPQESS_DESC_PAGE; - buf->dma = skb_frag_dma_map(&pdev->dev, frag, 0, len, DMA_TO_DEVICE); - if (dma_mapping_error(&pdev->dev, buf->dma)) - goto dma_error; - - desc->addr = cpu_to_le32(buf->dma); - desc->len = cpu_to_le16(len); - desc->svlan_tag = svlan_tag; - desc->word1 = word1 | lso_word1; - desc->word3 = word3; - } - desc->word1 |= 1 << IPQESS_TPD_EOP_SHIFT; - buf->skb = skb; - buf->flags |= IPQESS_DESC_LAST; - - return 0; - -dma_error: - ipqess_rollback_tx(tx_ring->ess, first_desc, tx_ring->ring_id); - dev_err(&pdev->dev, "TX DMA map failed\n"); - -vlan_tag_error: - return -ENOMEM; -} - -static inline void ipqess_kick_tx(struct ipqess_tx_ring *tx_ring) -{ - /* Ensure that all TPDs has been written completely */ - dma_wmb(); - - /* update software producer index */ - ipqess_w32(tx_ring->ess, IPQESS_REG_TPD_IDX_Q(tx_ring->idx), - tx_ring->head); -} - -static netdev_tx_t ipqess_xmit(struct sk_buff *skb, - struct net_device *netdev) -{ - struct ipqess *ess = netdev_priv(netdev); - struct ipqess_tx_ring *tx_ring; - int avail; - int tx_num; - int ret; - - tx_ring = &ess->tx_ring[skb_get_queue_mapping(skb)]; - tx_num = ipqess_cal_txd_req(skb); - avail = ipqess_tx_desc_available(tx_ring); - if (avail < tx_num) { - netdev_dbg(netdev, - "stopping tx queue %d, avail=%d req=%d im=%x\n", - tx_ring->idx, avail, tx_num, - ipqess_r32(tx_ring->ess, - IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx))); - netif_tx_stop_queue(tx_ring->nq); - ipqess_w32(tx_ring->ess, IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx), 0x1); - ipqess_kick_tx(tx_ring); - return NETDEV_TX_BUSY; - } - - ret = ipqess_tx_map_and_fill(tx_ring, skb); - if (ret) { - dev_kfree_skb_any(skb); - ess->stats.tx_errors++; - goto err_out; - } - - ess->stats.tx_packets++; - ess->stats.tx_bytes += skb->len; - netdev_tx_sent_queue(tx_ring->nq, skb->len); - - if (!netdev_xmit_more() || netif_xmit_stopped(tx_ring->nq)) - ipqess_kick_tx(tx_ring); - -err_out: - return NETDEV_TX_OK; -} - -static int ipqess_set_mac_address(struct net_device *netdev, void *p) -{ - int ret = eth_mac_addr(netdev, p); - struct ipqess *ess = netdev_priv(netdev); - const char *macaddr = netdev->dev_addr; - - if (ret) - return ret; - -// spin_lock_bh(&mac->hw->page_lock); - ipqess_w32(ess, IPQESS_REG_MAC_CTRL1, - (macaddr[0] << 8) | macaddr[1]); - ipqess_w32(ess, IPQESS_REG_MAC_CTRL0, - (macaddr[2] << 24) | (macaddr[3] << 16) | - (macaddr[4] << 8) | macaddr[5]); -// spin_unlock_bh(&mac->hw->page_lock); - - return 0; -} - -static void ipqess_tx_timeout(struct net_device *netdev, unsigned int txq_id) -{ - struct ipqess *ess = netdev_priv(netdev); - struct ipqess_tx_ring *tr = &ess->tx_ring[txq_id]; - - netdev_warn(netdev, "hardware queue %d is in stuck?\n", - tr->idx); - - /* TODO: dump hardware queue */ -} - -static const struct net_device_ops ipqess_axi_netdev_ops = { - .ndo_init = ipqess_init, - .ndo_uninit = ipqess_uninit, - .ndo_open = ipqess_open, - .ndo_stop = ipqess_stop, - .ndo_do_ioctl = ipqess_do_ioctl, - .ndo_start_xmit = ipqess_xmit, - .ndo_get_stats = ipqess_get_stats, - .ndo_set_mac_address = ipqess_set_mac_address, - .ndo_tx_timeout = ipqess_tx_timeout, -}; - -static void ipqess_hw_stop(struct ipqess *ess) -{ - int i; - - /* disable all RX queue IRQs */ - for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++) - ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(i), 0); - - /* disable all TX queue IRQs */ - for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++) - ipqess_w32(ess, IPQESS_REG_TX_INT_MASK_Q(i), 0); - - /* disable all other IRQs */ - ipqess_w32(ess, IPQESS_REG_MISC_IMR, 0); - ipqess_w32(ess, IPQESS_REG_WOL_IMR, 0); - - /* clear the IRQ status registers */ - ipqess_w32(ess, IPQESS_REG_RX_ISR, 0xff); - ipqess_w32(ess, IPQESS_REG_TX_ISR, 0xffff); - ipqess_w32(ess, IPQESS_REG_MISC_ISR, 0x1fff); - ipqess_w32(ess, IPQESS_REG_WOL_ISR, 0x1); - ipqess_w32(ess, IPQESS_REG_WOL_CTRL, 0); - - /* disable RX and TX queues */ - ipqess_m32(ess, IPQESS_RXQ_CTRL_EN_MASK, 0, IPQESS_REG_RXQ_CTRL); - ipqess_m32(ess, IPQESS_TXQ_CTRL_TXQ_EN, 0, IPQESS_REG_TXQ_CTRL); -} - -static int ipqess_hw_init(struct ipqess *ess) -{ - u32 tmp; - int i, err; - - ipqess_hw_stop(ess); - - ipqess_m32(ess, BIT(IPQESS_INTR_SW_IDX_W_TYP_SHIFT), - IPQESS_INTR_SW_IDX_W_TYPE << IPQESS_INTR_SW_IDX_W_TYP_SHIFT, - IPQESS_REG_INTR_CTRL); - - /* enable IRQ delay slot */ - ipqess_w32(ess, IPQESS_REG_IRQ_MODRT_TIMER_INIT, - (IPQESS_TX_IMT << IPQESS_IRQ_MODRT_TX_TIMER_SHIFT) | - (IPQESS_RX_IMT << IPQESS_IRQ_MODRT_RX_TIMER_SHIFT)); - - /* Set Customer and Service VLAN TPIDs */ - ipqess_w32(ess, IPQESS_REG_VLAN_CFG, - (ETH_P_8021Q << IPQESS_VLAN_CFG_CVLAN_TPID_SHIFT) | - (ETH_P_8021AD << IPQESS_VLAN_CFG_SVLAN_TPID_SHIFT)); - - /* Configure the TX Queue bursting */ - ipqess_w32(ess, IPQESS_REG_TXQ_CTRL, - (IPQESS_TPD_BURST << IPQESS_TXQ_NUM_TPD_BURST_SHIFT) | - (IPQESS_TXF_BURST << IPQESS_TXQ_TXF_BURST_NUM_SHIFT) | - IPQESS_TXQ_CTRL_TPD_BURST_EN); - - /* Set RSS type */ - ipqess_w32(ess, IPQESS_REG_RSS_TYPE, - IPQESS_RSS_TYPE_IPV4TCP | IPQESS_RSS_TYPE_IPV6_TCP | - IPQESS_RSS_TYPE_IPV4_UDP | IPQESS_RSS_TYPE_IPV6UDP | - IPQESS_RSS_TYPE_IPV4 | IPQESS_RSS_TYPE_IPV6); - - /* Set RFD ring burst and threshold */ - ipqess_w32(ess, IPQESS_REG_RX_DESC1, - (IPQESS_RFD_BURST << IPQESS_RXQ_RFD_BURST_NUM_SHIFT) | - (IPQESS_RFD_THR << IPQESS_RXQ_RFD_PF_THRESH_SHIFT) | - (IPQESS_RFD_LTHR << IPQESS_RXQ_RFD_LOW_THRESH_SHIFT)); - - /* Set Rx FIFO - * - threshold to start to DMA data to host - */ - ipqess_w32(ess, IPQESS_REG_RXQ_CTRL, - IPQESS_FIFO_THRESH_128_BYTE | IPQESS_RXQ_CTRL_RMV_VLAN); - - err = ipqess_rx_ring_alloc(ess); - if (err) - return err; - - err = ipqess_tx_ring_alloc(ess); - if (err) - return err; - - /* Load all of ring base addresses above into the dma engine */ - ipqess_m32(ess, 0, BIT(IPQESS_LOAD_PTR_SHIFT), - IPQESS_REG_TX_SRAM_PART); - - /* Disable TX FIFO low watermark and high watermark */ - ipqess_w32(ess, IPQESS_REG_TXF_WATER_MARK, 0); - - /* Configure RSS indirection table. - * 128 hash will be configured in the following - * pattern: hash{0,1,2,3} = {Q0,Q2,Q4,Q6} respectively - * and so on - */ - for (i = 0; i < IPQESS_NUM_IDT; i++) - ipqess_w32(ess, IPQESS_REG_RSS_IDT(i), IPQESS_RSS_IDT_VALUE); - - /* Configure load balance mapping table. - * 4 table entry will be configured according to the - * following pattern: load_balance{0,1,2,3} = {Q0,Q1,Q3,Q4} - * respectively. - */ - ipqess_w32(ess, IPQESS_REG_LB_RING, IPQESS_LB_REG_VALUE); - - /* Configure Virtual queue for Tx rings */ - ipqess_w32(ess, IPQESS_REG_VQ_CTRL0, IPQESS_VQ_REG_VALUE); - ipqess_w32(ess, IPQESS_REG_VQ_CTRL1, IPQESS_VQ_REG_VALUE); - - /* Configure Max AXI Burst write size to 128 bytes*/ - ipqess_w32(ess, IPQESS_REG_AXIW_CTRL_MAXWRSIZE, - IPQESS_AXIW_MAXWRSIZE_VALUE); - - /* Enable TX queues */ - ipqess_m32(ess, 0, IPQESS_TXQ_CTRL_TXQ_EN, IPQESS_REG_TXQ_CTRL); - - /* Enable RX queues */ - tmp = 0; - for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) - tmp |= IPQESS_RXQ_CTRL_EN(ess->rx_ring[i].idx); - - ipqess_m32(ess, IPQESS_RXQ_CTRL_EN_MASK, tmp, IPQESS_REG_RXQ_CTRL); - - return 0; -} - -static void ipqess_validate(struct phylink_config *config, - unsigned long *supported, - struct phylink_link_state *state) -{ - struct ipqess *ess = container_of(config, struct ipqess, phylink_config); - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; - - if (state->interface != PHY_INTERFACE_MODE_INTERNAL) { - dev_err(&ess->pdev->dev, "unsupported interface mode: %d\n", - state->interface); - linkmode_zero(supported); - return; - } - - phylink_set_port_modes(mask); - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, Pause); - phylink_set(mask, Asym_Pause); - - linkmode_and(supported, supported, mask); - linkmode_and(state->advertising, state->advertising, mask); -} - -static void ipqess_mac_config(struct phylink_config *config, unsigned int mode, - const struct phylink_link_state *state) -{ - /* TODO */ -} - -static void ipqess_mac_link_down(struct phylink_config *config, - unsigned int mode, - phy_interface_t interface) -{ - /* TODO */ -} - -static void ipqess_mac_link_up(struct phylink_config *config, - struct phy_device *phy, unsigned int mode, - phy_interface_t interface, - int speed, int duplex, - bool tx_pause, bool rx_pause) -{ - /* TODO */ -} - -static struct phylink_mac_ops ipqess_phylink_mac_ops = { - .validate = ipqess_validate, - .mac_config = ipqess_mac_config, - .mac_link_up = ipqess_mac_link_up, - .mac_link_down = ipqess_mac_link_down, -}; - -static void ipqess_cleanup(struct ipqess *ess) -{ - ipqess_hw_stop(ess); - unregister_netdev(ess->netdev); - - ipqess_tx_ring_free(ess); - ipqess_rx_ring_free(ess); - - if (!IS_ERR_OR_NULL(ess->phylink)) - phylink_destroy(ess->phylink); -} - -static void ess_reset(struct ipqess *ess) -{ - reset_control_assert(ess->ess_rst); - - mdelay(10); - - reset_control_deassert(ess->ess_rst); - - /* Waiting for all inner tables to be flushed and reinitialized. - * This takes between 5 and 10ms. - */ - mdelay(10); -} - -static int ipqess_axi_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct ipqess *ess; - struct net_device *netdev; - struct resource *res; - int i, err = 0; - - netdev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct ipqess), - IPQESS_NETDEV_QUEUES, - IPQESS_NETDEV_QUEUES); - if (!netdev) - return -ENOMEM; - - ess = netdev_priv(netdev); - ess->netdev = netdev; - ess->pdev = pdev; - spin_lock_init(&ess->stats_lock); - SET_NETDEV_DEV(netdev, &pdev->dev); - platform_set_drvdata(pdev, netdev); - - err = of_get_mac_address(np, netdev->dev_addr); - if (err == -EPROBE_DEFER) - return -EPROBE_DEFER; - - if (err) { - - random_ether_addr(netdev->dev_addr); - dev_info(&ess->pdev->dev, "generated random MAC address %pM\n", - netdev->dev_addr); - netdev->addr_assign_type = NET_ADDR_RANDOM; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ess->hw_addr = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(ess->hw_addr)) { - err = PTR_ERR(ess->hw_addr); - goto err_out; - } - - ess->ess_clk = of_clk_get_by_name(np, "ess_clk"); - if (IS_ERR(ess->ess_clk)) { - dev_err(&pdev->dev, "Failed to get ess_clk\n"); - return PTR_ERR(ess->ess_clk); - } - - ess->ess_rst = devm_reset_control_get(&pdev->dev, "ess_rst"); - if (IS_ERR(ess->ess_rst)) { - dev_err(&pdev->dev, "Failed to get ess_rst control!\n"); - return PTR_ERR(ess->ess_rst); - } - - clk_prepare_enable(ess->ess_clk); - - ess_reset(ess); - - ess->phylink_config.dev = &netdev->dev; - ess->phylink_config.type = PHYLINK_NETDEV; - ess->phylink_config.pcs_poll = true; - - ess->phylink = phylink_create(&ess->phylink_config, - of_fwnode_handle(np), - PHY_INTERFACE_MODE_INTERNAL, - &ipqess_phylink_mac_ops); - if (IS_ERR(ess->phylink)) { - err = PTR_ERR(ess->phylink); - goto err_out; - } - - for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++) { - ess->tx_irq[i] = platform_get_irq(pdev, i); - scnprintf(ess->tx_irq_names[i], sizeof(ess->tx_irq_names[i]), - "%s:txq%d", pdev->name, i); - } - - for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++) { - ess->rx_irq[i] = platform_get_irq(pdev, i + IPQESS_MAX_TX_QUEUE); - scnprintf(ess->rx_irq_names[i], sizeof(ess->rx_irq_names[i]), - "%s:rxq%d", pdev->name, i); - } - -#undef NETIF_F_TSO6 -#define NETIF_F_TSO6 0 - - netdev->netdev_ops = &ipqess_axi_netdev_ops; - netdev->features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM | - NETIF_F_HW_VLAN_CTAG_RX | - NETIF_F_HW_VLAN_CTAG_TX | - NETIF_F_TSO | NETIF_F_TSO6 | - NETIF_F_GRO | NETIF_F_SG; - /* feature change is not supported yet */ - netdev->hw_features = 0; - netdev->vlan_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_RXCSUM | - NETIF_F_TSO | NETIF_F_TSO6 | - NETIF_F_GRO; - netdev->watchdog_timeo = 5 * HZ; - netdev->base_addr = (u32) ess->hw_addr; - netdev->max_mtu = 9000; - netdev->gso_max_segs = IPQESS_TX_RING_SIZE / 2; - - ipqess_set_ethtool_ops(netdev); - - err = register_netdev(netdev); - if (err) - goto err_out; - - err = ipqess_hw_init(ess); - if (err) - goto err_out; - - dev_set_threaded(netdev, true); - - for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) { - int qid; - - netif_tx_napi_add(netdev, &ess->tx_ring[i].napi_tx, - ipqess_tx_napi, 64); - netif_napi_add(netdev, - &ess->rx_ring[i].napi_rx, - ipqess_rx_napi, 64); - - qid = ess->tx_ring[i].idx; - err = devm_request_irq(&ess->netdev->dev, ess->tx_irq[qid], - ipqess_interrupt_tx, 0, ess->tx_irq_names[qid], - &ess->tx_ring[i]); - if (err) - goto err_out; - - qid = ess->rx_ring[i].idx; - err = devm_request_irq(&ess->netdev->dev, ess->rx_irq[qid], - ipqess_interrupt_rx, 0, ess->rx_irq_names[qid], - &ess->rx_ring[i]); - if (err) - goto err_out; - } - - return 0; - -err_out: - ipqess_cleanup(ess); - return err; -} - -static int ipqess_axi_remove(struct platform_device *pdev) -{ - const struct net_device *netdev = platform_get_drvdata(pdev); - struct ipqess *ess = netdev_priv(netdev); - - ipqess_cleanup(ess); - - return 0; -} - -static const struct of_device_id ipqess_of_mtable[] = { - {.compatible = "qcom,ipq4019-ess-edma" }, - {} -}; -MODULE_DEVICE_TABLE(of, ipqess_of_mtable); - -static struct platform_driver ipqess_axi_driver = { - .driver = { - .name = "ipqess-edma", - .of_match_table = ipqess_of_mtable, - }, - .probe = ipqess_axi_probe, - .remove = ipqess_axi_remove, -}; - -module_platform_driver(ipqess_axi_driver); - -MODULE_AUTHOR("Qualcomm Atheros Inc"); -MODULE_AUTHOR("John Crispin "); -MODULE_AUTHOR("Christian Lamparter "); -MODULE_AUTHOR("Gabor Juhos "); -MODULE_LICENSE("GPL"); diff --git a/target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess.h b/target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess.h deleted file mode 100644 index ca4cb7b2d42..00000000000 --- a/target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess.h +++ /dev/null @@ -1,530 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR ISC) -/* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved. - * Copyright (c) 2017 - 2018, John Crispin - * Copyright (c) 2018 - 2019, Christian Lamparter - * Copyright (c) 2020 - 2021, Gabor Juhos - * - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef _IPQESS_H_ -#define _IPQESS_H_ - -#define IPQESS_NETDEV_QUEUES 4 - -#define IPQESS_TPD_EOP_SHIFT 31 - -#define IPQESS_PORT_ID_SHIFT 12 -#define IPQESS_PORT_ID_MASK 0x7 - -/* tpd word 3 bit 18-28 */ -#define IPQESS_TPD_PORT_BITMAP_SHIFT 18 - -#define IPQESS_TPD_FROM_CPU_SHIFT 25 - -#define IPQESS_RX_RING_SIZE 128 -#define IPQESS_RX_HEAD_BUFF_SIZE 1540 -#define IPQESS_TX_RING_SIZE 128 -#define IPQESS_MAX_RX_QUEUE 8 -#define IPQESS_MAX_TX_QUEUE 16 - - -/* Configurations */ -#define IPQESS_INTR_CLEAR_TYPE 0 -#define IPQESS_INTR_SW_IDX_W_TYPE 0 -#define IPQESS_FIFO_THRESH_TYPE 0 -#define IPQESS_RSS_TYPE 0 -#define IPQESS_RX_IMT 0x0020 -#define IPQESS_TX_IMT 0x0050 -#define IPQESS_TPD_BURST 5 -#define IPQESS_TXF_BURST 0x100 -#define IPQESS_RFD_BURST 8 -#define IPQESS_RFD_THR 16 -#define IPQESS_RFD_LTHR 0 - -/* Flags used in transmit direction */ -#define IPQESS_DESC_LAST 0x1 -#define IPQESS_DESC_SINGLE 0x2 -#define IPQESS_DESC_PAGE 0x4 - -struct ipqesstool_statistics { - u32 tx_q0_pkt; - u32 tx_q1_pkt; - u32 tx_q2_pkt; - u32 tx_q3_pkt; - u32 tx_q4_pkt; - u32 tx_q5_pkt; - u32 tx_q6_pkt; - u32 tx_q7_pkt; - u32 tx_q8_pkt; - u32 tx_q9_pkt; - u32 tx_q10_pkt; - u32 tx_q11_pkt; - u32 tx_q12_pkt; - u32 tx_q13_pkt; - u32 tx_q14_pkt; - u32 tx_q15_pkt; - u32 tx_q0_byte; - u32 tx_q1_byte; - u32 tx_q2_byte; - u32 tx_q3_byte; - u32 tx_q4_byte; - u32 tx_q5_byte; - u32 tx_q6_byte; - u32 tx_q7_byte; - u32 tx_q8_byte; - u32 tx_q9_byte; - u32 tx_q10_byte; - u32 tx_q11_byte; - u32 tx_q12_byte; - u32 tx_q13_byte; - u32 tx_q14_byte; - u32 tx_q15_byte; - u32 rx_q0_pkt; - u32 rx_q1_pkt; - u32 rx_q2_pkt; - u32 rx_q3_pkt; - u32 rx_q4_pkt; - u32 rx_q5_pkt; - u32 rx_q6_pkt; - u32 rx_q7_pkt; - u32 rx_q0_byte; - u32 rx_q1_byte; - u32 rx_q2_byte; - u32 rx_q3_byte; - u32 rx_q4_byte; - u32 rx_q5_byte; - u32 rx_q6_byte; - u32 rx_q7_byte; - u32 tx_desc_error; -}; - -struct ipqess_tx_desc { - __le16 len; - __le16 svlan_tag; - __le32 word1; - __le32 addr; - __le32 word3; -} __aligned(16) __packed; - -struct ipqess_rx_desc { - u16 rrd0; - u16 rrd1; - u16 rrd2; - u16 rrd3; - u16 rrd4; - u16 rrd5; - u16 rrd6; - u16 rrd7; -} __aligned(16) __packed; - -struct ipqess_buf { - struct sk_buff *skb; - dma_addr_t dma; - u32 flags; - u16 length; -}; - -struct ipqess_tx_ring { - struct napi_struct napi_tx; - u32 idx; - int ring_id; - struct ipqess *ess; - struct netdev_queue *nq; - struct ipqess_tx_desc *hw_desc; - struct ipqess_buf *buf; - dma_addr_t dma; - u16 count; - u16 head; - u16 tail; -}; - -struct ipqess_rx_ring { - struct napi_struct napi_rx; - u32 idx; - int ring_id; - struct ipqess *ess; - struct device *ppdev; - struct ipqess_rx_desc **hw_desc; - struct ipqess_buf *buf; - dma_addr_t dma; - u16 head; - u16 tail; - atomic_t refill_count; -}; - -struct ipqess_rx_ring_refill { - struct ipqess_rx_ring *rx_ring; - struct work_struct refill_work; -}; - -#define IPQESS_IRQ_NAME_LEN 32 - -struct ipqess { - struct net_device *netdev; - void __iomem *hw_addr; - struct clk *ess_clk; - struct reset_control *ess_rst; - - struct ipqess_rx_ring rx_ring[IPQESS_NETDEV_QUEUES]; - - struct platform_device *pdev; - struct phylink *phylink; - struct phylink_config phylink_config; - struct ipqess_tx_ring tx_ring[IPQESS_NETDEV_QUEUES]; - - struct ipqesstool_statistics ipqessstats; - spinlock_t stats_lock; - struct net_device_stats stats; - - struct ipqess_rx_ring_refill rx_refill[IPQESS_NETDEV_QUEUES]; - u32 tx_irq[IPQESS_MAX_TX_QUEUE]; - char tx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN]; - u32 rx_irq[IPQESS_MAX_RX_QUEUE]; - char rx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN]; -}; - -static inline void build_test(void) -{ - struct ipqess *ess; - BUILD_BUG_ON(ARRAY_SIZE(ess->rx_ring) != ARRAY_SIZE(ess->rx_refill)); -} - -void ipqess_set_ethtool_ops(struct net_device *netdev); -void ipqess_update_hw_stats(struct ipqess *ess); - -/* register definition */ -#define IPQESS_REG_MAS_CTRL 0x0 -#define IPQESS_REG_TIMEOUT_CTRL 0x004 -#define IPQESS_REG_DBG0 0x008 -#define IPQESS_REG_DBG1 0x00C -#define IPQESS_REG_SW_CTRL0 0x100 -#define IPQESS_REG_SW_CTRL1 0x104 - -/* Interrupt Status Register */ -#define IPQESS_REG_RX_ISR 0x200 -#define IPQESS_REG_TX_ISR 0x208 -#define IPQESS_REG_MISC_ISR 0x210 -#define IPQESS_REG_WOL_ISR 0x218 - -#define IPQESS_MISC_ISR_RX_URG_Q(x) (1 << x) - -#define IPQESS_MISC_ISR_AXIR_TIMEOUT 0x00000100 -#define IPQESS_MISC_ISR_AXIR_ERR 0x00000200 -#define IPQESS_MISC_ISR_TXF_DEAD 0x00000400 -#define IPQESS_MISC_ISR_AXIW_ERR 0x00000800 -#define IPQESS_MISC_ISR_AXIW_TIMEOUT 0x00001000 - -#define IPQESS_WOL_ISR 0x00000001 - -/* Interrupt Mask Register */ -#define IPQESS_REG_MISC_IMR 0x214 -#define IPQESS_REG_WOL_IMR 0x218 - -#define IPQESS_RX_IMR_NORMAL_MASK 0x1 -#define IPQESS_TX_IMR_NORMAL_MASK 0x1 -#define IPQESS_MISC_IMR_NORMAL_MASK 0x80001FFF -#define IPQESS_WOL_IMR_NORMAL_MASK 0x1 - -/* Edma receive consumer index */ -#define IPQESS_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */ - -/* Edma transmit consumer index */ -#define IPQESS_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */ - -/* IRQ Moderator Initial Timer Register */ -#define IPQESS_REG_IRQ_MODRT_TIMER_INIT 0x280 -#define IPQESS_IRQ_MODRT_TIMER_MASK 0xFFFF -#define IPQESS_IRQ_MODRT_RX_TIMER_SHIFT 0 -#define IPQESS_IRQ_MODRT_TX_TIMER_SHIFT 16 - -/* Interrupt Control Register */ -#define IPQESS_REG_INTR_CTRL 0x284 -#define IPQESS_INTR_CLR_TYP_SHIFT 0 -#define IPQESS_INTR_SW_IDX_W_TYP_SHIFT 1 -#define IPQESS_INTR_CLEAR_TYPE_W1 0 -#define IPQESS_INTR_CLEAR_TYPE_R 1 - -/* RX Interrupt Mask Register */ -#define IPQESS_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */ - -/* TX Interrupt mask register */ -#define IPQESS_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */ - -/* Load Ptr Register - * Software sets this bit after the initialization of the head and tail - */ -#define IPQESS_REG_TX_SRAM_PART 0x400 -#define IPQESS_LOAD_PTR_SHIFT 16 - -/* TXQ Control Register */ -#define IPQESS_REG_TXQ_CTRL 0x404 -#define IPQESS_TXQ_CTRL_IP_OPTION_EN 0x10 -#define IPQESS_TXQ_CTRL_TXQ_EN 0x20 -#define IPQESS_TXQ_CTRL_ENH_MODE 0x40 -#define IPQESS_TXQ_CTRL_LS_8023_EN 0x80 -#define IPQESS_TXQ_CTRL_TPD_BURST_EN 0x100 -#define IPQESS_TXQ_CTRL_LSO_BREAK_EN 0x200 -#define IPQESS_TXQ_NUM_TPD_BURST_MASK 0xF -#define IPQESS_TXQ_TXF_BURST_NUM_MASK 0xFFFF -#define IPQESS_TXQ_NUM_TPD_BURST_SHIFT 0 -#define IPQESS_TXQ_TXF_BURST_NUM_SHIFT 16 - -#define IPQESS_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */ -#define IPQESS_TXF_WATER_MARK_MASK 0x0FFF -#define IPQESS_TXF_LOW_WATER_MARK_SHIFT 0 -#define IPQESS_TXF_HIGH_WATER_MARK_SHIFT 16 -#define IPQESS_TXQ_CTRL_BURST_MODE_EN 0x80000000 - -/* WRR Control Register */ -#define IPQESS_REG_WRR_CTRL_Q0_Q3 0x40c -#define IPQESS_REG_WRR_CTRL_Q4_Q7 0x410 -#define IPQESS_REG_WRR_CTRL_Q8_Q11 0x414 -#define IPQESS_REG_WRR_CTRL_Q12_Q15 0x418 - -/* Weight round robin(WRR), it takes queue as input, and computes - * starting bits where we need to write the weight for a particular - * queue - */ -#define IPQESS_WRR_SHIFT(x) (((x) * 5) % 20) - -/* Tx Descriptor Control Register */ -#define IPQESS_REG_TPD_RING_SIZE 0x41C -#define IPQESS_TPD_RING_SIZE_SHIFT 0 -#define IPQESS_TPD_RING_SIZE_MASK 0xFFFF - -/* Transmit descriptor base address */ -#define IPQESS_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */ - -/* TPD Index Register */ -#define IPQESS_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */ - -#define IPQESS_TPD_PROD_IDX_BITS 0x0000FFFF -#define IPQESS_TPD_CONS_IDX_BITS 0xFFFF0000 -#define IPQESS_TPD_PROD_IDX_MASK 0xFFFF -#define IPQESS_TPD_CONS_IDX_MASK 0xFFFF -#define IPQESS_TPD_PROD_IDX_SHIFT 0 -#define IPQESS_TPD_CONS_IDX_SHIFT 16 - -/* TX Virtual Queue Mapping Control Register */ -#define IPQESS_REG_VQ_CTRL0 0x4A0 -#define IPQESS_REG_VQ_CTRL1 0x4A4 - -/* Virtual QID shift, it takes queue as input, and computes - * Virtual QID position in virtual qid control register - */ -#define IPQESS_VQ_ID_SHIFT(i) (((i) * 3) % 24) - -/* Virtual Queue Default Value */ -#define IPQESS_VQ_REG_VALUE 0x240240 - -/* Tx side Port Interface Control Register */ -#define IPQESS_REG_PORT_CTRL 0x4A8 -#define IPQESS_PAD_EN_SHIFT 15 - -/* Tx side VLAN Configuration Register */ -#define IPQESS_REG_VLAN_CFG 0x4AC - -#define IPQESS_VLAN_CFG_SVLAN_TPID_SHIFT 0 -#define IPQESS_VLAN_CFG_SVLAN_TPID_MASK 0xffff -#define IPQESS_VLAN_CFG_CVLAN_TPID_SHIFT 16 -#define IPQESS_VLAN_CFG_CVLAN_TPID_MASK 0xffff - -#define IPQESS_TX_CVLAN 16 -#define IPQESS_TX_INS_CVLAN 17 -#define IPQESS_TX_CVLAN_TAG_SHIFT 0 - -#define IPQESS_TX_SVLAN 14 -#define IPQESS_TX_INS_SVLAN 15 -#define IPQESS_TX_SVLAN_TAG_SHIFT 16 - -/* Tx Queue Packet Statistic Register */ -#define IPQESS_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */ - -#define IPQESS_TX_STAT_PKT_MASK 0xFFFFFF - -/* Tx Queue Byte Statistic Register */ -#define IPQESS_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */ - -/* Load Balance Based Ring Offset Register */ -#define IPQESS_REG_LB_RING 0x800 -#define IPQESS_LB_RING_ENTRY_MASK 0xff -#define IPQESS_LB_RING_ID_MASK 0x7 -#define IPQESS_LB_RING_PROFILE_ID_MASK 0x3 -#define IPQESS_LB_RING_ENTRY_BIT_OFFSET 8 -#define IPQESS_LB_RING_ID_OFFSET 0 -#define IPQESS_LB_RING_PROFILE_ID_OFFSET 3 -#define IPQESS_LB_REG_VALUE 0x6040200 - -/* Load Balance Priority Mapping Register */ -#define IPQESS_REG_LB_PRI_START 0x804 -#define IPQESS_REG_LB_PRI_END 0x810 -#define IPQESS_LB_PRI_REG_INC 4 -#define IPQESS_LB_PRI_ENTRY_BIT_OFFSET 4 -#define IPQESS_LB_PRI_ENTRY_MASK 0xf - -/* RSS Priority Mapping Register */ -#define IPQESS_REG_RSS_PRI 0x820 -#define IPQESS_RSS_PRI_ENTRY_MASK 0xf -#define IPQESS_RSS_RING_ID_MASK 0x7 -#define IPQESS_RSS_PRI_ENTRY_BIT_OFFSET 4 - -/* RSS Indirection Register */ -#define IPQESS_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */ -#define IPQESS_NUM_IDT 16 -#define IPQESS_RSS_IDT_VALUE 0x64206420 - -/* Default RSS Ring Register */ -#define IPQESS_REG_DEF_RSS 0x890 -#define IPQESS_DEF_RSS_MASK 0x7 - -/* RSS Hash Function Type Register */ -#define IPQESS_REG_RSS_TYPE 0x894 -#define IPQESS_RSS_TYPE_NONE 0x01 -#define IPQESS_RSS_TYPE_IPV4TCP 0x02 -#define IPQESS_RSS_TYPE_IPV6_TCP 0x04 -#define IPQESS_RSS_TYPE_IPV4_UDP 0x08 -#define IPQESS_RSS_TYPE_IPV6UDP 0x10 -#define IPQESS_RSS_TYPE_IPV4 0x20 -#define IPQESS_RSS_TYPE_IPV6 0x40 -#define IPQESS_RSS_HASH_MODE_MASK 0x7f - -#define IPQESS_REG_RSS_HASH_VALUE 0x8C0 - -#define IPQESS_REG_RSS_TYPE_RESULT 0x8C4 - -#define IPQESS_HASH_TYPE_START 0 -#define IPQESS_HASH_TYPE_END 5 -#define IPQESS_HASH_TYPE_SHIFT 12 - -#define IPQESS_RFS_FLOW_ENTRIES 1024 -#define IPQESS_RFS_FLOW_ENTRIES_MASK (IPQESS_RFS_FLOW_ENTRIES - 1) -#define IPQESS_RFS_EXPIRE_COUNT_PER_CALL 128 - -/* RFD Base Address Register */ -#define IPQESS_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */ - -/* RFD Index Register */ -#define IPQESS_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2)) /* x = queue id */ - -#define IPQESS_RFD_PROD_IDX_BITS 0x00000FFF -#define IPQESS_RFD_CONS_IDX_BITS 0x0FFF0000 -#define IPQESS_RFD_PROD_IDX_MASK 0xFFF -#define IPQESS_RFD_CONS_IDX_MASK 0xFFF -#define IPQESS_RFD_PROD_IDX_SHIFT 0 -#define IPQESS_RFD_CONS_IDX_SHIFT 16 - -/* Rx Descriptor Control Register */ -#define IPQESS_REG_RX_DESC0 0xA10 -#define IPQESS_RFD_RING_SIZE_MASK 0xFFF -#define IPQESS_RX_BUF_SIZE_MASK 0xFFFF -#define IPQESS_RFD_RING_SIZE_SHIFT 0 -#define IPQESS_RX_BUF_SIZE_SHIFT 16 - -#define IPQESS_REG_RX_DESC1 0xA14 -#define IPQESS_RXQ_RFD_BURST_NUM_MASK 0x3F -#define IPQESS_RXQ_RFD_PF_THRESH_MASK 0x1F -#define IPQESS_RXQ_RFD_LOW_THRESH_MASK 0xFFF -#define IPQESS_RXQ_RFD_BURST_NUM_SHIFT 0 -#define IPQESS_RXQ_RFD_PF_THRESH_SHIFT 8 -#define IPQESS_RXQ_RFD_LOW_THRESH_SHIFT 16 - -/* RXQ Control Register */ -#define IPQESS_REG_RXQ_CTRL 0xA18 -#define IPQESS_FIFO_THRESH_TYPE_SHIF 0 -#define IPQESS_FIFO_THRESH_128_BYTE 0x0 -#define IPQESS_FIFO_THRESH_64_BYTE 0x1 -#define IPQESS_RXQ_CTRL_RMV_VLAN 0x00000002 -#define IPQESS_RXQ_CTRL_EN_MASK GENMASK(15, 8) -#define IPQESS_RXQ_CTRL_EN(__qid) BIT(8 + (__qid)) - -/* AXI Burst Size Config */ -#define IPQESS_REG_AXIW_CTRL_MAXWRSIZE 0xA1C -#define IPQESS_AXIW_MAXWRSIZE_VALUE 0x0 - -/* Rx Statistics Register */ -#define IPQESS_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */ -#define IPQESS_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */ - -/* WoL Pattern Length Register */ -#define IPQESS_REG_WOL_PATTERN_LEN0 0xC00 -#define IPQESS_WOL_PT_LEN_MASK 0xFF -#define IPQESS_WOL_PT0_LEN_SHIFT 0 -#define IPQESS_WOL_PT1_LEN_SHIFT 8 -#define IPQESS_WOL_PT2_LEN_SHIFT 16 -#define IPQESS_WOL_PT3_LEN_SHIFT 24 - -#define IPQESS_REG_WOL_PATTERN_LEN1 0xC04 -#define IPQESS_WOL_PT4_LEN_SHIFT 0 -#define IPQESS_WOL_PT5_LEN_SHIFT 8 -#define IPQESS_WOL_PT6_LEN_SHIFT 16 - -/* WoL Control Register */ -#define IPQESS_REG_WOL_CTRL 0xC08 -#define IPQESS_WOL_WK_EN 0x00000001 -#define IPQESS_WOL_MG_EN 0x00000002 -#define IPQESS_WOL_PT0_EN 0x00000004 -#define IPQESS_WOL_PT1_EN 0x00000008 -#define IPQESS_WOL_PT2_EN 0x00000010 -#define IPQESS_WOL_PT3_EN 0x00000020 -#define IPQESS_WOL_PT4_EN 0x00000040 -#define IPQESS_WOL_PT5_EN 0x00000080 -#define IPQESS_WOL_PT6_EN 0x00000100 - -/* MAC Control Register */ -#define IPQESS_REG_MAC_CTRL0 0xC20 -#define IPQESS_REG_MAC_CTRL1 0xC24 - -/* WoL Pattern Register */ -#define IPQESS_REG_WOL_PATTERN_START 0x5000 -#define IPQESS_PATTERN_PART_REG_OFFSET 0x40 - - -/* TX descriptor fields */ -#define IPQESS_TPD_HDR_SHIFT 0 -#define IPQESS_TPD_PPPOE_EN 0x00000100 -#define IPQESS_TPD_IP_CSUM_EN 0x00000200 -#define IPQESS_TPD_TCP_CSUM_EN 0x0000400 -#define IPQESS_TPD_UDP_CSUM_EN 0x00000800 -#define IPQESS_TPD_CUSTOM_CSUM_EN 0x00000C00 -#define IPQESS_TPD_LSO_EN 0x00001000 -#define IPQESS_TPD_LSO_V2_EN 0x00002000 -/* The VLAN_TAGGED bit is not used in the publicly available - * drivers. The definition has been stolen from the Atheros - * 'alx' driver (drivers/net/ethernet/atheros/alx/hw.h). It - * seems that it has the same meaning in regard to the EDMA - * hardware. - */ -#define IPQESS_TPD_VLAN_TAGGED 0x00004000 -#define IPQESS_TPD_IPV4_EN 0x00010000 -#define IPQESS_TPD_MSS_MASK 0x1FFF -#define IPQESS_TPD_MSS_SHIFT 18 -#define IPQESS_TPD_CUSTOM_CSUM_SHIFT 18 - -/* RRD descriptor fields */ -#define IPQESS_RRD_NUM_RFD_MASK 0x000F -#define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF -#define IPQESS_RRD_SRC_PORT_NUM_MASK 0x4000 -#define IPQESS_RRD_SVLAN 0x8000 -#define IPQESS_RRD_FLOW_COOKIE_MASK 0x07FF; - -#define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF -#define IPQESS_RRD_CSUM_FAIL_MASK 0xC000 -#define IPQESS_RRD_CVLAN 0x0001 -#define IPQESS_RRD_DESC_VALID 0x8000 - -#define IPQESS_RRD_PRIORITY_SHIFT 4 -#define IPQESS_RRD_PRIORITY_MASK 0x7 -#define IPQESS_RRD_PORT_TYPE_SHIFT 7 -#define IPQESS_RRD_PORT_TYPE_MASK 0x1F - -#endif diff --git a/target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess_ethtool.c b/target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess_ethtool.c deleted file mode 100644 index da5fb4deed8..00000000000 --- a/target/linux/ipq40xx/files-5.15/drivers/net/ethernet/qualcomm/ipqess/ipqess_ethtool.c +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR ISC) -/* Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved. - * Copyright (c) 2017 - 2018, John Crispin - * - * Permission to use, copy, modify, and/or distribute this software for - * any purpose with or without fee is hereby granted, provided that the - * above copyright notice and this permission notice appear in all copies. - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT - * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include -#include -#include -#include - -#include "ipqess.h" - -struct ipqesstool_stats { - uint8_t string[ETH_GSTRING_LEN]; - uint32_t offset; -}; - -#define IPQESS_STAT(m) offsetof(struct ipqesstool_statistics, m) -#define DRVINFO_LEN 32 - -static const struct ipqesstool_stats ipqess_stats[] = { - {"tx_q0_pkt", IPQESS_STAT(tx_q0_pkt)}, - {"tx_q1_pkt", IPQESS_STAT(tx_q1_pkt)}, - {"tx_q2_pkt", IPQESS_STAT(tx_q2_pkt)}, - {"tx_q3_pkt", IPQESS_STAT(tx_q3_pkt)}, - {"tx_q4_pkt", IPQESS_STAT(tx_q4_pkt)}, - {"tx_q5_pkt", IPQESS_STAT(tx_q5_pkt)}, - {"tx_q6_pkt", IPQESS_STAT(tx_q6_pkt)}, - {"tx_q7_pkt", IPQESS_STAT(tx_q7_pkt)}, - {"tx_q8_pkt", IPQESS_STAT(tx_q8_pkt)}, - {"tx_q9_pkt", IPQESS_STAT(tx_q9_pkt)}, - {"tx_q10_pkt", IPQESS_STAT(tx_q10_pkt)}, - {"tx_q11_pkt", IPQESS_STAT(tx_q11_pkt)}, - {"tx_q12_pkt", IPQESS_STAT(tx_q12_pkt)}, - {"tx_q13_pkt", IPQESS_STAT(tx_q13_pkt)}, - {"tx_q14_pkt", IPQESS_STAT(tx_q14_pkt)}, - {"tx_q15_pkt", IPQESS_STAT(tx_q15_pkt)}, - {"tx_q0_byte", IPQESS_STAT(tx_q0_byte)}, - {"tx_q1_byte", IPQESS_STAT(tx_q1_byte)}, - {"tx_q2_byte", IPQESS_STAT(tx_q2_byte)}, - {"tx_q3_byte", IPQESS_STAT(tx_q3_byte)}, - {"tx_q4_byte", IPQESS_STAT(tx_q4_byte)}, - {"tx_q5_byte", IPQESS_STAT(tx_q5_byte)}, - {"tx_q6_byte", IPQESS_STAT(tx_q6_byte)}, - {"tx_q7_byte", IPQESS_STAT(tx_q7_byte)}, - {"tx_q8_byte", IPQESS_STAT(tx_q8_byte)}, - {"tx_q9_byte", IPQESS_STAT(tx_q9_byte)}, - {"tx_q10_byte", IPQESS_STAT(tx_q10_byte)}, - {"tx_q11_byte", IPQESS_STAT(tx_q11_byte)}, - {"tx_q12_byte", IPQESS_STAT(tx_q12_byte)}, - {"tx_q13_byte", IPQESS_STAT(tx_q13_byte)}, - {"tx_q14_byte", IPQESS_STAT(tx_q14_byte)}, - {"tx_q15_byte", IPQESS_STAT(tx_q15_byte)}, - {"rx_q0_pkt", IPQESS_STAT(rx_q0_pkt)}, - {"rx_q1_pkt", IPQESS_STAT(rx_q1_pkt)}, - {"rx_q2_pkt", IPQESS_STAT(rx_q2_pkt)}, - {"rx_q3_pkt", IPQESS_STAT(rx_q3_pkt)}, - {"rx_q4_pkt", IPQESS_STAT(rx_q4_pkt)}, - {"rx_q5_pkt", IPQESS_STAT(rx_q5_pkt)}, - {"rx_q6_pkt", IPQESS_STAT(rx_q6_pkt)}, - {"rx_q7_pkt", IPQESS_STAT(rx_q7_pkt)}, - {"rx_q0_byte", IPQESS_STAT(rx_q0_byte)}, - {"rx_q1_byte", IPQESS_STAT(rx_q1_byte)}, - {"rx_q2_byte", IPQESS_STAT(rx_q2_byte)}, - {"rx_q3_byte", IPQESS_STAT(rx_q3_byte)}, - {"rx_q4_byte", IPQESS_STAT(rx_q4_byte)}, - {"rx_q5_byte", IPQESS_STAT(rx_q5_byte)}, - {"rx_q6_byte", IPQESS_STAT(rx_q6_byte)}, - {"rx_q7_byte", IPQESS_STAT(rx_q7_byte)}, - {"tx_desc_error", IPQESS_STAT(tx_desc_error)}, -}; - -static int ipqess_get_strset_count(struct net_device *netdev, int sset) -{ - switch (sset) { - case ETH_SS_STATS: - return ARRAY_SIZE(ipqess_stats); - default: - netdev_dbg(netdev, "%s: Invalid string set", __func__); - return -EOPNOTSUPP; - } -} - -static void ipqess_get_strings(struct net_device *netdev, uint32_t stringset, - uint8_t *data) -{ - uint8_t *p = data; - uint32_t i; - - switch (stringset) { - case ETH_SS_STATS: - for (i = 0; i < ARRAY_SIZE(ipqess_stats); i++) { - memcpy(p, ipqess_stats[i].string, - min((size_t)ETH_GSTRING_LEN, - strlen(ipqess_stats[i].string) + 1)); - p += ETH_GSTRING_LEN; - } - break; - } -} - -static void ipqess_get_ethtool_stats(struct net_device *netdev, - struct ethtool_stats *stats, - uint64_t *data) -{ - struct ipqess *ess = netdev_priv(netdev); - u32 *essstats = (u32 *)&ess->ipqessstats; - int i; - - spin_lock(&ess->stats_lock); - - ipqess_update_hw_stats(ess); - - for (i = 0; i < ARRAY_SIZE(ipqess_stats); i++) - data[i] = *(u32 *)(essstats + (ipqess_stats[i].offset / sizeof(u32))); - - spin_unlock(&ess->stats_lock); -} - -static void ipqess_get_drvinfo(struct net_device *dev, - struct ethtool_drvinfo *info) -{ - strlcpy(info->driver, "qca_ipqess", DRVINFO_LEN); - strlcpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN); -} - -static int ipqess_get_settings(struct net_device *netdev, - struct ethtool_link_ksettings *cmd) -{ - struct ipqess *ess = netdev_priv(netdev); - - return phylink_ethtool_ksettings_get(ess->phylink, cmd); -} - -static int ipqess_set_settings(struct net_device *netdev, - const struct ethtool_link_ksettings *cmd) -{ - struct ipqess *ess = netdev_priv(netdev); - - return phylink_ethtool_ksettings_set(ess->phylink, cmd); -} - -static void ipqess_get_ringparam(struct net_device *netdev, - struct ethtool_ringparam *ring) -{ - ring->tx_max_pending = IPQESS_TX_RING_SIZE; - ring->rx_max_pending = IPQESS_RX_RING_SIZE; -} - -static const struct ethtool_ops ipqesstool_ops = { - .get_drvinfo = &ipqess_get_drvinfo, - .get_link = ðtool_op_get_link, - .get_link_ksettings = &ipqess_get_settings, - .set_link_ksettings = &ipqess_set_settings, - .get_strings = &ipqess_get_strings, - .get_sset_count = &ipqess_get_strset_count, - .get_ethtool_stats = &ipqess_get_ethtool_stats, - .get_ringparam = ipqess_get_ringparam, -}; - -void ipqess_set_ethtool_ops(struct net_device *netdev) -{ - netdev->ethtool_ops = &ipqesstool_ops; -} diff --git a/target/linux/ipq40xx/patches-5.15/100-dt-bindings-clock-qcom-ipq4019-add-missing-networkin.patch b/target/linux/ipq40xx/patches-5.15/100-dt-bindings-clock-qcom-ipq4019-add-missing-networkin.patch deleted file mode 100644 index ae59005bba5..00000000000 --- a/target/linux/ipq40xx/patches-5.15/100-dt-bindings-clock-qcom-ipq4019-add-missing-networkin.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 53cac0823f86c39eb4b00e2c9a7b2483a4182008 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 14 Aug 2023 12:37:58 +0200 -Subject: [PATCH 1/2] dt-bindings: clock: qcom: ipq4019: add missing networking - resets - -Add bindings for the missing networking resets found in IPQ4019 GCC. - -Signed-off-by: Robert Marko ---- - include/dt-bindings/clock/qcom,gcc-ipq4019.h | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h -+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h -@@ -165,5 +165,11 @@ - #define GCC_QDSS_BCR 69 - #define GCC_MPM_BCR 70 - #define GCC_SPDM_BCR 71 -+#define ESS_MAC1_ARES 72 -+#define ESS_MAC2_ARES 73 -+#define ESS_MAC3_ARES 74 -+#define ESS_MAC4_ARES 75 -+#define ESS_MAC5_ARES 76 -+#define ESS_PSGMII_ARES 77 - - #endif diff --git a/target/linux/ipq40xx/patches-5.15/101-clk-qcom-gcc-ipq4019-add-missing-networking-resets.patch b/target/linux/ipq40xx/patches-5.15/101-clk-qcom-gcc-ipq4019-add-missing-networking-resets.patch deleted file mode 100644 index 42a2f341bea..00000000000 --- a/target/linux/ipq40xx/patches-5.15/101-clk-qcom-gcc-ipq4019-add-missing-networking-resets.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 6038ba75e2aa8e57d4eaf20a90c8061c43b1117f Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 14 Aug 2023 12:39:04 +0200 -Subject: [PATCH 2/2] clk: qcom: gcc-ipq4019: add missing networking resets - -IPQ4019 has more networking related resets that will be required for future -wired networking support, so lets add them. - -Signed-off-by: Robert Marko ---- - drivers/clk/qcom/gcc-ipq4019.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/clk/qcom/gcc-ipq4019.c -+++ b/drivers/clk/qcom/gcc-ipq4019.c -@@ -1707,6 +1707,12 @@ static const struct qcom_reset_map gcc_i - [GCC_TCSR_BCR] = {0x22000, 0}, - [GCC_MPM_BCR] = {0x24000, 0}, - [GCC_SPDM_BCR] = {0x25000, 0}, -+ [ESS_MAC1_ARES] = {0x1200C, 0}, -+ [ESS_MAC2_ARES] = {0x1200C, 1}, -+ [ESS_MAC3_ARES] = {0x1200C, 2}, -+ [ESS_MAC4_ARES] = {0x1200C, 3}, -+ [ESS_MAC5_ARES] = {0x1200C, 4}, -+ [ESS_PSGMII_ARES] = {0x1200C, 5}, - }; - - static const struct regmap_config gcc_ipq4019_regmap_config = { diff --git a/target/linux/ipq40xx/patches-5.15/104-clk-fix-apss-cpu-overclocking.patch b/target/linux/ipq40xx/patches-5.15/104-clk-fix-apss-cpu-overclocking.patch deleted file mode 100644 index 2de03f7ae0a..00000000000 --- a/target/linux/ipq40xx/patches-5.15/104-clk-fix-apss-cpu-overclocking.patch +++ /dev/null @@ -1,115 +0,0 @@ -From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sun, 11 Mar 2018 14:41:31 +0100 -Subject: [PATCH 2/2] clk: fix apss cpu overclocking - -There's an interaction issue between the clk changes:" -clk: qcom: ipq4019: Add the apss cpu pll divider clock node -clk: qcom: ipq4019: remove fixed clocks and add pll clocks -" and the cpufreq-dt. - -cpufreq-dt is now spamming the kernel-log with the following: - -[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP -for freq 761142857 (-34) - -This only happens on certain devices like the Compex WPJ428 -and AVM FritzBox!4040. However, other devices like the Asus -RT-AC58U and Meraki MR33 work just fine. - -The issue stem from the fact that all higher CPU-Clocks -are achieved by switching the clock-parent to the P_DDRPLLAPSS -(ddrpllapss). Which is set by Qualcomm's proprietary bootcode -as part of the DDR calibration. - -For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked -at round 533 MHz (ddrpllsdcc = 190285714 Hz). - -whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is -clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz). - -This patch attempts to fix the issue by modifying -clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate() -to use a new qcom_find_freq_close() function, which returns the closest -matching frequency, instead of the next higher. This way, the SoC in -the FB4040 (with its max clock speed of 710.4 MHz) will no longer -try to overclock to 761 MHz. - -Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node") -Signed-off-by: Christian Lamparter -Signed-off-by: John Crispin ---- - drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++--- - 1 file changed, 31 insertions(+), 3 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq4019.c -+++ b/drivers/clk/qcom/gcc-ipq4019.c -@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe - .reg = 0x2f020, - }; - -+ -+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f, -+ unsigned long rate) -+{ -+ const struct freq_tbl *last = NULL; -+ -+ for ( ; f->freq; f++) { -+ if (rate == f->freq) -+ return f; -+ -+ if (f->freq > rate) { -+ if (!last || -+ (f->freq - rate) < (rate - last->freq)) -+ return f; -+ else -+ return last; -+ } -+ last = f; -+ } -+ -+ return last; -+} -+ - /* - * Round rate function for APSS CPU PLL Clock divider. - * It looks up the frequency table and returns the next higher frequency -@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc - struct clk_hw *p_hw; - const struct freq_tbl *f; - -- f = qcom_find_freq(pll->freq_tbl, rate); -+ f = qcom_find_freq_close(pll->freq_tbl, rate); - if (!f) - return -EINVAL; - -@@ -1277,7 +1300,7 @@ static int clk_cpu_div_set_rate(struct c - const struct freq_tbl *f; - u32 mask; - -- f = qcom_find_freq(pll->freq_tbl, rate); -+ f = qcom_find_freq_close(pll->freq_tbl, rate); - if (!f) - return -EINVAL; - -@@ -1304,6 +1327,7 @@ static unsigned long - clk_cpu_div_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) - { -+ const struct freq_tbl *f; - struct clk_fepll *pll = to_clk_fepll(hw); - u32 cdiv, pre_div; - u64 rate; -@@ -1324,7 +1348,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h - rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2; - do_div(rate, pre_div); - -- return rate; -+ f = qcom_find_freq_close(pll->freq_tbl, rate); -+ if (!f) -+ return rate; -+ -+ return f->freq; - }; - - static const struct clk_ops clk_regmap_cpu_div_ops = { diff --git a/target/linux/ipq40xx/patches-5.15/301-arm-compressed-add-appended-DTB-section.patch b/target/linux/ipq40xx/patches-5.15/301-arm-compressed-add-appended-DTB-section.patch deleted file mode 100644 index 0448574e7e5..00000000000 --- a/target/linux/ipq40xx/patches-5.15/301-arm-compressed-add-appended-DTB-section.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 30 Oct 2020 13:36:31 +0100 -Subject: [PATCH] arm: compressed: add appended DTB section - -This adds a appended_dtb section to the ARM decompressor -linker script. - -This allows using the existing ARM zImage appended DTB support for -appending a DTB to the raw ELF kernel. - -Its size is set to 1MB max to match the zImage appended DTB size limit. - -To use it to pass the DTB to the kernel, objcopy is used: - -objcopy --set-section-flags=.appended_dtb=alloc,contents \ - --update-section=.appended_dtb=.dtb vmlinux - -This is based off the following patch: -https://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69 - -Signed-off-by: Robert Marko ---- - arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/compressed/vmlinux.lds.S -+++ b/arch/arm/boot/compressed/vmlinux.lds.S -@@ -103,6 +103,13 @@ SECTIONS - - _edata = .; - -+ .appended_dtb : { -+ /* leave space for appended DTB */ -+ . += 0x100000; -+ } -+ -+ _edata_dtb = .; -+ - /* - * The image_end section appears after any additional loadable sections - * that the linker may decide to insert in the binary image. Having -@@ -140,4 +147,4 @@ SECTIONS - - ARM_ASSERTS - } --ASSERT(_edata_real == _edata, "error: zImage file size is incorrect"); -+ASSERT(_edata_real == _edata_dtb, "error: zImage file size is incorrect"); diff --git a/target/linux/ipq40xx/patches-5.15/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch b/target/linux/ipq40xx/patches-5.15/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch deleted file mode 100644 index 51891c1f227..00000000000 --- a/target/linux/ipq40xx/patches-5.15/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001 -From: John Thomson -Date: Fri, 23 Oct 2020 19:42:36 +1000 -Subject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot - -For IPQ40XX systems where the SoC watchdog is activated before linux, -the watchdog timer may be too small for linux to finish uncompress, -boot, and watchdog management start. -If the watchdog is enabled, set the timeout for it to 30 seconds. -The functionality and offsets were copied from: -drivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start -The watchdog memory address was taken from: -arch/arm/boot/dts/qcom-ipq4019.dtsi - -This was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's -RouterBoot bootloader. - -Signed-off-by: John Thomson ---- - arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) - ---- a/arch/arm/boot/compressed/head.S -+++ b/arch/arm/boot/compressed/head.S -@@ -624,6 +624,41 @@ not_relocated: mov r0, #0 - bic r4, r4, #1 - blne cache_on - -+/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds -+ * if it is enabled, so that there is time for kernel -+ * to decompress, boot, and take over the watchdog. -+ * data and functionality from drivers/watchdog/qcom-wdt.c -+ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi -+ */ -+#ifdef CONFIG_ARCH_IPQ40XX -+watchdog_set: -+ /* offsets: -+ * 0x04 reset (=1 resets countdown) -+ * 0x08 enable (=0 disables) -+ * 0x0c status (=1 when SoC was reset by watchdog) -+ * 0x10 bark (=timeout warning in ticks) -+ * 0x14 bite (=timeout reset in ticks) -+ * clock rate is 1<<15 hertz -+ */ -+ .equ watchdog, 0x0b017000 @Store watchdog base address -+ movw r0, #:lower16:watchdog -+ movt r0, #:upper16:watchdog -+ ldr r1, [r0, #0x08] @Get enabled? -+ cmp r1, #1 @If not enabled, do not change -+ bne watchdog_finished -+ mov r1, #0 -+ str r1, [r0, #0x08] @Disable the watchdog -+ mov r1, #1 -+ str r1, [r0, #0x04] @Pet the watchdog -+ mov r1, #30 @30 seconds timeout -+ lsl r1, r1, #15 @converted to ticks -+ str r1, [r0, #0x10] @Set the bark timeout -+ str r1, [r0, #0x14] @Set the bite timeout -+ mov r1, #1 -+ str r1, [r0, #0x08] @Enable the watchdog -+watchdog_finished: -+#endif /* CONFIG_ARCH_IPQ40XX */ -+ - /* - * The C runtime environment should now be setup sufficiently. - * Set up some pointers, and start decompressing. diff --git a/target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch b/target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch deleted file mode 100644 index 3a3be91709e..00000000000 --- a/target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch +++ /dev/null @@ -1,24 +0,0 @@ -From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 14 Dec 2020 13:35:35 +0100 -Subject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock - -When using sdhci_msm_set_clock clock setting will fail, so lets -use the generic sdhci_set_clock. - -Signed-off-by: Robert Marko ---- - drivers/mmc/host/sdhci-msm.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mmc/host/sdhci-msm.c -+++ b/drivers/mmc/host/sdhci-msm.c -@@ -2447,7 +2447,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat - - static const struct sdhci_ops sdhci_msm_ops = { - .reset = sdhci_msm_reset, -- .set_clock = sdhci_msm_set_clock, -+ .set_clock = sdhci_set_clock, - .get_min_clock = sdhci_msm_get_min_clock, - .get_max_clock = sdhci_msm_get_max_clock, - .set_bus_width = sdhci_set_bus_width, diff --git a/target/linux/ipq40xx/patches-5.15/401-mmc-sdhci-msm-comment-unused-sdhci_msm_set_clock.patch b/target/linux/ipq40xx/patches-5.15/401-mmc-sdhci-msm-comment-unused-sdhci_msm_set_clock.patch deleted file mode 100644 index b297600171a..00000000000 --- a/target/linux/ipq40xx/patches-5.15/401-mmc-sdhci-msm-comment-unused-sdhci_msm_set_clock.patch +++ /dev/null @@ -1,108 +0,0 @@ -From 28edd829133766eb3cefaf2e49d3ee701968061b Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Tue, 9 May 2023 01:57:17 +0200 -Subject: [PATCH] mmc: sdhci-msm: comment unused sdhci_msm_set_clock - -comment unused sdhci_msm_set_clock and __sdhci_msm_set_clock as due to some -current problem, we are forced to use sdhci_set_clock. - -Signed-off-by: Christian Marangi ---- - drivers/mmc/host/sdhci-msm.c | 86 ++++++++++++++++++------------------ - 1 file changed, 43 insertions(+), 43 deletions(-) - ---- a/drivers/mmc/host/sdhci-msm.c -+++ b/drivers/mmc/host/sdhci-msm.c -@@ -1751,49 +1751,49 @@ static unsigned int sdhci_msm_get_min_cl - return SDHCI_MSM_MIN_CLOCK; - } - --/* -- * __sdhci_msm_set_clock - sdhci_msm clock control. -- * -- * Description: -- * MSM controller does not use internal divider and -- * instead directly control the GCC clock as per -- * HW recommendation. -- **/ --static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) --{ -- u16 clk; -- -- sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); -- -- if (clock == 0) -- return; -- -- /* -- * MSM controller do not use clock divider. -- * Thus read SDHCI_CLOCK_CONTROL and only enable -- * clock with no divider value programmed. -- */ -- clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); -- sdhci_enable_clk(host, clk); --} -- --/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */ --static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) --{ -- struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); -- struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); -- -- if (!clock) { -- host->mmc->actual_clock = msm_host->clk_rate = 0; -- goto out; -- } -- -- sdhci_msm_hc_select_mode(host); -- -- msm_set_clock_rate_for_bus_mode(host, clock); --out: -- __sdhci_msm_set_clock(host, clock); --} -+// /* -+// * __sdhci_msm_set_clock - sdhci_msm clock control. -+// * -+// * Description: -+// * MSM controller does not use internal divider and -+// * instead directly control the GCC clock as per -+// * HW recommendation. -+// **/ -+// static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) -+// { -+// u16 clk; -+ -+// sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); -+ -+// if (clock == 0) -+// return; -+ -+// /* -+// * MSM controller do not use clock divider. -+// * Thus read SDHCI_CLOCK_CONTROL and only enable -+// * clock with no divider value programmed. -+// */ -+// clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); -+// sdhci_enable_clk(host, clk); -+// } -+ -+// /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */ -+// static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) -+// { -+// struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); -+// struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); -+ -+// if (!clock) { -+// host->mmc->actual_clock = msm_host->clk_rate = 0; -+// goto out; -+// } -+ -+// sdhci_msm_hc_select_mode(host); -+ -+// msm_set_clock_rate_for_bus_mode(host, clock); -+// out: -+// __sdhci_msm_set_clock(host, clock); -+// } - - /*****************************************************************************\ - * * diff --git a/target/linux/ipq40xx/patches-5.15/420-firmware-qcom-scm-Add-SDI-disable-support.patch b/target/linux/ipq40xx/patches-5.15/420-firmware-qcom-scm-Add-SDI-disable-support.patch deleted file mode 100644 index e4ee745ff1c..00000000000 --- a/target/linux/ipq40xx/patches-5.15/420-firmware-qcom-scm-Add-SDI-disable-support.patch +++ /dev/null @@ -1,60 +0,0 @@ -From b514bc3c0a5a57bc83843dc66c72788b9c9435ac Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 18 May 2023 16:02:23 +0200 -Subject: [PATCH 1/3] firmware: qcom: scm: Add SDI disable support - -Some SoC-s like IPQ5018 require SDI(Secure Debug Image) to be disabled -before trying to reboot, otherwise board will just hang after reboot has -been issued via PSCI. - -So, provide a call to SCM that allows disabling it. - -Signed-off-by: Robert Marko -Acked-by: Mukesh Ojha ---- - drivers/firmware/qcom_scm.c | 23 +++++++++++++++++++++++ - drivers/firmware/qcom_scm.h | 1 + - 2 files changed, 24 insertions(+) - ---- a/drivers/firmware/qcom_scm.c -+++ b/drivers/firmware/qcom_scm.c -@@ -389,6 +389,29 @@ int qcom_scm_set_remote_state(u32 state, - } - EXPORT_SYMBOL(qcom_scm_set_remote_state); - -+static int qcom_scm_disable_sdi(void) -+{ -+ int ret; -+ struct qcom_scm_desc desc = { -+ .svc = QCOM_SCM_SVC_BOOT, -+ .cmd = QCOM_SCM_BOOT_SDI_CONFIG, -+ .args[0] = 1, /* Disable watchdog debug */ -+ .args[1] = 0, /* Disable SDI */ -+ .arginfo = QCOM_SCM_ARGS(2), -+ .owner = ARM_SMCCC_OWNER_SIP, -+ }; -+ struct qcom_scm_res res; -+ -+ ret = qcom_scm_clk_enable(); -+ if (ret) -+ return ret; -+ ret = qcom_scm_call(__scm->dev, &desc, &res); -+ -+ qcom_scm_clk_disable(); -+ -+ return ret ? : res.result[0]; -+} -+ - static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) - { - struct qcom_scm_desc desc = { ---- a/drivers/firmware/qcom_scm.h -+++ b/drivers/firmware/qcom_scm.h -@@ -77,6 +77,7 @@ extern int scm_legacy_call(struct device - #define QCOM_SCM_SVC_BOOT 0x01 - #define QCOM_SCM_BOOT_SET_ADDR 0x01 - #define QCOM_SCM_BOOT_TERMINATE_PC 0x02 -+#define QCOM_SCM_BOOT_SDI_CONFIG 0x09 - #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10 - #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a - #define QCOM_SCM_FLUSH_FLAG_MASK 0x3 diff --git a/target/linux/ipq40xx/patches-5.15/421-firmware-qcom-scm-disable-SDI-on-Google-WiFi.patch b/target/linux/ipq40xx/patches-5.15/421-firmware-qcom-scm-disable-SDI-on-Google-WiFi.patch deleted file mode 100644 index 98f02934a96..00000000000 --- a/target/linux/ipq40xx/patches-5.15/421-firmware-qcom-scm-disable-SDI-on-Google-WiFi.patch +++ /dev/null @@ -1,34 +0,0 @@ -From a658ad57c2b9d46eb5395c7bb8cf83b8e0f289e7 Mon Sep 17 00:00:00 2001 -From: Brian Norris -Date: Fri, 28 Jul 2023 12:02:19 +0200 -Subject: [PATCH 2/3] firmware: qcom: scm: disable SDI on Google WiFi - -Google WiFi seems to have SDI (Secure Debug Image) enabled by default which -prevents normal reboot from working causing the board to just hang after -reboot is called. - -So lets disable SDI during SCM probe on Google WiFi boards in order to -avoid a state where WDT will kick in and then the board will just hang -in the debug mode. - -Signed-off-by: Brian Norris ---- - drivers/firmware/qcom_scm.c | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/firmware/qcom_scm.c -+++ b/drivers/firmware/qcom_scm.c -@@ -1337,6 +1337,13 @@ static int qcom_scm_probe(struct platfor - if (download_mode) - qcom_scm_set_download_mode(true); - -+ /* -+ * Factory firmware leaves SDI (a debug interface), which prevents -+ * clean reboot. -+ */ -+ if (of_machine_is_compatible("google,wifi")) -+ qcom_scm_disable_sdi(); -+ - return 0; - } - diff --git a/target/linux/ipq40xx/patches-5.15/422-firmware-qcom-scm-fix-SCM-cold-boot-address.patch b/target/linux/ipq40xx/patches-5.15/422-firmware-qcom-scm-fix-SCM-cold-boot-address.patch deleted file mode 100644 index a31ea69e897..00000000000 --- a/target/linux/ipq40xx/patches-5.15/422-firmware-qcom-scm-fix-SCM-cold-boot-address.patch +++ /dev/null @@ -1,138 +0,0 @@ -From aaa675f07e781e248fcf169ce9a917b48bc2cc9b Mon Sep 17 00:00:00 2001 -From: Brian Norris -Date: Fri, 28 Jul 2023 12:06:23 +0200 -Subject: [PATCH 3/3] firmware: qcom: scm: fix SCM cold boot address - -This effectively reverts upstream Linux commit 13e77747800e ("firmware: -qcom: scm: Use atomic SCM for cold boot"), because Google WiFi boot -firmwares don't support the atomic variant. - -This fixes SMP support for Google WiFi. - -Signed-off-by: Brian Norris ---- - drivers/firmware/qcom_scm-legacy.c | 62 +++++++++++++++++++++++++----- - drivers/firmware/qcom_scm.c | 11 ++++++ - 2 files changed, 63 insertions(+), 10 deletions(-) - ---- a/drivers/firmware/qcom_scm-legacy.c -+++ b/drivers/firmware/qcom_scm-legacy.c -@@ -13,6 +13,9 @@ - #include - #include - -+#include -+#include -+ - #include "qcom_scm.h" - - static DEFINE_MUTEX(qcom_scm_lock); -@@ -117,6 +120,25 @@ static void __scm_legacy_do(const struct - } while (res->a0 == QCOM_SCM_INTERRUPTED); - } - -+static void qcom_scm_inv_range(unsigned long start, unsigned long end) -+{ -+ u32 cacheline_size, ctr; -+ -+ asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); -+ cacheline_size = 4 << ((ctr >> 16) & 0xf); -+ -+ start = round_down(start, cacheline_size); -+ end = round_up(end, cacheline_size); -+ outer_inv_range(start, end); -+ while (start < end) { -+ asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start) -+ : "memory"); -+ start += cacheline_size; -+ } -+ dsb(); -+ isb(); -+} -+ - /** - * scm_legacy_call() - Sends a command to the SCM and waits for the command to - * finish processing. -@@ -160,10 +182,16 @@ int scm_legacy_call(struct device *dev, - - rsp = scm_legacy_command_to_response(cmd); - -- cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE); -- if (dma_mapping_error(dev, cmd_phys)) { -- kfree(cmd); -- return -ENOMEM; -+ if (dev) { -+ cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE); -+ if (dma_mapping_error(dev, cmd_phys)) { -+ kfree(cmd); -+ return -ENOMEM; -+ } -+ } else { -+ cmd_phys = virt_to_phys(cmd); -+ __cpuc_flush_dcache_area(cmd, alloc_len); -+ outer_flush_range(cmd_phys, cmd_phys + alloc_len); - } - - smc.args[0] = 1; -@@ -179,13 +207,26 @@ int scm_legacy_call(struct device *dev, - goto out; - - do { -- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len, -- sizeof(*rsp), DMA_FROM_DEVICE); -+ if (dev) { -+ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + -+ cmd_len, sizeof(*rsp), -+ DMA_FROM_DEVICE); -+ } else { -+ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) + -+ cmd_len; -+ qcom_scm_inv_range(start, start + sizeof(*rsp)); -+ } - } while (!rsp->is_complete); - -- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len + -- le32_to_cpu(rsp->buf_offset), -- resp_len, DMA_FROM_DEVICE); -+ if (dev) { -+ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len + -+ le32_to_cpu(rsp->buf_offset), -+ resp_len, DMA_FROM_DEVICE); -+ } else { -+ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) + cmd_len + -+ le32_to_cpu(rsp->buf_offset); -+ qcom_scm_inv_range(start, start + resp_len); -+ } - - if (res) { - res_buf = scm_legacy_get_response_buffer(rsp); -@@ -193,7 +234,8 @@ int scm_legacy_call(struct device *dev, - res->result[i] = le32_to_cpu(res_buf[i]); - } - out: -- dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE); -+ if (dev) -+ dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE); - kfree(cmd); - return ret; - } ---- a/drivers/firmware/qcom_scm.c -+++ b/drivers/firmware/qcom_scm.c -@@ -344,6 +344,17 @@ int qcom_scm_set_cold_boot_addr(void *en - desc.args[0] = flags; - desc.args[1] = virt_to_phys(entry); - -+ /* -+ * Factory firmware doesn't support the atomic variant. Non-atomic SCMs -+ * require ugly DMA invalidation support that was dropped upstream a -+ * while ago. For more info, see: -+ * -+ * [RFC] qcom_scm: IPQ4019 firmware does not support atomic API? -+ * https://lore.kernel.org/linux-arm-msm/20200913201608.GA3162100@bDebian/ -+ */ -+ if (of_machine_is_compatible("google,wifi")) -+ return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL); -+ - return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); - } - EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr); diff --git a/target/linux/ipq40xx/patches-5.15/444-mtd-nand-rawnand-add-support-for-Toshiba-TC58NVG0S3H.patch b/target/linux/ipq40xx/patches-5.15/444-mtd-nand-rawnand-add-support-for-Toshiba-TC58NVG0S3H.patch deleted file mode 100644 index 91919b28948..00000000000 --- a/target/linux/ipq40xx/patches-5.15/444-mtd-nand-rawnand-add-support-for-Toshiba-TC58NVG0S3H.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 35ca7e3e6ccd120d694a3425f37fc6374ad2e11e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Andreas=20B=C3=B6hler?= -Date: Wed, 20 Apr 2022 12:08:38 +0200 -Subject: [PATCH] mtd: rawnand: add support for Toshiba TC58NVG0S3HTA00 - NAND flash -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The Toshiba TC58NVG0S3HTA00 is detected with 64 byte OOB while the flash -has 128 bytes OOB. This adds a static NAND ID entry to correct this. - -Tested on FRITZ!Box 7530 flashed with OpenWrt. - -Signed-off-by: Andreas Böhler -(changed id_len to 8, added comment about possible counterfeits) ---- ---- a/drivers/mtd/nand/raw/nand_ids.c -+++ b/drivers/mtd/nand/raw/nand_ids.c -@@ -29,6 +29,9 @@ struct nand_flash_dev nand_flash_ids[] = - {"TC58NVG0S3E 1G 3.3V 8-bit", - { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} }, - SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), }, -+ {"TC58NVG0S3HTA00 1G 3.3V 8-bit", /* possibly counterfeit chip - see commit */ -+ { .id = {0x98, 0xf1, 0x80, 0x15} }, /* should be more bytes */ -+ SZ_2K, SZ_128, SZ_128K, 0, 8, 128, NAND_ECC_INFO(8, SZ_512), }, - {"TC58NVG2S0F 4G 3.3V 8-bit", - { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} }, - SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) }, diff --git a/target/linux/ipq40xx/patches-5.15/700-skbuff-add-DSA-specific-data-to-struct-skb_shared_in.patch b/target/linux/ipq40xx/patches-5.15/700-skbuff-add-DSA-specific-data-to-struct-skb_shared_in.patch deleted file mode 100644 index 385364c076e..00000000000 --- a/target/linux/ipq40xx/patches-5.15/700-skbuff-add-DSA-specific-data-to-struct-skb_shared_in.patch +++ /dev/null @@ -1,43 +0,0 @@ -From da75807ac41175e9db8c95f7a172b4133763b744 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Mon, 11 Jan 2021 17:49:36 +0100 -Subject: [PATCH] skbuff: add DSA specific data to struct skb_shared_info - -All of the already existing DSA tagging protocol drivers -are storing the tagging data directly into the skb. In most -cases that is the only way to send the required information -to the underlying ethernet switch. - -However on certain platforms (like the Qualcomm IPQ40xx -SoCs) the built-in ethernet switch is connected directly -to an ethernet MAC, and the tagging information must be -sent out-of-band which is done directly via the hardware -TX descriptors of the ethernet MAC. - -In such cases, putting the information into the skb causes -unneccesary overhead, because the ethernet driver must -remove that before sending the ethernet frame towards to -the hardware. - -This change adds two new DSA specific fields to struct -skb_shared_info which makes it possible to send the -tagging information via skb->shinfo. With this approach, -the twofold modifications of the skb data can be avoided. - -Signed-off-by: Gabor Juhos ---- - include/linux/skbuff.h | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/include/linux/skbuff.h -+++ b/include/linux/skbuff.h -@@ -564,6 +564,9 @@ struct skb_shared_info { - unsigned int gso_type; - u32 tskey; - -+ unsigned int dsa_tag_proto; -+ unsigned char dsa_tag_data[8]; -+ - /* - * Warning : all fields before dataref are cleared in __alloc_skb() - */ diff --git a/target/linux/ipq40xx/patches-5.15/701-net-dsa-tag_ipq4019-add-shinfo-based-tagging-driver-.patch b/target/linux/ipq40xx/patches-5.15/701-net-dsa-tag_ipq4019-add-shinfo-based-tagging-driver-.patch deleted file mode 100644 index 74079d68a13..00000000000 --- a/target/linux/ipq40xx/patches-5.15/701-net-dsa-tag_ipq4019-add-shinfo-based-tagging-driver-.patch +++ /dev/null @@ -1,187 +0,0 @@ -From 29a0c2fae991cab142575c92276c0afdeb260ebe Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Thu, 28 Oct 2021 21:44:52 +0200 -Subject: [PATCH] net: dsa: tag_ipq4019: add shinfo based tagging driver for - IPQ40xx - -This change adds a tagging protocol driver for the built-in -ethernet switch of the Qualcomm Atheros IPQ4019 SoCs. - -In comparison to the existing tagging protocols this hardware -requires a slightly different approach because the switch does -not use in-band tags. - -On the receive path, the source port information is embedded -into the RX descriptors of the ethernet MAC hardware. Similarly, -the destination port mask must be sent via the TX descriptors -of the ethernet MAC when a packet is sent towards the switch. - -In order to support this special requirements, this patch -adds a new tagging protocol driver. - -The driver extracts the source port information directly -from the 'receive return descriptor' of the ethernet MAC. -It is possible because that descriptor is part of the skb -received from the ethernet driver. - -Unfortunatley, it is not possible to put the destination -port information directly to the TX descriptors, because -those are handled internally by the driver of the ethernet -hardware. - -To overcome this limitation, this tagging driver uses the -DSA specific fields in skb->shinfo to send the destination -port information to the ethernet driver. - -A similar tagging driver is exist but that uses skb -extensions which causes unnecessary overhead. - -Signed-off-by: Gabor Juhos ---- - include/linux/dsa/ipq4019.h | 11 ++++++ - include/net/dsa.h | 2 + - net/dsa/Kconfig | 6 +++ - net/dsa/Makefile | 1 + - net/dsa/tag_ipq4019.c | 79 +++++++++++++++++++++++++++++++++++++ - 5 files changed, 99 insertions(+) - create mode 100644 include/linux/dsa/ipq4019.h - create mode 100644 net/dsa/tag_ipq4019.c - ---- /dev/null -+++ b/include/linux/dsa/ipq4019.h -@@ -0,0 +1,11 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+ -+#ifndef DSA_IPQ40XX_H -+#define DSA_IPQ40XX_H -+ -+struct ipq40xx_dsa_tag_data { -+ u8 from_cpu; -+ u8 dp; -+}; -+ -+#endif /* DSA_IPQ40XX_H */ ---- a/include/net/dsa.h -+++ b/include/net/dsa.h -@@ -51,6 +51,7 @@ struct phylink_link_state; - #define DSA_TAG_PROTO_SEVILLE_VALUE 21 - #define DSA_TAG_PROTO_BRCM_LEGACY_VALUE 22 - #define DSA_TAG_PROTO_SJA1110_VALUE 23 -+#define DSA_TAG_PROTO_IPQ4019_VALUE 24 - - enum dsa_tag_protocol { - DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE, -@@ -77,6 +78,7 @@ enum dsa_tag_protocol { - DSA_TAG_PROTO_OCELOT_8021Q = DSA_TAG_PROTO_OCELOT_8021Q_VALUE, - DSA_TAG_PROTO_SEVILLE = DSA_TAG_PROTO_SEVILLE_VALUE, - DSA_TAG_PROTO_SJA1110 = DSA_TAG_PROTO_SJA1110_VALUE, -+ DSA_TAG_PROTO_IPQ4019 = DSA_TAG_PROTO_IPQ4019_VALUE, - }; - - struct dsa_switch; ---- a/net/dsa/Kconfig -+++ b/net/dsa/Kconfig -@@ -57,6 +57,12 @@ config NET_DSA_TAG_HELLCREEK - Say Y or M if you want to enable support for tagging frames - for the Hirschmann Hellcreek TSN switches. - -+config NET_DSA_TAG_IPQ4019 -+ tristate "Tag driver for Qualcomm Atheros IPQ4019 SoC built-in switch" -+ help -+ Say Y or M if you want to enable support for tagging frames for -+ the built-in switch of the Qualcomm Atheros IPQ4019 SoC-s. -+ - config NET_DSA_TAG_GSWIP - tristate "Tag driver for Lantiq / Intel GSWIP switches" - help ---- a/net/dsa/Makefile -+++ b/net/dsa/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_NET_DSA_TAG_AR9331) += tag_ - obj-$(CONFIG_NET_DSA_TAG_BRCM_COMMON) += tag_brcm.o - obj-$(CONFIG_NET_DSA_TAG_DSA_COMMON) += tag_dsa.o - obj-$(CONFIG_NET_DSA_TAG_GSWIP) += tag_gswip.o -+obj-$(CONFIG_NET_DSA_TAG_IPQ4019) += tag_ipq4019.o - obj-$(CONFIG_NET_DSA_TAG_HELLCREEK) += tag_hellcreek.o - obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o - obj-$(CONFIG_NET_DSA_TAG_RTL4_A) += tag_rtl4_a.o ---- /dev/null -+++ b/net/dsa/tag_ipq4019.c -@@ -0,0 +1,78 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+/* Copyright (c) 2021, Gabor Juhos */ -+ -+#include -+#include -+ -+#include "dsa_priv.h" -+ -+/* Receive Return Descriptor */ -+struct edma_rrd { -+ u16 rrd0; -+ u16 rrd1; -+ u16 rrd2; -+ u16 rrd3; -+ u16 rrd4; -+ u16 rrd5; -+ u16 rrd6; -+ u16 rrd7; -+} __packed; -+ -+#define EDMA_RRD_SIZE sizeof(struct edma_rrd) -+ -+#define EDMA_RRD1_PORT_ID_MASK GENMASK(14, 12) -+ -+static struct sk_buff *ipq4019_sh_tag_xmit(struct sk_buff *skb, -+ struct net_device *dev) -+{ -+ struct dsa_port *dp = dsa_slave_to_port(dev); -+ struct ipq40xx_dsa_tag_data *tag_data; -+ -+ BUILD_BUG_ON(sizeof_field(struct skb_shared_info, dsa_tag_data) < -+ sizeof(struct ipq40xx_dsa_tag_data)); -+ -+ skb_shinfo(skb)->dsa_tag_proto = DSA_TAG_PROTO_IPQ4019; -+ tag_data = (struct ipq40xx_dsa_tag_data *)skb_shinfo(skb)->dsa_tag_data; -+ -+ tag_data->from_cpu = 1; -+ /* set the destination port information */ -+ tag_data->dp = BIT(dp->index); -+ -+ return skb; -+} -+ -+static struct sk_buff *ipq4019_sh_tag_rcv(struct sk_buff *skb, -+ struct net_device *dev) -+{ -+ struct edma_rrd *rrd; -+ int offset; -+ int port; -+ -+ offset = EDMA_RRD_SIZE + ETH_HLEN; -+ if (unlikely(skb_headroom(skb) < offset)) -+ return NULL; -+ -+ rrd = (struct edma_rrd *)(skb->data - offset); -+ port = FIELD_GET(EDMA_RRD1_PORT_ID_MASK, rrd->rrd1); -+ -+ skb->dev = dsa_master_find_slave(dev, 0, port); -+ if (!skb->dev) -+ return NULL; -+ -+ return skb; -+} -+ -+const struct dsa_device_ops ipq4019_sh_tag_dsa_ops = { -+ .name = "ipq4019-sh", -+ .proto = DSA_TAG_PROTO_IPQ4019, -+ .xmit = ipq4019_sh_tag_xmit, -+ .rcv = ipq4019_sh_tag_rcv, -+}; -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_DESCRIPTION("DSA tag driver for the IPQ4019 SoC built-in ethernet switch"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_IPQ4019); -+ -+module_dsa_tag_driver(ipq4019_sh_tag_dsa_ops); diff --git a/target/linux/ipq40xx/patches-5.15/702-net-ethernet-qualcomm-add-IPQESS-support.patch b/target/linux/ipq40xx/patches-5.15/702-net-ethernet-qualcomm-add-IPQESS-support.patch deleted file mode 100644 index 72e9345118e..00000000000 --- a/target/linux/ipq40xx/patches-5.15/702-net-ethernet-qualcomm-add-IPQESS-support.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 4f488235f498db43f2412116dea6e02c7fb20216 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 1 Nov 2021 12:36:51 +0100 -Subject: [PATCH] net: ethernet: qualcomm: add IPQESS support - -Allow compiling the IPQESS driver that supports the -Qualcomm IPQ40xx SoC built-in ethernet controller. - -Signed-off-by: Robert Marko ---- - drivers/net/ethernet/qualcomm/Kconfig | 11 +++++++++++ - drivers/net/ethernet/qualcomm/Makefile | 1 + - 2 files changed, 12 insertions(+) - ---- a/drivers/net/ethernet/qualcomm/Kconfig -+++ b/drivers/net/ethernet/qualcomm/Kconfig -@@ -60,6 +60,17 @@ config QCOM_EMAC - low power, Receive-Side Scaling (RSS), and IEEE 1588-2008 - Precision Clock Synchronization Protocol. - -+config QCOM_IPQ4019_ESS_EDMA -+ tristate "Qualcomm Atheros IPQ4019 ESS EDMA support" -+ depends on OF -+ select PHYLINK -+ help -+ This driver supports the Qualcomm Atheros IPQ40xx built-in -+ ESS EDMA ethernet controller. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called ipqess. -+ - source "drivers/net/ethernet/qualcomm/rmnet/Kconfig" - - endif # NET_VENDOR_QUALCOMM ---- a/drivers/net/ethernet/qualcomm/Makefile -+++ b/drivers/net/ethernet/qualcomm/Makefile -@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o - qcauart-objs := qca_uart.o - - obj-y += emac/ -+obj-y += ipqess/ - - obj-$(CONFIG_RMNET) += rmnet/ diff --git a/target/linux/ipq40xx/patches-5.15/703-arm-dts-ipq4019-add-ethernet-controller-DT-node.patch b/target/linux/ipq40xx/patches-5.15/703-arm-dts-ipq4019-add-ethernet-controller-DT-node.patch deleted file mode 100644 index 68fb4eb4cee..00000000000 --- a/target/linux/ipq40xx/patches-5.15/703-arm-dts-ipq4019-add-ethernet-controller-DT-node.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 44327d7098d4f32c24ec8c528e5aff6e030956bc Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 20 Oct 2021 13:21:45 +0200 -Subject: [PATCH] arm: dts: ipq4019: add ethernet controller DT node - -Since IPQ40xx SoC built-in ethernet controller now has a driver, -add its DT node so it can be used. - -Signed-off-by: Robert Marko ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++ - 1 file changed, 48 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -38,6 +38,7 @@ - spi1 = &blsp1_spi2; - i2c0 = &blsp1_i2c3; - i2c1 = &blsp1_i2c4; -+ ethernet0 = &gmac; - }; - - cpus { -@@ -589,6 +590,57 @@ - status = "disabled"; - }; - -+ gmac: ethernet@c080000 { -+ compatible = "qcom,ipq4019-ess-edma"; -+ reg = <0xc080000 0x8000>; -+ resets = <&gcc ESS_RESET>; -+ reset-names = "ess_rst"; -+ clocks = <&gcc GCC_ESS_CLK>; -+ clock-names = "ess_clk"; -+ interrupts = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ -+ status = "disabled"; -+ -+ phy-mode = "internal"; -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ pause; -+ asym-pause; -+ }; -+ }; -+ - mdio: mdio@90000 { - #address-cells = <1>; - #size-cells = <0>; diff --git a/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch b/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch deleted file mode 100644 index ed5b7b60fb9..00000000000 --- a/target/linux/ipq40xx/patches-5.15/704-net-phy-define-PSGMII-PHY-interface-mode.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 157ac9f52fd9b9a22cf12f7755a905fb34ef72f7 Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Fri, 25 Dec 2020 08:02:47 +0100 -Subject: [PATCH] net: phy: define PSGMII PHY interface mode - -The PSGMII interface is similar to QSGMII. The main difference -is that the PSGMII interface combines five SGMII lines into a -single link while in QSGMII only four lines are combined. - -Similarly to the QSGMII, this interface mode might also needs -special handling within the MAC driver. - -Add definitions for the PHY layer to allow to express this type -of connection between the MAC and PHY. - -Signed-off-by: Gabor Juhos ---- - Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 + - drivers/net/phy/phylink.c | 2 ++ - include/linux/phy.h | 3 +++ - 3 files changed, 6 insertions(+) - ---- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml -+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml -@@ -64,6 +64,7 @@ properties: - - mii - - gmii - - sgmii -+ - psgmii - - qsgmii - - tbi - - rev-mii ---- a/drivers/net/phy/phylink.c -+++ b/drivers/net/phy/phylink.c -@@ -371,6 +371,7 @@ void phylink_get_linkmodes(unsigned long - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII: -+ case PHY_INTERFACE_MODE_PSGMII: - case PHY_INTERFACE_MODE_QSGMII: - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_GMII: -@@ -634,6 +635,7 @@ static int phylink_parse_mode(struct phy - - switch (pl->link_config.interface) { - case PHY_INTERFACE_MODE_SGMII: -+ case PHY_INTERFACE_MODE_PSGMII: - case PHY_INTERFACE_MODE_QSGMII: - phylink_set(pl->supported, 10baseT_Half); - phylink_set(pl->supported, 10baseT_Full); ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -139,6 +139,7 @@ typedef enum { - PHY_INTERFACE_MODE_XGMII, - PHY_INTERFACE_MODE_XLGMII, - PHY_INTERFACE_MODE_MOCA, -+ PHY_INTERFACE_MODE_PSGMII, - PHY_INTERFACE_MODE_QSGMII, - PHY_INTERFACE_MODE_TRGMII, - PHY_INTERFACE_MODE_100BASEX, -@@ -244,6 +245,8 @@ static inline const char *phy_modes(phy_ - return "xlgmii"; - case PHY_INTERFACE_MODE_MOCA: - return "moca"; -+ case PHY_INTERFACE_MODE_PSGMII: -+ return "psgmii"; - case PHY_INTERFACE_MODE_QSGMII: - return "qsgmii"; - case PHY_INTERFACE_MODE_TRGMII: diff --git a/target/linux/ipq40xx/patches-5.15/705-net-dsa-add-Qualcomm-IPQ4019-built-in-switch-support.patch b/target/linux/ipq40xx/patches-5.15/705-net-dsa-add-Qualcomm-IPQ4019-built-in-switch-support.patch deleted file mode 100644 index 13b169e576c..00000000000 --- a/target/linux/ipq40xx/patches-5.15/705-net-dsa-add-Qualcomm-IPQ4019-built-in-switch-support.patch +++ /dev/null @@ -1,57 +0,0 @@ -From b5f71652b85a85ea53162e9e2b760b84fd0d254f Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 1 Nov 2021 18:10:28 +0100 -Subject: [PATCH] net: dsa: add Qualcomm IPQ4019 built-in switch support - -Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in. - -It shares most of the stuff with its external counterpart, however it is -modified for the SoC. -Namely, it doesn't have second CPU port (Port 6), so it has 6 ports -instead of 7. -It also has no built-in PHY-s but rather requires external PSGMII based -companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry -out calibration before using them. -PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which -unfortunately requires some magic values as the datasheet doesnt document -the bits that are being set or the register at all. - -Since its built-in it is MMIO like other peripherals and doesn't have its -own MDIO bus but depends on the SoC provided one. - -CPU connection is at Port 0 and it uses some kind of a internal connection -and no traditional RGMII/SGMII. -It also doesn't use in-band tagging like other qca8k switches so a shinfo -based tagger is used. - -Signed-off-by: Robert Marko ---- - drivers/net/dsa/qca/Kconfig | 9 +++++++++ - drivers/net/dsa/qca/Makefile | 1 + - 2 files changed, 10 insertions(+) - ---- a/drivers/net/dsa/qca/Kconfig -+++ b/drivers/net/dsa/qca/Kconfig -@@ -23,3 +23,13 @@ config NET_DSA_QCA8K_LEDS_SUPPORT - help - This enabled support for LEDs present on the Qualcomm Atheros - QCA8K Ethernet switch chips. -+ -+config NET_DSA_QCA8K_IPQ4019 -+ tristate "Qualcomm Atheros IPQ4019 built-in Ethernet switch support" -+ depends on HAS_IOMEM && NET_DSA -+ select NET_DSA_TAG_IPQ4019 -+ select REGMAP -+ help -+ This enables support for the Qualcomm Atheros IPQ4019 SoC built-in -+ Ethernet switch. -+ ---- a/drivers/net/dsa/qca/Makefile -+++ b/drivers/net/dsa/qca/Makefile -@@ -1,5 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0-only - obj-$(CONFIG_NET_DSA_AR9331) += ar9331.o -+obj-$(CONFIG_NET_DSA_QCA8K_IPQ4019) += qca8k-ipq4019.o - obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o - qca8k-y += qca8k-common.o qca8k-8xxx.o - ifdef CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT diff --git a/target/linux/ipq40xx/patches-5.15/706-arm-dts-ipq4019-add-switch-node.patch b/target/linux/ipq40xx/patches-5.15/706-arm-dts-ipq4019-add-switch-node.patch deleted file mode 100644 index a231c7331bf..00000000000 --- a/target/linux/ipq40xx/patches-5.15/706-arm-dts-ipq4019-add-switch-node.patch +++ /dev/null @@ -1,98 +0,0 @@ -From ebb62523990a27b3a25e422fa575619f7f725a20 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 1 Nov 2021 18:15:04 +0100 -Subject: [PATCH] arm: dts: ipq4019: add switch node - -Since the built-in IPQ40xx switch now has a driver, add the required node -for it to work. - -Signed-off-by: Robert Marko ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 78 +++++++++++++++++++++++++++++ - 1 file changed, 78 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -590,6 +590,82 @@ - status = "disabled"; - }; - -+ switch: switch@c000000 { -+ compatible = "qca,ipq4019-qca8337n"; -+ reg = <0xc000000 0x80000>, <0x98000 0x800>; -+ reg-names = "base", "psgmii_phy"; -+ resets = <&gcc ESS_PSGMII_ARES>; -+ reset-names = "psgmii_rst"; -+ mdio = <&mdio>; -+ psgmii-ethphy = <&psgmiiphy>; -+ -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { /* MAC0 */ -+ reg = <0>; -+ label = "cpu"; -+ ethernet = <&gmac>; -+ phy-mode = "internal"; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ pause; -+ asym-pause; -+ }; -+ }; -+ -+ swport1: port@1 { /* MAC1 */ -+ reg = <1>; -+ label = "lan1"; -+ phy-handle = <ðphy0>; -+ phy-mode = "psgmii"; -+ -+ status = "disabled"; -+ }; -+ -+ swport2: port@2 { /* MAC2 */ -+ reg = <2>; -+ label = "lan2"; -+ phy-handle = <ðphy1>; -+ phy-mode = "psgmii"; -+ -+ status = "disabled"; -+ }; -+ -+ swport3: port@3 { /* MAC3 */ -+ reg = <3>; -+ label = "lan3"; -+ phy-handle = <ðphy2>; -+ phy-mode = "psgmii"; -+ -+ status = "disabled"; -+ }; -+ -+ swport4: port@4 { /* MAC4 */ -+ reg = <4>; -+ label = "lan4"; -+ phy-handle = <ðphy3>; -+ phy-mode = "psgmii"; -+ -+ status = "disabled"; -+ }; -+ -+ swport5: port@5 { /* MAC5 */ -+ reg = <5>; -+ label = "wan"; -+ phy-handle = <ðphy4>; -+ phy-mode = "psgmii"; -+ -+ status = "disabled"; -+ }; -+ }; -+ }; -+ - gmac: ethernet@c080000 { - compatible = "qcom,ipq4019-ess-edma"; - reg = <0xc080000 0x8000>; diff --git a/target/linux/ipq40xx/patches-5.15/707-dt-bindings-net-add-QCA807x-PHY.patch b/target/linux/ipq40xx/patches-5.15/707-dt-bindings-net-add-QCA807x-PHY.patch deleted file mode 100644 index dfb8d692abe..00000000000 --- a/target/linux/ipq40xx/patches-5.15/707-dt-bindings-net-add-QCA807x-PHY.patch +++ /dev/null @@ -1,61 +0,0 @@ -From c66863c1ba8995b61e6d727d78a241c734f5bb57 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 1 Oct 2020 15:05:35 +0200 -Subject: [PATCH] dt-bindings: net: add QCA807x PHY - -Add DT bindings for Qualcomm QCA807x PHY series. - -Signed-off-by: Robert Marko ---- - include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++ - 1 file changed, 45 insertions(+) - create mode 100644 include/dt-bindings/net/qcom-qca807x.h - ---- /dev/null -+++ b/include/dt-bindings/net/qcom-qca807x.h -@@ -0,0 +1,45 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Device Tree constants for the Qualcomm QCA807X PHYs -+ */ -+ -+#ifndef _DT_BINDINGS_QCOM_QCA807X_H -+#define _DT_BINDINGS_QCOM_QCA807X_H -+ -+#define PSGMII_QSGMII_TX_DRIVER_140MV 0 -+#define PSGMII_QSGMII_TX_DRIVER_160MV 1 -+#define PSGMII_QSGMII_TX_DRIVER_180MV 2 -+#define PSGMII_QSGMII_TX_DRIVER_200MV 3 -+#define PSGMII_QSGMII_TX_DRIVER_220MV 4 -+#define PSGMII_QSGMII_TX_DRIVER_240MV 5 -+#define PSGMII_QSGMII_TX_DRIVER_260MV 6 -+#define PSGMII_QSGMII_TX_DRIVER_280MV 7 -+#define PSGMII_QSGMII_TX_DRIVER_300MV 8 -+#define PSGMII_QSGMII_TX_DRIVER_320MV 9 -+#define PSGMII_QSGMII_TX_DRIVER_400MV 10 -+#define PSGMII_QSGMII_TX_DRIVER_500MV 11 -+/* Default value */ -+#define PSGMII_QSGMII_TX_DRIVER_600MV 12 -+ -+/* Full amplitude, full bias current */ -+#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS 0 -+/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */ -+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS 1 -+/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */ -+#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS 2 -+/* Both amplitude and bias current follow DSP */ -+#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS 3 -+/* Full amplitude, half bias current */ -+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS 4 -+/* Amplitude follow DSP setting; 1/4 bias current when cable<10m, -+ * otherwise half bias current -+ */ -+#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS 5 -+/* Full amplitude; same bias current setting with “010” and “011”, -+ * but half more bias is reduced when cable <10m -+ */ -+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT 6 -+/* Amplitude follow DSP; same bias current setting with “110”, default value */ -+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT 7 -+ -+#endif diff --git a/target/linux/ipq40xx/patches-5.15/708-net-phy-Add-Qualcom-QCA807x-driver.patch b/target/linux/ipq40xx/patches-5.15/708-net-phy-Add-Qualcom-QCA807x-driver.patch deleted file mode 100644 index 6a92a103d64..00000000000 --- a/target/linux/ipq40xx/patches-5.15/708-net-phy-Add-Qualcom-QCA807x-driver.patch +++ /dev/null @@ -1,50 +0,0 @@ -From f825cdc8bfde7616a14e2163f16303a8973031d2 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Wed, 7 Oct 2020 17:38:48 +0200 -Subject: [PATCH] net: phy: Add Qualcom QCA807x driver - -This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s. - -They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s. - -They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber. - -Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber. - -Each PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s. -But some vendors used these to driver generic LED-s controlled by userspace, -so lets enable registering each PHY as GPIO controller and add driver for it. - -These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards. - -Signed-off-by: Robert Marko ---- - drivers/net/phy/Kconfig | 6 ++++++ - drivers/net/phy/Makefile | 1 + - 2 files changed, 7 insertions(+) - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -347,6 +347,12 @@ config AT803X_PHY - Currently supports the AR8030, AR8031, AR8033, AR8035 and internal - QCA8337(Internal qca8k PHY) model - -+config QCA807X_PHY -+ tristate "Qualcomm QCA807X PHYs" -+ depends on OF_MDIO -+ help -+ Currently supports the QCA8072 and QCA8075 models. -+ - config QSEMI_PHY - tristate "Quality Semiconductor PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -92,6 +92,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o - obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp-c45-tja11xx.o - obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o - obj-$(CONFIG_QSEMI_PHY) += qsemi.o -+obj-$(CONFIG_QCA807X_PHY) += qca807x.o - obj-$(CONFIG_REALTEK_PHY) += realtek.o - obj-$(CONFIG_RENESAS_PHY) += uPD60620.o - obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o diff --git a/target/linux/ipq40xx/patches-5.15/709-arm-dts-ipq4019-QCA807x-properties.patch b/target/linux/ipq40xx/patches-5.15/709-arm-dts-ipq4019-QCA807x-properties.patch deleted file mode 100644 index cc4b44b393a..00000000000 --- a/target/linux/ipq40xx/patches-5.15/709-arm-dts-ipq4019-QCA807x-properties.patch +++ /dev/null @@ -1,61 +0,0 @@ -From e0fa88eaa3c176b71e563da68949ac2ab45aaa61 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 2 Oct 2020 10:43:26 +0200 -Subject: [PATCH] arm: dts: ipq4019: QCA807x properties - -This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI. - -Signed-off-by: Robert Marko ---- - arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - - / { - #address-cells = <1>; -@@ -726,22 +727,38 @@ - - ethphy0: ethernet-phy@0 { - reg = <0>; -+ -+ qcom,control-dac = ; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; -+ -+ qcom,control-dac = ; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; -+ -+ qcom,control-dac = ; - }; - - ethphy3: ethernet-phy@3 { - reg = <3>; -+ -+ qcom,control-dac = ; - }; - - ethphy4: ethernet-phy@4 { - reg = <4>; -+ -+ qcom,control-dac = ; -+ }; -+ -+ psgmiiphy: psgmii-phy@5 { -+ reg = <5>; -+ -+ qcom,tx-driver-strength = ; - }; - }; - diff --git a/target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch deleted file mode 100644 index 9b44a4c885c..00000000000 --- a/target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch +++ /dev/null @@ -1,180 +0,0 @@ -From: Christian Lamparter -Subject: SoC: add qualcomm syscon ---- a/drivers/soc/qcom/Makefile -+++ b/drivers/soc/qcom/Makefile -@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o - obj-$(CONFIG_QCOM_SMSM) += smsm.o - obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o - obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o -+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o - obj-$(CONFIG_QCOM_APR) += apr.o - obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o - obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o ---- a/drivers/soc/qcom/Kconfig -+++ b/drivers/soc/qcom/Kconfig -@@ -192,6 +192,13 @@ config QCOM_SOCINFO - Say yes here to support the Qualcomm socinfo driver, providing - information about the SoC to user space. - -+config QCOM_TCSR -+ tristate "QCOM Top Control and Status Registers" -+ depends on ARCH_QCOM -+ help -+ Say y here to enable TCSR support. The TCSR provides control -+ functions for various peripherals. -+ - config QCOM_WCNSS_CTRL - tristate "Qualcomm WCNSS control driver" - depends on ARCH_QCOM || COMPILE_TEST ---- /dev/null -+++ b/drivers/soc/qcom/qcom_tcsr.c -@@ -0,0 +1,98 @@ -+/* -+ * Copyright (c) 2014, The Linux foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License rev 2 and -+ * only rev 2 as published by the free Software foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define TCSR_USB_PORT_SEL 0xb0 -+#define TCSR_USB_HSPHY_CONFIG 0xC -+ -+#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0 -+#define TCSR_ESS_INTERFACE_SEL_MASK 0xf -+ -+#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0 -+#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4 -+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4 -+ -+static int tcsr_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ const struct device_node *node = pdev->dev.of_node; -+ void __iomem *base; -+ u32 val; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) { -+ dev_err(&pdev->dev, "setting usb port select = %d\n", val); -+ writel(val, base + TCSR_USB_PORT_SEL); -+ } -+ -+ if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) { -+ dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val); -+ writel(val, base + TCSR_USB_HSPHY_CONFIG); -+ } -+ -+ if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) { -+ u32 tmp = 0; -+ dev_info(&pdev->dev, "setting ess interface select = %x\n", val); -+ tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET); -+ tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK); -+ tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK); -+ writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET); -+ } -+ -+ if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) { -+ dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val); -+ writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET); -+ writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET); -+ } -+ -+ if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) { -+ dev_info(&pdev->dev, -+ "setting wifi_noc_memtype_m0_m2 = %x\n", val); -+ writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2); -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id tcsr_dt_match[] = { -+ { .compatible = "qcom,tcsr", }, -+ { }, -+}; -+ -+MODULE_DEVICE_TABLE(of, tcsr_dt_match); -+ -+static struct platform_driver tcsr_driver = { -+ .driver = { -+ .name = "tcsr", -+ .owner = THIS_MODULE, -+ .of_match_table = tcsr_dt_match, -+ }, -+ .probe = tcsr_probe, -+}; -+ -+module_platform_driver(tcsr_driver); -+ -+MODULE_AUTHOR("Andy Gross "); -+MODULE_DESCRIPTION("QCOM TCSR driver"); -+MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/include/dt-bindings/soc/qcom,tcsr.h -@@ -0,0 +1,48 @@ -+/* Copyright (c) 2014, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+#ifndef __DT_BINDINGS_QCOM_TCSR_H -+#define __DT_BINDINGS_QCOM_TCSR_H -+ -+#define TCSR_USB_SELECT_USB3_P0 0x1 -+#define TCSR_USB_SELECT_USB3_P1 0x2 -+#define TCSR_USB_SELECT_USB3_DUAL 0x3 -+ -+/* IPQ40xx HS PHY Mode Select */ -+#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7 -+#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7 -+ -+/* IPQ40xx ess interface mode select */ -+#define TCSR_ESS_PSGMII 0 -+#define TCSR_ESS_PSGMII_RGMII5 1 -+#define TCSR_ESS_PSGMII_RMII0 2 -+#define TCSR_ESS_PSGMII_RMII1 4 -+#define TCSR_ESS_PSGMII_RMII0_RMII1 6 -+#define TCSR_ESS_PSGMII_RGMII4 9 -+ -+/* -+ * IPQ40xx WiFi Global Config -+ * Bit 30:AXID_EN -+ * Enable AXI master bus Axid translating to confirm all txn submitted by order -+ * Bit 24: Use locally generated socslv_wxi_bvalid -+ * 1: use locally generate socslv_wxi_bvalid for performance. -+ * 0: use SNOC socslv_wxi_bvalid. -+ */ -+#define TCSR_WIFI_GLB_CFG 0x41000000 -+ -+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */ -+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222 -+ -+/* TCSR A/B REG */ -+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0 -+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1 -+ -+#endif diff --git a/target/linux/ipq40xx/patches-5.15/910-Revert-firmware-qcom_scm-Clear-download-bit-during-r.patch b/target/linux/ipq40xx/patches-5.15/910-Revert-firmware-qcom_scm-Clear-download-bit-during-r.patch deleted file mode 100644 index b5b89b26f1d..00000000000 --- a/target/linux/ipq40xx/patches-5.15/910-Revert-firmware-qcom_scm-Clear-download-bit-during-r.patch +++ /dev/null @@ -1,27 +0,0 @@ -From c668fd2c4d9ad4a510fd214a2da83bd9b67a2508 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Sun, 13 Aug 2023 18:13:08 +0200 -Subject: [PATCH] Revert "firmware: qcom_scm: Clear download bit during reboot" - -This reverts commit a3ea89b5978dbcd0fa55f675c5a1e04611093709. - -It is breaking reboot on IPQ4019 boards, so revert until a proper fix -is found. - -Signed-off-by: Robert Marko ---- - drivers/firmware/qcom_scm.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/firmware/qcom_scm.c -+++ b/drivers/firmware/qcom_scm.c -@@ -1361,7 +1361,8 @@ static int qcom_scm_probe(struct platfor - static void qcom_scm_shutdown(struct platform_device *pdev) - { - /* Clean shutdown, disable download mode to allow normal restart */ -- qcom_scm_set_download_mode(false); -+ if (download_mode) -+ qcom_scm_set_download_mode(false); - } - - static const struct of_device_id qcom_scm_dt_match[] = { diff --git a/target/linux/ipq40xx/patches-5.15/998-lantiq-atm-hacks.patch b/target/linux/ipq40xx/patches-5.15/998-lantiq-atm-hacks.patch deleted file mode 100644 index c15a4b3ae3e..00000000000 --- a/target/linux/ipq40xx/patches-5.15/998-lantiq-atm-hacks.patch +++ /dev/null @@ -1,43 +0,0 @@ -From: John Crispin -Date: Fri, 3 Aug 2012 10:27:25 +0200 -Subject: [PATCH 04/36] MIPS: lantiq: add atm hack - -Signed-off-by: John Crispin ---- a/include/uapi/linux/atm.h -+++ b/include/uapi/linux/atm.h -@@ -131,8 +131,14 @@ - #define ATM_ABR 4 - #define ATM_ANYCLASS 5 /* compatible with everything */ - -+#define ATM_VBR_NRT ATM_VBR -+#define ATM_VBR_RT 6 -+#define ATM_UBR_PLUS 7 -+#define ATM_GFR 8 -+ - #define ATM_MAX_PCR -1 /* maximum available PCR */ - -+ - struct atm_trafprm { - unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */ - int max_pcr; /* maximum PCR in cells per second */ -@@ -155,6 +161,9 @@ struct atm_trafprm { - unsigned int adtf :10; /* ACR Decrease Time Factor (10-bit) */ - unsigned int cdf :3; /* Cutoff Decrease Factor (3-bit) */ - unsigned int spare :9; /* spare bits */ -+ int scr; /* sustained rate in cells per second */ -+ int mbs; /* maximum burst size (MBS) in cells */ -+ int cdv; /* Cell delay variation */ - }; - - struct atm_qos { ---- a/net/atm/proc.c -+++ b/net/atm/proc.c -@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil - static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) - { - static const char *const class_name[] = { -- "off", "UBR", "CBR", "VBR", "ABR"}; -+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; - static const char *const aal_name[] = { - "---", "1", "2", "3/4", /* 0- 3 */ - "???", "5", "???", "???", /* 4- 7 */ diff --git a/target/linux/ipq40xx/patches-5.15/999-atm-mpoa-intel-dsl-phy-support.patch b/target/linux/ipq40xx/patches-5.15/999-atm-mpoa-intel-dsl-phy-support.patch deleted file mode 100644 index b774fc39d8c..00000000000 --- a/target/linux/ipq40xx/patches-5.15/999-atm-mpoa-intel-dsl-phy-support.patch +++ /dev/null @@ -1,137 +0,0 @@ -From: Subhra Banerjee -Date: Fri, 31 Aug 2018 12:01:19 +0530 -Subject: [PATCH] UGW_SW-29163: ATM oam support - ---- a/drivers/net/ppp/ppp_generic.c -+++ b/drivers/net/ppp/ppp_generic.c -@@ -2952,6 +2952,22 @@ char *ppp_dev_name(struct ppp_channel *c - return name; - } - -+/* -+ * Return the PPP device interface pointer -+ */ -+struct net_device *ppp_device(struct ppp_channel *chan) -+{ -+ struct channel *pch = chan->ppp; -+ struct net_device *dev = NULL; -+ -+ if (pch) { -+ read_lock_bh(&pch->upl); -+ if (pch->ppp && pch->ppp->dev) -+ dev = pch->ppp->dev; -+ read_unlock_bh(&pch->upl); -+ } -+ return dev; -+} - - /* - * Disconnect a channel from the generic layer. -@@ -3598,6 +3614,7 @@ EXPORT_SYMBOL(ppp_unregister_channel); - EXPORT_SYMBOL(ppp_channel_index); - EXPORT_SYMBOL(ppp_unit_number); - EXPORT_SYMBOL(ppp_dev_name); -+EXPORT_SYMBOL(ppp_device); - EXPORT_SYMBOL(ppp_input); - EXPORT_SYMBOL(ppp_input_error); - EXPORT_SYMBOL(ppp_output_wakeup); ---- a/include/linux/ppp_channel.h -+++ b/include/linux/ppp_channel.h -@@ -74,6 +74,9 @@ extern int ppp_unit_number(struct ppp_ch - /* Get the device name associated with a channel, or NULL if none */ - extern char *ppp_dev_name(struct ppp_channel *); - -+/* Get the device pointer associated with a channel, or NULL if none */ -+extern struct net_device *ppp_device(struct ppp_channel *); -+ - /* - * SMP locking notes: - * The channel code must ensure that when it calls ppp_unregister_channel, ---- a/net/atm/Kconfig -+++ b/net/atm/Kconfig -@@ -56,6 +56,12 @@ config ATM_MPOA - subnetwork boundaries. These shortcut connections bypass routers - enhancing overall network performance. - -+config ATM_MPOA_INTEL_DSL_PHY_SUPPORT -+ bool "Intel DSL Phy MPOA support" -+ depends on ATM && INET && ATM_MPOA!=n -+ help -+ Add support for Intel DSL Phy ATM MPOA -+ - config ATM_BR2684 - tristate "RFC1483/2684 Bridged protocols" - depends on ATM && INET ---- a/net/atm/br2684.c -+++ b/net/atm/br2684.c -@@ -596,6 +596,11 @@ static int br2684_regvcc(struct atm_vcc - atmvcc->push = br2684_push; - atmvcc->pop = br2684_pop; - atmvcc->release_cb = br2684_release_cb; -+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT) -+ if (atm_hook_mpoa_setup) /* IPoA or EoA w/o FCS */ -+ atm_hook_mpoa_setup(atmvcc, brdev->payload == p_routed ? 3 : 0, -+ brvcc->encaps == BR2684_ENCAPS_LLC ? 1 : 0, net_dev); -+#endif - atmvcc->owner = THIS_MODULE; - - /* initialize netdev carrier state */ ---- a/net/atm/common.c -+++ b/net/atm/common.c -@@ -137,6 +137,11 @@ static struct proto vcc_proto = { - .release_cb = vcc_release_cb, - }; - -+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT) -+void (*atm_hook_mpoa_setup)(struct atm_vcc *, int, int, struct net_device *) = NULL; -+EXPORT_SYMBOL(atm_hook_mpoa_setup); -+#endif -+ - int vcc_create(struct net *net, struct socket *sock, int protocol, int family, int kern) - { - struct sock *sk; ---- a/net/atm/common.h -+++ b/net/atm/common.h -@@ -53,4 +53,6 @@ int svc_change_qos(struct atm_vcc *vcc,s - - void atm_dev_release_vccs(struct atm_dev *dev); - -+extern void (*atm_hook_mpoa_setup)(struct atm_vcc *, int, int, struct net_device *); -+ - #endif ---- a/net/atm/mpc.c -+++ b/net/atm/mpc.c -@@ -31,6 +31,7 @@ - /* Modular too */ - #include - -+#include "common.h" - #include "lec.h" - #include "mpc.h" - #include "resources.h" -@@ -645,6 +646,10 @@ static int atm_mpoa_vcc_attach(struct at - vcc->proto_data = mpc->dev; - vcc->push = mpc_push; - -+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT) -+ if (atm_hook_mpoa_setup) /* IPoA, LLC */ -+ atm_hook_mpoa_setup(vcc, 3, 1, mpc->dev); -+#endif - return 0; - } - ---- a/net/atm/pppoatm.c -+++ b/net/atm/pppoatm.c -@@ -422,6 +422,12 @@ static int pppoatm_assign_vcc(struct atm - atmvcc->user_back = pvcc; - atmvcc->push = pppoatm_push; - atmvcc->pop = pppoatm_pop; -+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT) -+ if (atm_hook_mpoa_setup) /* PPPoA */ -+ atm_hook_mpoa_setup(atmvcc, 2, -+ pvcc->encaps == e_llc ? 1 : 0, -+ ppp_device(&pvcc->chan)); -+#endif - atmvcc->release_cb = pppoatm_release_cb; - __module_get(THIS_MODULE); - atmvcc->owner = THIS_MODULE; From 964b576fc133019d0379983df597e4eb343cd635 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20B=C3=B6hler?= Date: Mon, 25 Sep 2023 20:16:22 +0200 Subject: [PATCH 14/30] ipq40xx: ZTE MF287 fix sysupgrade MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While refactoring support for the MF287 series, an entry in platform.sh was overlooked - this fixes sysupgrade on this devices. Signed-off-by: Andreas Böhler --- target/linux/ipq40xx/base-files/lib/upgrade/platform.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh b/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh index 32a25a28f26..aa64fb9379f 100644 --- a/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh +++ b/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh @@ -215,6 +215,7 @@ platform_do_upgrade() { teltonika,rutx50 |\ zte,mf18a |\ zte,mf286d |\ + zte,mf287 |\ zte,mf287plus |\ zte,mf287pro |\ zte,mf289f) From 4c83b6a4f83cd344ee56632ea95386dad81c2c63 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20B=C3=B6hler?= Date: Mon, 25 Sep 2023 20:18:52 +0200 Subject: [PATCH 15/30] ipq40xx: ZTE MF282 Plus fix sysupgrade MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While adding support for the MF282 Plus, an entry in platform.sh was overlooked - this fixes sysupgrade on this devices. Signed-off-by: Andreas Böhler --- target/linux/ipq40xx/base-files/lib/upgrade/platform.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh b/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh index aa64fb9379f..22f2ee9ccc8 100644 --- a/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh +++ b/target/linux/ipq40xx/base-files/lib/upgrade/platform.sh @@ -214,6 +214,7 @@ platform_do_upgrade() { teltonika,rutx10 |\ teltonika,rutx50 |\ zte,mf18a |\ + zte,mf282plus |\ zte,mf286d |\ zte,mf287 |\ zte,mf287plus |\ From d2b5f4b2cd5509915834e04187aae76aac90c797 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 24 Sep 2023 20:16:21 +0200 Subject: [PATCH 16/30] treewide: Add extra CPE identifier This adds some Common Platform Enumerations (CPE) identifiers which I found. Signed-off-by: Hauke Mehrtens --- package/boot/at91bootstrap/Makefile | 1 + package/libs/popt/Makefile | 1 + package/libs/sysfsutils/Makefile | 1 + package/system/iucode-tool/Makefile | 1 + 4 files changed, 4 insertions(+) diff --git a/package/boot/at91bootstrap/Makefile b/package/boot/at91bootstrap/Makefile index efd42ecf5cc..f27a3f01dc2 100644 --- a/package/boot/at91bootstrap/Makefile +++ b/package/boot/at91bootstrap/Makefile @@ -13,6 +13,7 @@ PKG_VERSION:=v4.0.3 PKG_MIRROR_HASH:=1ecdc31a13350fcdcaa3f77ed8ad73906f79fc668dbb2f337e1d5dd877bf9882 PKG_SOURCE_VERSION:=1d9e673698d9db4a4f2301559f481274de2e75ae BINARIES_DIR:=build/binaries +PKG_CPE_ID:=cpe:/a:linux4sam:at91bootstrap AT91BOOTSTRAP_V4=y ifdef CONFIG_PACKAGE_at91bootstrap-sama5d4_xplaineddf_uboot_secure diff --git a/package/libs/popt/Makefile b/package/libs/popt/Makefile index ad767b8eede..ba9c82349bb 100644 --- a/package/libs/popt/Makefile +++ b/package/libs/popt/Makefile @@ -15,6 +15,7 @@ PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=http://ftp.rpm.org/popt/releases/popt-1.x/ PKG_HASH:=c25a4838fc8e4c1c8aacb8bd620edb3084a3d63bf8987fdad3ca2758c63240f9 PKG_LICENSE:=MIT +PKG_CPE_ID:=cpe:/a:popt_project:popt PKG_FIXUP:=autoreconf PKG_REMOVE_FILES:=autogen.sh aclocal.m4 diff --git a/package/libs/sysfsutils/Makefile b/package/libs/sysfsutils/Makefile index ff676308dab..b7c9d8cdc14 100644 --- a/package/libs/sysfsutils/Makefile +++ b/package/libs/sysfsutils/Makefile @@ -15,6 +15,7 @@ PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz PKG_SOURCE_URL:=@SF/linux-diag PKG_HASH:=e865de2c1f559fff0d3fc936e660c0efaf7afe662064f2fb97ccad1ec28d208a PKG_MAINTAINER:=Jo-Philipp Wich +PKG_CPE_ID:=cpe:/a:sysfsutils_project:sysfsutils PKG_LICENSE:=LGPL-2.1 PKG_LICENSE_FILES:=COPYING cmd/GPL lib/LGPL diff --git a/package/system/iucode-tool/Makefile b/package/system/iucode-tool/Makefile index d7c85b2d42d..c2ea37a5c5c 100644 --- a/package/system/iucode-tool/Makefile +++ b/package/system/iucode-tool/Makefile @@ -14,6 +14,7 @@ PKG_RELEASE:=2 PKG_SOURCE:=iucode-tool_$(PKG_VERSION).tar.xz PKG_SOURCE_URL:=https://gitlab.com/iucode-tool/releases/raw/latest PKG_HASH:=12b88efa4d0d95af08db05a50b3dcb217c0eb2bfc67b483779e33d498ddb2f95 +PKG_CPE_ID:=cpe:/a:iucode-tool_project:iucode-tool PKG_BUILD_DEPENDS:=USE_UCLIBC:argp-standalone USE_MUSL:argp-standalone HOST_BUILD_DEPENDS:=HOST_OS_MACOS:argp-standalone/host From 74e7f8ebbdc19c58ac59c792154041a6b3c124f5 Mon Sep 17 00:00:00 2001 From: Glen Lee Date: Fri, 25 Aug 2023 21:46:59 -0400 Subject: [PATCH 17/30] ipq40xx: add support for Extreme Networks WS-AP391x series APs This in a single image to run many types of hardware in the AP391x series (AP3912/AP3915/AP3916/AP3917/AP7662). Hardware -------- Qualcomm IPQ4029 WiSoC 2T2R 802.11 abgn 2T2R 802.11 nac Macronix MX25L25635E SPI-NOR (32M) 512M DDR3 RAM 1-4x Gigabit Ethernet Senao EXT1025 HD Camera (AP3916 only) USB 2.0 Port (AP3915e only) 1x Cisco RJ-45 Console port - except for AP3916 and AP3912 where there is no external serial console and it is TDB how to solder one. Possibly J12 is UART with pin1 = 3.3V, pin2 = GND, pin3 = TXD, pin4 = RXD. - Settings: 115200 8N1 Installation With Serial Console -------------------------------- 1. Attach to the Console port. Power up the device and press the s key to interrupt autoboot. 2. The default username / password to the bootloader is admin / new2day 3. Check uboot variables using printenv, and update if necessary: $ setenv AP_MODE 0 $ setenv WATCHDOG_COUNT 0 $ setenv WATCHDOG_LIMIT 0 $ setenv AP_PERSONALITY identifi $ setenv serverip $ setenv ipaddr $ setenv MOSTRECENTKERNEL 0; ## OpenWRT only uses the primary image $ saveenv $ saveenv ## 2nd time to write the secondary copy 4. On the TFTP server located at , download the OpenWrt initramfs image. Rename and serve it as vmlinux.gz.uImage.3912 5. TFTP boot the OpenWrt initramfs image from the AP serial console: $ run boot_net 6. Wait for OpenWrt to start. Internet port sw-eth5 is assiged to LAN bridge and sw-eth4 (if available) is assigned to WAN. The LAN port will use default IP address 192.168.1.1 and run a DHCP server. If you already have a working DHCP server or already have 192.168.1.1 on your network you MUST DISCONNECT the LAN cable from your active network immediately after the power/status LED turns green! At this point, you need to temporarily reconfigure the AP to have a way to transfer the OpenWRT sysupgrade image to it. Reconfigure the newly converted OpenWRT AP using serial console or plug in a PC to a sw-eth5 as a separate network. Note -- the LAN/WAN port assignments were designed to make it possible to convert to OpenWRT without serial console and using a common firmware image for many AP models -- they may not make the most sense when fully deployed. 7. Download and transfer the sysupgrade image to the device using e.g. SCP. 8. Install OpenWrt to the device using "sysupgrade" $ sysupgrade -n /path/to/openwrt.bin 9. After it boots up again, as in step 6, connect to AP and reconfigure for final deployment. This build supports APs in the AP391x series and similar such as WiNG AP7662. Ethernet devices within OpenWRT are named "sw-eth1" thru "sw-eth5". Mapping from OpenWRT internal naming to external naming on the case is as follows: ``` |sw-eth1|sw-eth2|sw-eth3|sw-eth4|sw-eth5 ------------+-------+-------+-------+-------+------- AP3917 | | | | GE2 | GE1 ------------+-------+-------+-------+-------+------- AP7662 | | | | GE2 | GE1 ------------+-------+-------+-------+-------+------- AP3916 | | | | CAM* | GE1 ------------+-------+-------+-------+-------+------- AP3915 | | | | | GE1 ------------+-------+-------+-------+-------+------- AP3912 | | P1 | P2 | P3 | LAN1 ------------+-------+-------+-------+-------+------- ``` By default sw-eth4 is mapped to WAN. All others are assigned to the LAN. CAM* - On AP3916, sw-eth4 is the camera's interface. You should reconfigure this to be on LAN after OpenWRT boots from flash. Installation Without Serial Console ----------------------------------- The main premise is to set u-boot environment variables using the Extreme Networks firmware's rdwr_boot_cfg program. $ rdwr_boot_cfg Utility to manipulate the boot ROM config blocks All errors are written to the sytem log file (/tmp/log/ap.log) ``` Usage: rdwr_boot_cfg ... read_all read the entire active block read_var read a single variable from the active block read_var_f read a single variable from the active block (formatted) write_var write a single variable/value pair to both blocks rm_var delete a single variable from both blocks ``` WARNING: Be very sure you have set the u-boot environment correctly. If not, it can only be fixed by attaching serial console! Be aware that the Extreme Networks shell environment will automatically reboot every 5 minutes if there is no controller present. Read and understand these steps fully before attempting. It is easy to make mistakes! 1. Place the OpenWRT initramfs on the TFTP server and name it as vmlinux.gz.uImage.3912 2. Boot up to Extreme Networks WING-Campus mode OS. Port GE1/LAN1 will be a DHCP **client**. Find out the IP address from your DHCP server and SSH in. Default user/passwd is admin/new2day or admin/admin123. If it is booting to WING-Distributed mode, use this command to convert to Campus mode. $ operational-mode centralized 3. Upon bootup you have about 5mins to changed these u-boot variables if necessary using the rdwr_boot_cfg command in Linux shell: $ rdwr_boot_cfg write_var AP_MODE=0 $ rdwr_boot_cfg write_var MOSTRECENTKERNEL=0 $ rdwr_boot_cfg write_var WATCHDOG_COUNT=0 $ rdwr_boot_cfg write_var WATCHDOG_LIMIT=0 $ rdwr_boot_cfg write_var AP_PERSONALITY=identifi $ rdwr_boot_cfg write_var serverip= $ rdwr_boot_cfg write_var ipaddr= $ rdwr_boot_cfg write_var bootcmd="run boot_net" 4. Reboot AP. 5. Connect PC with ethernet to GE1/LAN1 port. You should get a DHCP address in the 192.168.1.x range and should be able to SSH to the new OpenWRT TFTP recovery/installation shell. 6. At this point, u-boot is still set to TFTP boot, so you have to replace the TFTP image with the original Extreme Networks image so that you can change the u-boot environment. See the instructions for Extracting Extreme Networks firmware image. DON'T REBOOT YET! 7. Next you must follow steps 6 thru 8 from the Installation with serial console. After which you should have OpenWRT installed to primary flash firmware. 8. Now Reboot. This time it will boot using TFTP into Extreme Networks image. You may need to reconnect cables at this point -- GE1/LAN1 will be a DHCP **client** and you can SSH in -- just like step 2. Get the IP address from you own DHCP server. 9. Set u-boot env as follows: $ rdwr_boot_cfg write_var MOSTRECENTKERNEL=0 $ rdwr_boot_cfg write_var WATCHDOG_COUNT=0 $ rdwr_boot_cfg write_var bootcmd="run boot_flash" 10. Reboot AP. This time it should be into OpenWRT. GE1/LAN1 will be a DHCP **server** and have static IP 192.168.1.1 -- just like step 5. 11. SSH into the LAN port and reconfigure to final configuration. Don't make any changes that prevent you from SSH or Luci access! Restoring Extreme Networks firmware ----------------------------------- Assuming you have the original Extreme Networks image: 1. Login to OpenWRT shell 2. scp the Extreme Networks packaged firmware image file AP391x-*.img to /tmp 3. Extract the firmware uimage file: $ tar xjf AP391x-*.img vmlinux.gz.uImage 4. Force run sysupgrade: $ sysupgrade -F /tmp/AP391x-*.img / 5. Restore the u-boot varable(s): $ rdwr_boot_cfg write_var WATCHDOG_LIMIT=3 USB 2.0 Port on AP3915e ----------------------- Enable this by setting LED "eth:amber_or_usb_enable" to ALWAYS ON. Reviewed-by: Robert Marko Signed-off-by: Glen Lee --- .../ipq40xx/base-files/etc/board.d/02_network | 3 + .../etc/hotplug.d/firmware/11-ath10k-caldata | 6 +- .../lib/preinit/05_set_iface_mac_ipq40xx.sh | 3 +- .../arm/boot/dts/qcom-ipq4029-ws-ap391x.dts | 344 ++++++++++++++++++ target/linux/ipq40xx/image/generic.mk | 10 + 5 files changed, 363 insertions(+), 3 deletions(-) create mode 100644 target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ws-ap391x.dts diff --git a/target/linux/ipq40xx/base-files/etc/board.d/02_network b/target/linux/ipq40xx/base-files/etc/board.d/02_network index a3f16507115..babde1b8e22 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/02_network +++ b/target/linux/ipq40xx/base-files/etc/board.d/02_network @@ -74,6 +74,9 @@ ipq40xx_setup_interfaces() devolo,magic-2-wifi-next) ucidef_set_interface_lan "lan1 lan2 ghn" ;; + extreme-networks,ws-ap391x) + ucidef_set_interfaces_lan_wan "sw-eth1 sw-eth2 sw-eth3 sw-eth5" "sw-eth4" + ;; linksys,whw01) ucidef_set_interface_lan "eth1 eth2" ;; diff --git a/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata index 7b72df86ef4..654be2697a6 100644 --- a/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata +++ b/target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -94,7 +94,8 @@ case "$FIRMWARE" in caldata_extract "ART" 0x1000 0x2f20 ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 2) ;; - extreme-networks,ws-ap3915i) + extreme-networks,ws-ap3915i |\ + extreme-networks,ws-ap391x) caldata_extract "ART" 0x1000 0x2f20 ath10k_patch_mac $(mtd_get_mac_ascii CFG1 RADIOADDR0) ;; @@ -189,7 +190,8 @@ case "$FIRMWARE" in caldata_extract "ART" 0x5000 0x2f20 ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 3) ;; - extreme-networks,ws-ap3915i) + extreme-networks,ws-ap3915i |\ + extreme-networks,ws-ap391x) caldata_extract "ART" 0x5000 0x2f20 ath10k_patch_mac $(mtd_get_mac_ascii CFG1 RADIOADDR1) ;; diff --git a/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh b/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh index ce0b55bb809..96e70f62a92 100644 --- a/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh +++ b/target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh @@ -20,7 +20,8 @@ preinit_set_mac_address() { base_mac=$(cat /sys/class/net/eth0/address) ip link set dev eth1 address $(macaddr_add "$base_mac" 1) ;; - extreme-networks,ws-ap3915i) + extreme-networks,ws-ap3915i|\ + extreme-networks,ws-ap391x) ip link set dev eth0 address $(mtd_get_mac_ascii CFG1 ethaddr) ;; linksys,ea8300|\ diff --git a/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ws-ap391x.dts b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ws-ap391x.dts new file mode 100644 index 00000000000..04b55b1abf9 --- /dev/null +++ b/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ws-ap391x.dts @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +#include "qcom-ipq4019.dtsi" +#include +#include +#include + +/ { + model = "Extreme Networks WS-AP391x"; + compatible = "extreme-networks,ws-ap391x"; + + aliases { + led-boot = &led_system_green; + led-failsafe = &led_system_red; + led-running = &led_system_green; + led-upgrade = &led_system_red; + }; + + soc { + + tcsr@1949000 { + compatible = "qcom,tcsr"; + reg = <0x1949000 0x100>; + qcom,wifi_glb_cfg = ; + }; + + ess_tcsr@1953000 { + compatible = "qcom,tcsr"; + reg = <0x1953000 0x1000>; + qcom,ess-interface-select = ; + }; + + tcsr@1957000 { + compatible = "qcom,tcsr"; + reg = <0x1957000 0x100>; + qcom,wifi_noc_memtype_m0_m2 = ; + }; + + }; + + leds { + compatible = "gpio-leds"; + + led_system_green: system_green { + label = "system:green"; + gpios = <&tlmm 49 GPIO_ACTIVE_LOW>; + }; + + /* + * system:amber ==> AP3917 + * system:red ==> AP3916 + * */ + led_system_red: system_red { + label = "system:red_or_system:amber"; + gpios = <&tlmm 50 GPIO_ACTIVE_LOW>; + }; + + led_wlan24_green: wlan24_green { + label = "wlan24:green"; + gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + /* + * wlan24:amber ==> AP3915/AP3917 + * pse:green ==> AP3912 + * */ + led_wlan24_amber: wlan24_amber { + label = "wlan24:amber_or_pse:green"; + gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; + }; + + led_wlan5_green: wlan5_green { + label = "wlan5:green"; + gpios = <&tlmm 22 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + /* iot:blue ==> AP3917 */ + led_iot_green: iot_green { + label = "iot:green_or_iot:blue"; + gpios = <&tlmm 10 GPIO_ACTIVE_LOW>; + }; + + /* eth:green ==> only AP3912/AP3916 */ + led_eth_green: eth_green { + label = "eth:green"; + gpios = <&tlmm 41 GPIO_ACTIVE_LOW>; + }; + + /* + * eth:amber ==> only AP3912/AP3916 + * usb_enable ==> only AP3915e + */ + led_eth_amber: eth_amber { + label = "eth:amber_or_usb_enable"; + gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; + }; + + /* + * wlan5:amber ==> AP3915/AP3917 + * cam:green ==> only AP3916 + */ + led_wlan5_amber: wlan5_amber { + label = "wlan5:amber_or_cam:green"; + gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; + }; + + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&prng { + status = "okay"; +}; + +&mdio { + status = "okay"; + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; +}; + +&crypto { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&usb3_ss_phy { + status = "okay"; +}; + +&usb3_hs_phy { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb2_hs_phy { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&blsp_dma { + status = "okay"; +}; + +&blsp1_uart1 { + pinctrl-0 = <&serial_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&cryptobam { + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + +&gmac { + status = "okay"; +}; + +&switch { + status = "okay"; +}; + +&swport1 { + status = "okay"; + label = "sw-eth1"; +}; + +&swport2 { + status = "okay"; + label = "sw-eth2"; +}; + +&swport3 { + status = "okay"; + label = "sw-eth3"; +}; + +/* "GE2" on AP3917/AP3916/WiNG-AP7662 */ +&swport4 { + status = "okay"; + label = "sw-eth4"; +}; + +/* + * "GE1" on AP3917/AP3916/AP3915/AP7662 + * "LAN1" on EXTR-AP3912 + */ +&swport5 { + status = "okay"; + label = "sw-eth5"; +}; + +&tlmm { + mdio_pins: mdio_pinmux { + mux_1 { + pins = "gpio6"; + function = "mdio"; + bias-pull-up; + }; + mux_2 { + pins = "gpio7"; + function = "mdc"; + bias-pull-up; + }; + }; + + spi_0_pins: spi_0_pinmux { + pin { + function = "blsp_spi0"; + pins = "gpio13", "gpio14", "gpio15"; + drive-strength = <12>; + bias-disable; + }; + pin_cs { + function = "gpio"; + pins = "gpio12"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + serial_pins: serial_0_pinmux { + mux { + pins = "gpio16", "gpio17"; + function = "blsp_uart0"; + bias-disable; + }; + }; +}; + +&wifi0 { + status = "okay"; + qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i"; +}; + +&wifi1 { + status = "okay"; + qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i"; +}; + +&blsp1_spi1 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Layout for 0x0 - 0xe0000 unknown */ + + partition@e0000 { + label = "CFG1"; + compatible = "u-boot,env-redundant-bool"; + reg = <0xe0000 0x10000>; + read-only; + }; + + partition@f0000 { + label = "BootBAK"; + reg = <0xf0000 0x70000>; + read-only; + }; + + partition@160000 { + label = "WINGCFG1"; + reg = <0x160000 0x10000>; + read-only; + }; + + partition@170000 { + label = "ART"; + reg = <0x170000 0x10000>; + read-only; + }; + + partition@180000 { + label = "BootPRI"; + reg = <0x180000 0x70000>; + read-only; + }; + + partition@1f0000 { + label = "WINGCFG2"; + reg = <0x1f0000 0x10000>; + read-only; + }; + + partition@200000 { + label = "FS"; + reg = <0x200000 0x80000>; + read-only; + }; + + partition@280000 { + label = "firmware"; + reg = <0x280000 0xeb0000>; + }; + + partition@1130000 { + label = "firmware2"; + reg = <0x1130000 0xeb0000>; + }; + + partition@1fe0000 { + label = "CFG2"; + compatible = "u-boot,env-redundant-bool"; + reg = <0x1fe0000 0x10000>; + read-only; + }; + }; + }; +}; diff --git a/target/linux/ipq40xx/image/generic.mk b/target/linux/ipq40xx/image/generic.mk index 9e1ff89c855..6581d81c00e 100644 --- a/target/linux/ipq40xx/image/generic.mk +++ b/target/linux/ipq40xx/image/generic.mk @@ -538,6 +538,16 @@ define Device/extreme-networks_ws-ap3915i endef TARGET_DEVICES += extreme-networks_ws-ap3915i +define Device/extreme-networks_ws-ap391x + $(call Device/FitImage) + DEVICE_VENDOR := Extreme Networks + DEVICE_MODEL := WS-AP391x + IMAGE_SIZE := 15040k + SOC := qcom-ipq4029 + IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | check-size | append-metadata +endef +TARGET_DEVICES += extreme-networks_ws-ap391x + define Device/ezviz_cs-w3-wd1200g-eup $(call Device/FitImage) DEVICE_VENDOR := EZVIZ From cd14b17cb00cda45819739aa63422a090e3f80e1 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Mon, 25 Sep 2023 20:58:04 +0200 Subject: [PATCH 18/30] mpc85xx: drop WS-AP3715i label-mac Label MAC detection does not work properly, as MAC address is assigned on preinit. Thus, remove the label-mac definition. Signed-off-by: David Bauer --- target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts index d13952acae8..a8a4118b003 100644 --- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts @@ -13,7 +13,6 @@ led-failsafe = &led_power_red; led-running = &led_power_green; led-upgrade = &led_power_red; - label-mac-device = &enet0; }; chosen { From ff95f859ebf710d2914472a3feeeb0d187d14459 Mon Sep 17 00:00:00 2001 From: "Alexey D. Filimonov" Date: Sat, 19 Aug 2023 00:26:59 +0300 Subject: [PATCH 19/30] ramips: cf-ew72-v2: Add support for COMFAST CF-EW72 V2 Add support for COMFAST CF-EW72 V2 Hardware: - SoC: Mediatek MT7621 (MT7621DAT or MT7621AT) - Flash: 16 MiB NOR - RAM: 128 MiB - Ethernet: Built-in, 2 x 1GbE - Power: only 802.3af PD on any port, injector supplied in the box - PoE passthrough: No - Wifi 2.4GHz: Mediatek MT7603BE 802.11b/g/b - Wifi 5GHz: Mediatek MT7613BEN 802.11ac/n/a - LEDs: 8x (only 1 is both visible and controllable, see below) - Buttons: 1x (RESET) Installing OpenWrt: Flashing is done using Mediatek U-Boot System Recovery Mode - make wired connection with 2 cables like this: - - PC (LAN) <-> PoE Injector (LAN) - - PoE Injector (POE) <-> CF-EW72 V2 (LAN). Leave unconnected to CF-EW72 V2 yet. - configure 192.168.1.(2-254)/24 static ip address on your PC LAN - press and keep pressed RESET button on device - power the device by plugging PoE Injector (POE) <-> CF-EW72 V2 (LAN) cable - wait for about 10 seconds until wifi led stops blinking and release RESET button - navigate from your PC to http://192.168.1.1 and upload OpenWrt *-factory.bin firmware file - proceed until router starts blinking with wifi led again (flashing) and stops (rebooting to OpenWrt) MAC addresses as verified by OEM firmware: vendor OpenWrt address LAN lan\eth0 label WAN wan label + 1 2g phy0 label + 2 5g phy1 label + 3 The label MAC address was found in 0xe000. LEDs detailed: The only both visible and controllable indicator is blue:wlan LED. It is not bound by default to indicate activity of any wireless interfaces. Place (WAN->ANT) | Num | GPIO | LED name (LuCI) | Note -----------------|-----|----------------------------------------------------------------------------------------- power | 1 | | | POWER LED. Not controlled with GPIO. hidden_led_2 | 2 | 13 | blue:hidden_led_2 | This LED does not have proper hole in shell. wan | 3 | | | WAN LED. Not controlled with GPIO. hidden_led_4 | 4 | 16 | blue:hidden_led_4 | This LED does not have proper hole in shell. lan | 5 | | | LAN LED. Not controlled with GPIO. noconn_led_6 | 6 | | | Not controlled with GPIO, possibly not connected wlan | 7 | 15 | blue:wlan | WLAN LED. Wireless indicator. noconn_led_8 | 8 | | | Not controlled with GPIO, possibly not connected mt76-phy0 and mt76-phy1 leds also exist in OpenWrt, but do not exist on board. Signed-off-by: Alexey D. Filimonov --- .../ramips/dts/mt7621_comfast_cf-ew72-v2.dts | 192 ++++++++++++++++++ target/linux/ramips/image/mt7621.mk | 15 ++ .../mt7621/base-files/etc/board.d/02_network | 3 +- 3 files changed, 209 insertions(+), 1 deletion(-) create mode 100644 target/linux/ramips/dts/mt7621_comfast_cf-ew72-v2.dts diff --git a/target/linux/ramips/dts/mt7621_comfast_cf-ew72-v2.dts b/target/linux/ramips/dts/mt7621_comfast_cf-ew72-v2.dts new file mode 100644 index 00000000000..8b7b4a035ea --- /dev/null +++ b/target/linux/ramips/dts/mt7621_comfast_cf-ew72-v2.dts @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7621.dtsi" + +#include +#include +#include + +/ { + compatible = "comfast,cf-ew72-v2", "mediatek,mt7621-soc"; + model = "COMFAST CF-EW72 V2"; + + // There are at least two HW variants of cf-ew72-v2: + // With external RAM chip and with integrated RAM (RAM chip not soldered). + // Both act same. + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + + // The only both visible and controllable indicator is wifi LED. + // CF-EW72 have 8 LEDs: + // "wlan" is the only LED is controllable with GPIO and have proper hole in shell. + // "power", "wan" and "lan" LEDs have proper holes in shell, but can not be controlled with GPIO + // "hidden_led_2" and "hidden_led_4" can be controlled with GPIO, but have no proper holes in shell + // "hidden_led_2" is between POWER and WAN LEDs + // "hidden_led_4" is between WAN and LAN LEDs + // "noconn_led_6" and "noconn_led_8" exist, but have no proper holes in shell and not controlled: + // "noconn_led_6" is between LAN and WLAN LEDs + // "noconn_led_8" is after WLAN LED + + // LED "hidden_led_2" between POWER and WAN LEDs is controllable with GPIO, but it has no proper hole in shell; + // LED "hidden_led_4" between WAN and LAN LEDs is controllable with GPIO, but it has no proper hole in shell; + + // TABLE of LEDs. All leds are blue. + // + // Place (WAN->ANT) | Num | GPIO | LED name (LuCI) | Note + // -----------------|-----|----------------------------------------------------------------------------------------- + // power | 1 | | | POWER LED. Not controlled with GPIO. + // hidden_led_2 | 2 | 13 | blue:hidden_led_2 | This LED does not have proper hole in shell. + // wan | 3 | | | WAN LED. Not controlled with GPIO. + // hidden_led_4 | 4 | 16 | blue:hidden_led_4 | This LED does not have proper hole in shell. + // lan | 5 | | | LAN LED. Not controlled with GPIO. + // noconn_led_6 | 6 | | | Not controlled with GPIO, possibly not connected + // wlan | 7 | 15 | blue:wlan | WLAN LED. Wireless indicator. + // noconn_led_8 | 8 | | | Not controlled with GPIO, possibly not connected + + hidden_led_2_blue { + label = "blue:hidden_led_2"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + }; + + hidden_led_4_blue { + label = "blue:hidden_led_4"; + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; + }; + + wlan_blue { + label = "blue:wlan"; + gpios = <&gpio 15 GPIO_ACTIVE_LOW>; + }; + }; + + aliases { + label-mac-device = &wan; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "w25q128"; + reg = <0>; + spi-max-frequency = <10000000>; + m25p,fast-read; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Bootloader"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "Config"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + compatible = "nvmem-cells"; + reg = <0x40000 0x10000>; + read-only; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + macaddr_factory_e000: macaddr@e000 { + compatible = "mac-base"; + reg = <0xe000 0x6>; + #nvmem-cell-cells = <1>; + }; + + // Serial number can be found in "factory" at 0xE100. + // it starts and ends with double quotes `"` and is ASCII string + }; + }; + + partition@50000 { + label = "firmware"; + compatible = "denx,uimage"; + reg = <0x50000 0xfb0000>; + }; + }; + }; +}; + +&gpio { + groups = "i2c", "uart2", "uart3", "sdhci", "jtag"; + function = "gpio"; +}; + +&gmac0 { + nvmem-cells = <&macaddr_factory_e000 0>; + nvmem-cell-names = "mac-address"; +}; + +&pcie { + status = "okay"; +}; + +&pcie0 { + wifi_2_4_ghz: wifi@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x0000>; + // Wi-Fi device reads it's MAC address from EEPROM (&factory + 4) + // adding anything related to mac-address here will cause use random MAC + }; +}; + +&pcie1 { + wifi_5_0_ghz: wifi@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x8000>; + // Wi-Fi device reads it's MAC address from EEPROM, (&factory + 0x8000 + 4) + // adding anything related to mac-address here will cause use random MAC. + }; +}; + +&pcie2 { + status = "disabled"; +}; + +&switch0 { + mediatek,mcm; + ports { + wan: port@0 { + status = "okay"; + label = "wan"; + nvmem-cells = <&macaddr_factory_e000 1>; + nvmem-cell-names = "mac-address"; + }; + + lan: port@1 { + status = "okay"; + label = "lan"; + nvmem-cells = <&macaddr_factory_e000 0>; + nvmem-cell-names = "mac-address"; + }; + }; +}; diff --git a/target/linux/ramips/image/mt7621.mk b/target/linux/ramips/image/mt7621.mk index 0710564fa51..9838810af43 100644 --- a/target/linux/ramips/image/mt7621.mk +++ b/target/linux/ramips/image/mt7621.mk @@ -558,6 +558,21 @@ define Device/comfast_cf-e390ax endef TARGET_DEVICES += comfast_cf-e390ax +define Device/comfast_cf-ew72-v2 + $(Device/dsa-migration) + $(Device/uimage-lzma-loader) + IMAGE_SIZE := 15808k + DEVICE_VENDOR := ComFast + DEVICE_MODEL := CF-EW72 V2 + DEVICE_PACKAGES := kmod-mt7603 kmod-mt7615e kmod-mt7663-firmware-ap \ + -uboot-envtools + IMAGES += factory.bin + IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | \ + check-size | append-metadata + IMAGE/factory.bin := append-kernel | append-rootfs | pad-rootfs | check-size +endef +TARGET_DEVICES += comfast_cf-ew72-v2 + define Device/cudy_m1800 $(Device/dsa-migration) DEVICE_VENDOR := Cudy diff --git a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network index 4496bf8f9f3..67fe45f6336 100644 --- a/target/linux/ramips/mt7621/base-files/etc/board.d/02_network +++ b/target/linux/ramips/mt7621/base-files/etc/board.d/02_network @@ -152,7 +152,8 @@ ramips_setup_interfaces() ucidef_set_interface_lan "lan1 lan2 lan3 lan4" ucidef_set_interface "qtn" ifname "eth1" protocol "static" ipaddr "1.1.1.1" netmask "255.255.255.0" ;; - comfast,cf-e390ax) + comfast,cf-e390ax|\ + comfast,cf-ew72-v2) ucidef_set_interfaces_lan_wan "lan" "wan" ;; *) From 0c43a48735959245f18d79a6e908d3b45cff0a94 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Wed, 27 Sep 2023 15:03:16 +0200 Subject: [PATCH 20/30] hostapd: fix mac address of interfaces created via wdev.uc Use the wdev config with the generated MAC address Signed-off-by: Felix Fietkau --- package/network/services/hostapd/files/wdev.uc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/package/network/services/hostapd/files/wdev.uc b/package/network/services/hostapd/files/wdev.uc index 8a031b40b9e..cf438f7715f 100644 --- a/package/network/services/hostapd/files/wdev.uc +++ b/package/network/services/hostapd/files/wdev.uc @@ -41,7 +41,7 @@ function iface_start(wdev) wdev_config[key] = wdev[key]; if (!wdev_config.macaddr && wdev.mode != "monitor") wdev_config.macaddr = phydev.macaddr_next(); - wdev_create(phy, ifname, wdev); + wdev_create(phy, ifname, wdev_config); system([ "ip", "link", "set", "dev", ifname, "up" ]); if (wdev.freq) system(`iw dev ${ifname} set freq ${wdev.freq} ${wdev.htmode}`); From 0e8641d3b08bf8b9eac8e3338faf11cc058a5124 Mon Sep 17 00:00:00 2001 From: David Bauer Date: Wed, 27 Sep 2023 16:43:54 +0200 Subject: [PATCH 21/30] mpc85xx: add Enterasys WS-AP3715i reset button The reset button was missing from the Enterasys WS-AP3715i DTS. Add the node required for making the reset button work. Signed-off-by: David Bauer --- .../files/arch/powerpc/boot/dts/ws-ap3715i.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts index a8a4118b003..af8917ffe1a 100644 --- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3715i.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later or MIT #include +#include /include/ "fsl/p1010si-pre.dtsi" @@ -70,6 +71,16 @@ }; }; + keys { + compatible = "gpio-keys"; + + reset { + label = "Reset button"; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; From abceef120d57bf066941882630a76788eb4985a9 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Thu, 28 Sep 2023 10:28:43 +0200 Subject: [PATCH 22/30] hostapd: fix wpa_supplicant mac address allocation on ap+sta MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If the full interface is restarted while bringing up an AP, it can trigger a wpa_supplicant interface start before wpa_supplicant is notified of the allocated mac addresses. Fix this by moving the iface_update_supplicant_macaddr call to just after the point where mac addresses are allocated. Reported-by: Michael-cy Lee (李峻宇) Signed-off-by: Felix Fietkau --- .../network/services/hostapd/files/hostapd.uc | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/package/network/services/hostapd/files/hostapd.uc b/package/network/services/hostapd/files/hostapd.uc index 5cddb9c268b..88f01caa93e 100644 --- a/package/network/services/hostapd/files/hostapd.uc +++ b/package/network/services/hostapd/files/hostapd.uc @@ -122,6 +122,14 @@ function iface_config_macaddr_list(config) return macaddr_list; } +function iface_update_supplicant_macaddr(phy, config) +{ + let macaddr_list = []; + for (let i = 0; i < length(config.bss); i++) + push(macaddr_list, config.bss[i].bssid); + ubus.call("wpa_supplicant", "phy_set_macaddr_list", { phy: phy, macaddr: macaddr_list }); +} + function iface_restart(phydev, config, old_config) { let phy = phydev.name; @@ -142,6 +150,8 @@ function iface_restart(phydev, config, old_config) bss.bssid = phydev.macaddr_next(); } + iface_update_supplicant_macaddr(phy, config); + let bss = config.bss[0]; let err = wdev_create(phy, bss.ifname, { mode: "ap" }); if (err) @@ -498,14 +508,6 @@ function iface_reload_config(phydev, config, old_config) return true; } -function iface_update_supplicant_macaddr(phy, config) -{ - let macaddr_list = []; - for (let i = 0; i < length(config.bss); i++) - push(macaddr_list, config.bss[i].bssid); - ubus.call("wpa_supplicant", "phy_set_macaddr_list", { phy: phy, macaddr: macaddr_list }); -} - function iface_set_config(phy, config) { let old_config = hostapd.data.config[phy]; @@ -536,7 +538,6 @@ function iface_set_config(phy, config) hostapd.printf(`Restart interface for phy ${phy}`); let ret = iface_restart(phydev, config, old_config); - iface_update_supplicant_macaddr(phy, config); return ret; } From d304ad045dbbe3d657886c19962274f9f94fa363 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Fri, 22 Sep 2023 18:29:15 +0200 Subject: [PATCH 23/30] sifiveu: copy patches from 5.15 to 6.1 To start the upgrade, we copy the patches from 5.15 to 6.1. Signed-off-by: Zoltan HERPAI --- ...40-cpu-1-2-3-4-set-compatible-to-sif.patch | 49 +++ ...e-unmatched-update-regulators-values.patch | 104 ++++++ ...scv-sifive-unmatched-define-PWM-LEDs.patch | 69 ++++ ...ive-unmatched-add-gpio-poweroff-node.patch | 26 ++ ...e-unleashed-define-opp-table-cpufreq.patch | 116 +++++++ .../0006-riscv-sbi-srst-support.patch | 301 ++++++++++++++++++ 6 files changed, 665 insertions(+) create mode 100644 target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch create mode 100644 target/linux/sifiveu/patches-6.1/0002-riscv-sifive-unmatched-update-regulators-values.patch create mode 100644 target/linux/sifiveu/patches-6.1/0003-riscv-sifive-unmatched-define-PWM-LEDs.patch create mode 100644 target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch create mode 100644 target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch create mode 100644 target/linux/sifiveu/patches-6.1/0006-riscv-sbi-srst-support.patch diff --git a/target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch b/target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch new file mode 100644 index 00000000000..9a1c9681390 --- /dev/null +++ b/target/linux/sifiveu/patches-6.1/0001-riscv-sifive-fu740-cpu-1-2-3-4-set-compatible-to-sif.patch @@ -0,0 +1,49 @@ +From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Wed, 17 Feb 2021 06:06:14 -0800 +Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to + sifive,u74-mc + +Signed-off-by: David Abdurachmanov +--- + arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi ++++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +@@ -39,7 +39,7 @@ + }; + }; + cpu1: cpu@1 { +- compatible = "sifive,bullet0", "riscv"; ++ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; +@@ -63,7 +63,7 @@ + }; + }; + cpu2: cpu@2 { +- compatible = "sifive,bullet0", "riscv"; ++ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; +@@ -87,7 +87,7 @@ + }; + }; + cpu3: cpu@3 { +- compatible = "sifive,bullet0", "riscv"; ++ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; +@@ -111,7 +111,7 @@ + }; + }; + cpu4: cpu@4 { +- compatible = "sifive,bullet0", "riscv"; ++ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; diff --git a/target/linux/sifiveu/patches-6.1/0002-riscv-sifive-unmatched-update-regulators-values.patch b/target/linux/sifiveu/patches-6.1/0002-riscv-sifive-unmatched-update-regulators-values.patch new file mode 100644 index 00000000000..ac316e9d9b9 --- /dev/null +++ b/target/linux/sifiveu/patches-6.1/0002-riscv-sifive-unmatched-update-regulators-values.patch @@ -0,0 +1,104 @@ +From 657819ff477dd73cd71075609698aa57ba098d8c Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Wed, 15 Sep 2021 07:10:02 -0700 +Subject: [PATCH 2/7] riscv: sifive: unmatched: update regulators values + +These are the regulators values from the schematics for Rev3{A,B} boards. + +Note this is not fully correct as bcore1/bcore2 and bmem/bio are merged, but +it's only supported in v5.15 kernel. See: + +541ee8f640327f951e7039278057827322231ab0 ("regulator: da9063: Add support for +full-current mode.") + +This will be changed for v5.15 kernel based on the patch above. + +Signed-off-by: David Abdurachmanov +--- + .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 32 +++++++++++----------- + 1 file changed, 16 insertions(+), 16 deletions(-) + +--- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts ++++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts +@@ -73,16 +73,16 @@ + + regulators { + vdd_bcore1: bcore1 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; + regulator-min-microamp = <5000000>; + regulator-max-microamp = <5000000>; + regulator-always-on; + }; + + vdd_bcore2: bcore2 { +- regulator-min-microvolt = <900000>; +- regulator-max-microvolt = <900000>; ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; + regulator-min-microamp = <5000000>; + regulator-max-microamp = <5000000>; + regulator-always-on; +@@ -137,48 +137,48 @@ + }; + + vdd_ldo3: ldo3 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + vdd_ldo4: ldo4 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + vdd_ldo5: ldo5 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; + regulator-min-microamp = <100000>; + regulator-max-microamp = <100000>; + regulator-always-on; + }; + + vdd_ldo6: ldo6 { +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + vdd_ldo7: ldo7 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; + }; + + vdd_ldo8: ldo8 { +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-always-on; diff --git a/target/linux/sifiveu/patches-6.1/0003-riscv-sifive-unmatched-define-PWM-LEDs.patch b/target/linux/sifiveu/patches-6.1/0003-riscv-sifive-unmatched-define-PWM-LEDs.patch new file mode 100644 index 00000000000..661e15905f9 --- /dev/null +++ b/target/linux/sifiveu/patches-6.1/0003-riscv-sifive-unmatched-define-PWM-LEDs.patch @@ -0,0 +1,69 @@ +From 2c2d8ac8c124a2938c9326c14b2dffd46d76b4a8 Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Mon, 13 Sep 2021 02:15:37 -0700 +Subject: [PATCH 3/7] riscv: sifive: unmatched: define PWM LEDs + +Add D2 (RGB) and D12 (green) LEDs for SiFive Unmatched board. + +Signed-off-by: David Abdurachmanov +--- + .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 41 ++++++++++++++++++++++ + 1 file changed, 41 insertions(+) + +--- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts ++++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts +@@ -4,6 +4,8 @@ + #include "fu740-c000.dtsi" + #include + #include ++#include ++#include + + /* Clock frequency (in Hz) of the PCB crystal for rtcclk */ + #define RTCCLK_FREQ 1000000 +@@ -31,6 +33,45 @@ + soc { + }; + ++ pwmleds { ++ compatible = "pwm-leds"; ++ green-d12 { ++ label = "green:d12"; ++ color = ; ++ pwms = <&pwm0 0 7812500 PWM_POLARITY_INVERTED>; ++ active-low = <1>; ++ max-brightness = <255>; ++ linux,default-trigger = "none"; ++ }; ++ ++ green-d2 { ++ label = "green:d2"; ++ color = ; ++ pwms = <&pwm0 1 7812500 PWM_POLARITY_INVERTED>; ++ active-low = <1>; ++ max-brightness = <255>; ++ linux,default-trigger = "none"; ++ }; ++ ++ red-d2 { ++ label = "red:d2"; ++ color = ; ++ pwms = <&pwm0 2 7812500 PWM_POLARITY_INVERTED>; ++ active-low = <1>; ++ max-brightness = <255>; ++ linux,default-trigger = "none"; ++ }; ++ ++ blue-d2 { ++ label = "blue:d2"; ++ color = ; ++ pwms = <&pwm0 3 7812500 PWM_POLARITY_INVERTED>; ++ active-low = <1>; ++ max-brightness = <255>; ++ linux,default-trigger = "none"; ++ }; ++ }; ++ + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; diff --git a/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch b/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch new file mode 100644 index 00000000000..6d09628cb3b --- /dev/null +++ b/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch @@ -0,0 +1,26 @@ +From 14ede57943bc4209755d08daf93ac7be967d7fbe Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Mon, 13 Sep 2021 02:18:30 -0700 +Subject: [PATCH 4/7] riscv: sifive: unmatched: add gpio-poweroff node + +Add gpio-poweroff node to allow powering off the system. + +Signed-off-by: David Abdurachmanov +--- + arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts ++++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts +@@ -85,6 +85,11 @@ + clock-frequency = ; + clock-output-names = "rtcclk"; + }; ++ ++ gpio-poweroff { ++ compatible = "gpio-poweroff"; ++ gpios = <&gpio 2 GPIO_ACTIVE_LOW>; ++ }; + }; + + &uart0 { diff --git a/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch b/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch new file mode 100644 index 00000000000..c6b997dbbed --- /dev/null +++ b/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch @@ -0,0 +1,116 @@ +From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001 +From: David Abdurachmanov +Date: Fri, 14 May 2021 05:27:51 -0700 +Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq) + +Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4 + +Signed-off-by: David Abdurachmanov +--- + arch/riscv/Kconfig | 8 +++++ + arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 ++++ + .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++ + 3 files changed, 47 insertions(+) + +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -566,6 +566,14 @@ config BUILTIN_DTB + depends on OF + default y if XIP_KERNEL + ++menu "CPU Power Management" ++ ++source "drivers/cpuidle/Kconfig" ++ ++source "drivers/cpufreq/Kconfig" ++ ++endmenu ++ + menu "Power management options" + + source "kernel/power/Kconfig" +--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi ++++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +@@ -30,6 +30,7 @@ + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; ++ clocks = <&prci PRCI_CLK_COREPLL>; + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; +@@ -54,6 +55,7 @@ + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; ++ clocks = <&prci PRCI_CLK_COREPLL>; + next-level-cache = <&l2cache>; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; +@@ -78,6 +80,7 @@ + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; ++ clocks = <&prci PRCI_CLK_COREPLL>; + next-level-cache = <&l2cache>; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; +@@ -102,6 +105,7 @@ + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; ++ clocks = <&prci PRCI_CLK_COREPLL>; + next-level-cache = <&l2cache>; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; +@@ -126,6 +130,7 @@ + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; ++ clocks = <&prci PRCI_CLK_COREPLL>; + next-level-cache = <&l2cache>; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; +--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts ++++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts +@@ -84,6 +84,40 @@ + label = "d4"; + }; + }; ++ ++ fu540_c000_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-350000000 { ++ opp-hz = /bits/ 64 <350000000>; ++ }; ++ opp-700000000 { ++ opp-hz = /bits/ 64 <700000000>; ++ }; ++ opp-999999999 { ++ opp-hz = /bits/ 64 <999999999>; ++ }; ++ opp-1400000000 { ++ opp-hz = /bits/ 64 <1400000000>; ++ }; ++ }; ++}; ++ ++&cpu0 { ++ operating-points-v2 = <&fu540_c000_opp_table>; ++}; ++&cpu1 { ++ operating-points-v2 = <&fu540_c000_opp_table>; ++}; ++&cpu2 { ++ operating-points-v2 = <&fu540_c000_opp_table>; ++}; ++&cpu3 { ++ operating-points-v2 = <&fu540_c000_opp_table>; ++}; ++&cpu4 { ++ operating-points-v2 = <&fu540_c000_opp_table>; + }; + + &uart0 { diff --git a/target/linux/sifiveu/patches-6.1/0006-riscv-sbi-srst-support.patch b/target/linux/sifiveu/patches-6.1/0006-riscv-sbi-srst-support.patch new file mode 100644 index 00000000000..409001bcfa8 --- /dev/null +++ b/target/linux/sifiveu/patches-6.1/0006-riscv-sbi-srst-support.patch @@ -0,0 +1,301 @@ +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-21.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, + DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, + INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,MSGID_FROM_MTA_HEADER, + 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+X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR04MB7794 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20210609_051349_766689_30430D67 +X-CRM114-Status: GOOD ( 15.29 ) +X-BeenThere: linux-riscv@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Content-Type: text/plain; charset="us-ascii" +Content-Transfer-Encoding: 7bit +Sender: "linux-riscv" +Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org + +The SBI SRST extension provides a standard way to poweroff and +reboot the system irrespective to whether Linux RISC-V S-mode +is running natively (HS-mode) or inside Guest/VM (VS-mode). + +The SBI SRST extension is available in the SBI v0.3 specification. +(Refer, https://github.com/riscv/riscv-sbi-doc/releases/tag/v0.3.0-rc1) + +This patch extends Linux RISC-V SBI implementation to detect +and use SBI SRST extension. + +Signed-off-by: Anup Patel +Reviewed-by: Atish Patra +--- + arch/riscv/include/asm/sbi.h | 24 ++++++++++++++++++++++++ + arch/riscv/kernel/sbi.c | 35 +++++++++++++++++++++++++++++++++++ + 2 files changed, 59 insertions(+) + +--- a/arch/riscv/include/asm/sbi.h ++++ b/arch/riscv/include/asm/sbi.h +@@ -27,6 +27,7 @@ enum sbi_ext_id { + SBI_EXT_IPI = 0x735049, + SBI_EXT_RFENCE = 0x52464E43, + SBI_EXT_HSM = 0x48534D, ++ SBI_EXT_SRST = 0x53525354, + }; + + enum sbi_ext_base_fid { +@@ -70,6 +71,21 @@ enum sbi_hsm_hart_status { + SBI_HSM_HART_STATUS_STOP_PENDING, + }; + ++enum sbi_ext_srst_fid { ++ SBI_EXT_SRST_RESET = 0, ++}; ++ ++enum sbi_srst_reset_type { ++ SBI_SRST_RESET_TYPE_SHUTDOWN = 0, ++ SBI_SRST_RESET_TYPE_COLD_REBOOT, ++ SBI_SRST_RESET_TYPE_WARM_REBOOT, ++}; ++ ++enum sbi_srst_reset_reason { ++ SBI_SRST_RESET_REASON_NONE = 0, ++ SBI_SRST_RESET_REASON_SYS_FAILURE, ++}; ++ + #define SBI_SPEC_VERSION_DEFAULT 0x1 + #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 + #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f +@@ -148,6 +164,14 @@ static inline unsigned long sbi_minor_ve + return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK; + } + ++/* Make SBI version */ ++static inline unsigned long sbi_mk_version(unsigned long major, ++ unsigned long minor) ++{ ++ return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << ++ SBI_SPEC_VERSION_MAJOR_SHIFT) | minor; ++} ++ + int sbi_err_map_linux_errno(int err); + #else /* CONFIG_RISCV_SBI */ + static inline int sbi_remote_fence_i(const unsigned long *hart_mask) { return -1; } +--- a/arch/riscv/kernel/sbi.c ++++ b/arch/riscv/kernel/sbi.c +@@ -7,6 +7,7 @@ + + #include + #include ++#include + #include + #include + +@@ -501,6 +502,32 @@ int sbi_remote_hfence_vvma_asid(const un + } + EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid); + ++static void sbi_srst_reset(unsigned long type, unsigned long reason) ++{ ++ sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason, ++ 0, 0, 0, 0); ++ pr_warn("%s: type=0x%lx reason=0x%lx failed\n", ++ __func__, type, reason); ++} ++ ++static int sbi_srst_reboot(struct notifier_block *this, ++ unsigned long mode, void *cmd) ++{ ++ sbi_srst_reset((mode == REBOOT_WARM || mode == REBOOT_SOFT) ? ++ SBI_SRST_RESET_TYPE_WARM_REBOOT : ++ SBI_SRST_RESET_TYPE_COLD_REBOOT, ++ SBI_SRST_RESET_REASON_NONE); ++ return NOTIFY_DONE; ++} ++ ++static struct notifier_block sbi_srst_reboot_nb; ++ ++static void sbi_srst_power_off(void) ++{ ++ sbi_srst_reset(SBI_SRST_RESET_TYPE_SHUTDOWN, ++ SBI_SRST_RESET_REASON_NONE); ++} ++ + /** + * sbi_probe_extension() - Check if an SBI extension ID is supported or not. + * @extid: The extension ID to be probed. +@@ -608,6 +635,14 @@ void __init sbi_init(void) + } else { + __sbi_rfence = __sbi_rfence_v01; + } ++ if ((sbi_spec_version >= sbi_mk_version(0, 3)) && ++ (sbi_probe_extension(SBI_EXT_SRST) > 0)) { ++ pr_info("SBI SRST extension detected\n"); ++ pm_power_off = sbi_srst_power_off; ++ sbi_srst_reboot_nb.notifier_call = sbi_srst_reboot; ++ sbi_srst_reboot_nb.priority = 192; ++ register_restart_handler(&sbi_srst_reboot_nb); ++ } + } else { + __sbi_set_timer = __sbi_set_timer_v01; + __sbi_send_ipi = __sbi_send_ipi_v01; From 1871aa145b7123a2c048197c08a4d71920a1fed2 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Fri, 22 Sep 2023 18:29:57 +0200 Subject: [PATCH 24/30] sifiveu: add testing kernel 6.1 Compile-tested: HiFive Unleashed / Unmatched Runtime-tested: HiFive Unleashed / Unmatched Signed-off-by: Zoltan HERPAI --- target/linux/sifiveu/Makefile | 1 + target/linux/sifiveu/config-6.1 | 362 ++++++++++++++++++++++++++++++++ 2 files changed, 363 insertions(+) create mode 100644 target/linux/sifiveu/config-6.1 diff --git a/target/linux/sifiveu/Makefile b/target/linux/sifiveu/Makefile index f88164e7af3..43f70b5ce0d 100644 --- a/target/linux/sifiveu/Makefile +++ b/target/linux/sifiveu/Makefile @@ -12,6 +12,7 @@ KERNELNAME:=Image dtbs SUBTARGETS:=generic KERNEL_PATCHVER:=5.15 +KERNEL_TESTING_PATCHVER:=6.1 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/sifiveu/config-6.1 b/target/linux/sifiveu/config-6.1 new file mode 100644 index 00000000000..de3fe5b46f7 --- /dev/null +++ b/target/linux/sifiveu/config-6.1 @@ -0,0 +1,362 @@ +CONFIG_64BIT=y +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +# CONFIG_ARCH_RV32I is not set +CONFIG_ARCH_RV64I=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_ATA=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_CAVIUM_PTP=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y +CONFIG_CLK_SIFIVE=y +CONFIG_CLK_SIFIVE_PRCI=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CLZ_TAB=y +CONFIG_CMODEL_MEDANY=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_COMMON_CLK=y +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_COMPAT_BRK=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC7=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EDAC=y +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_SIFIVE=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EFI=y +CONFIG_EFIVAR_FS=m +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +CONFIG_EFI_EARLYCON=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_STUB=y +# CONFIG_EFI_TEST is not set +CONFIG_ELF_CORE=y +CONFIG_ERRATA_SIFIVE=y +CONFIG_ERRATA_SIFIVE_CIP_1200=y +CONFIG_ERRATA_SIFIVE_CIP_453=y +CONFIG_EXT4_FS=y +CONFIG_FAILOVER=y +CONFIG_FHANDLE=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_FONT_SUPPORT=y +CONFIG_FPU=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_INJECTION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_SIFIVE=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HID=y +CONFIG_HID_GENERIC=y +CONFIG_HOTPLUG_PCI=y +# CONFIG_HOTPLUG_PCI_CPCI is not set +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_HOTPLUG_PCI_SHPC=y +CONFIG_HVC_DRIVER=y +CONFIG_HVC_RISCV_SBI=y +CONFIG_HW_CONSOLE=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_OCORES=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IO_URING=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +CONFIG_KEYS=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LIBFDT=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_MACB=y +# CONFIG_MACB_PCI is not set +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MEMFD_CREATE=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MICROSEMI_PHY=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_CADENCE=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SPI=y +CONFIG_MMIOWB=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MODULE_SECTIONS=y +CONFIG_MPILIB=y +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_FAILOVER=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NR_CPUS=8 +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OID_REGISTRY=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xffffffe000000000 +CONFIG_PAGE_REPORTING=y +CONFIG_PA_BITS=56 +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEAER_INJECT=m +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DPC=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_ECRC=y +CONFIG_PCIE_FU740=y +CONFIG_PCIE_PTM=y +CONFIG_PCIE_XILINX=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_SW_SWITCHTEC=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHYS_RAM_BASE_FIXED is not set +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_PPS=y +CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_PWM_SIFIVE=y +CONFIG_PWM_SYSFS=y +CONFIG_RATIONAL=y +CONFIG_RCU_TRACE=y +CONFIG_RD_GZIP=y +CONFIG_REALTEK_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +# CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SIMPLE=y +CONFIG_RFS_ACCEL=y +CONFIG_RISCV=y +CONFIG_RISCV_ERRATA_ALTERNATIVE=y +CONFIG_RISCV_INTC=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_SBI=y +CONFIG_RISCV_SBI_V01=y +CONFIG_RISCV_TIMER=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_EFI is not set +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_DEBUG=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SG_POOL=y +CONFIG_SIFIVE_L2=y +CONFIG_SIFIVE_PLIC=y +CONFIG_SLUB_DEBUG=y +CONFIG_SMP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +# CONFIG_SOC_MICROCHIP_POLARFIRE is not set +CONFIG_SOC_SIFIVE=y +# CONFIG_SOC_VIRT is not set +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_SIFIVE=y +CONFIG_SRCU=y +CONFIG_STACKTRACE=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TRACE_CLOCK=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_TUNE_GENERIC=y +CONFIG_UCS2_STRING=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_HID=y +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_PCI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +# CONFIG_USB_UHCI_HCD is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_VA_BITS=39 +CONFIG_VFAT_FS=y +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_VMAP_STACK=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y From d9a8747a3dd7608c1ace77a85fb38e43c497129c Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Fri, 22 Sep 2023 19:47:01 +0200 Subject: [PATCH 25/30] sifiveu: remove upstreamed patches, refresh remaining ones Upstreamed: 0002-riscv-sifive-unmatched-update-regulators-values.patch 0003-riscv-sifive-unmatched-define-PWM-LEDs.patch 0006-riscv-sbi-srst-support.patch Compile-tested: HiFive Unleashed / Unmatched Runtime-tested: HiFive Unleashed / Unmatched Signed-off-by: Zoltan HERPAI --- ...e-unmatched-update-regulators-values.patch | 104 ------ ...scv-sifive-unmatched-define-PWM-LEDs.patch | 69 ---- ...ive-unmatched-add-gpio-poweroff-node.patch | 6 +- ...e-unleashed-define-opp-table-cpufreq.patch | 18 +- .../0006-riscv-sbi-srst-support.patch | 301 ------------------ 5 files changed, 12 insertions(+), 486 deletions(-) delete mode 100644 target/linux/sifiveu/patches-6.1/0002-riscv-sifive-unmatched-update-regulators-values.patch delete mode 100644 target/linux/sifiveu/patches-6.1/0003-riscv-sifive-unmatched-define-PWM-LEDs.patch delete mode 100644 target/linux/sifiveu/patches-6.1/0006-riscv-sbi-srst-support.patch diff --git a/target/linux/sifiveu/patches-6.1/0002-riscv-sifive-unmatched-update-regulators-values.patch b/target/linux/sifiveu/patches-6.1/0002-riscv-sifive-unmatched-update-regulators-values.patch deleted file mode 100644 index ac316e9d9b9..00000000000 --- a/target/linux/sifiveu/patches-6.1/0002-riscv-sifive-unmatched-update-regulators-values.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 657819ff477dd73cd71075609698aa57ba098d8c Mon Sep 17 00:00:00 2001 -From: David Abdurachmanov -Date: Wed, 15 Sep 2021 07:10:02 -0700 -Subject: [PATCH 2/7] riscv: sifive: unmatched: update regulators values - -These are the regulators values from the schematics for Rev3{A,B} boards. - -Note this is not fully correct as bcore1/bcore2 and bmem/bio are merged, but -it's only supported in v5.15 kernel. See: - -541ee8f640327f951e7039278057827322231ab0 ("regulator: da9063: Add support for -full-current mode.") - -This will be changed for v5.15 kernel based on the patch above. - -Signed-off-by: David Abdurachmanov ---- - .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 32 +++++++++++----------- - 1 file changed, 16 insertions(+), 16 deletions(-) - ---- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -@@ -73,16 +73,16 @@ - - regulators { - vdd_bcore1: bcore1 { -- regulator-min-microvolt = <900000>; -- regulator-max-microvolt = <900000>; -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; - regulator-min-microamp = <5000000>; - regulator-max-microamp = <5000000>; - regulator-always-on; - }; - - vdd_bcore2: bcore2 { -- regulator-min-microvolt = <900000>; -- regulator-max-microvolt = <900000>; -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; - regulator-min-microamp = <5000000>; - regulator-max-microamp = <5000000>; - regulator-always-on; -@@ -137,48 +137,48 @@ - }; - - vdd_ldo3: ldo3 { -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; - regulator-always-on; - }; - - vdd_ldo4: ldo4 { -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <2500000>; -+ regulator-max-microvolt = <2500000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; - regulator-always-on; - }; - - vdd_ldo5: ldo5 { -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; - regulator-min-microamp = <100000>; - regulator-max-microamp = <100000>; - regulator-always-on; - }; - - vdd_ldo6: ldo6 { -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; - regulator-always-on; - }; - - vdd_ldo7: ldo7 { -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; - regulator-always-on; - }; - - vdd_ldo8: ldo8 { -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; - regulator-min-microamp = <200000>; - regulator-max-microamp = <200000>; - regulator-always-on; diff --git a/target/linux/sifiveu/patches-6.1/0003-riscv-sifive-unmatched-define-PWM-LEDs.patch b/target/linux/sifiveu/patches-6.1/0003-riscv-sifive-unmatched-define-PWM-LEDs.patch deleted file mode 100644 index 661e15905f9..00000000000 --- a/target/linux/sifiveu/patches-6.1/0003-riscv-sifive-unmatched-define-PWM-LEDs.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 2c2d8ac8c124a2938c9326c14b2dffd46d76b4a8 Mon Sep 17 00:00:00 2001 -From: David Abdurachmanov -Date: Mon, 13 Sep 2021 02:15:37 -0700 -Subject: [PATCH 3/7] riscv: sifive: unmatched: define PWM LEDs - -Add D2 (RGB) and D12 (green) LEDs for SiFive Unmatched board. - -Signed-off-by: David Abdurachmanov ---- - .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 41 ++++++++++++++++++++++ - 1 file changed, 41 insertions(+) - ---- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -@@ -4,6 +4,8 @@ - #include "fu740-c000.dtsi" - #include - #include -+#include -+#include - - /* Clock frequency (in Hz) of the PCB crystal for rtcclk */ - #define RTCCLK_FREQ 1000000 -@@ -31,6 +33,45 @@ - soc { - }; - -+ pwmleds { -+ compatible = "pwm-leds"; -+ green-d12 { -+ label = "green:d12"; -+ color = ; -+ pwms = <&pwm0 0 7812500 PWM_POLARITY_INVERTED>; -+ active-low = <1>; -+ max-brightness = <255>; -+ linux,default-trigger = "none"; -+ }; -+ -+ green-d2 { -+ label = "green:d2"; -+ color = ; -+ pwms = <&pwm0 1 7812500 PWM_POLARITY_INVERTED>; -+ active-low = <1>; -+ max-brightness = <255>; -+ linux,default-trigger = "none"; -+ }; -+ -+ red-d2 { -+ label = "red:d2"; -+ color = ; -+ pwms = <&pwm0 2 7812500 PWM_POLARITY_INVERTED>; -+ active-low = <1>; -+ max-brightness = <255>; -+ linux,default-trigger = "none"; -+ }; -+ -+ blue-d2 { -+ label = "blue:d2"; -+ color = ; -+ pwms = <&pwm0 3 7812500 PWM_POLARITY_INVERTED>; -+ active-low = <1>; -+ max-brightness = <255>; -+ linux,default-trigger = "none"; -+ }; -+ }; -+ - hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; diff --git a/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch b/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch index 6d09628cb3b..07170d7c769 100644 --- a/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch +++ b/target/linux/sifiveu/patches-6.1/0004-riscv-sifive-unmatched-add-gpio-poweroff-node.patch @@ -12,9 +12,9 @@ Signed-off-by: David Abdurachmanov --- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts +++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts -@@ -85,6 +85,11 @@ - clock-frequency = ; - clock-output-names = "rtcclk"; +@@ -86,6 +86,11 @@ + }; + }; }; + + gpio-poweroff { diff --git a/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch b/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch index c6b997dbbed..c4242c6f07d 100644 --- a/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch +++ b/target/linux/sifiveu/patches-6.1/0005-riscv-sifive-unleashed-define-opp-table-cpufreq.patch @@ -14,9 +14,9 @@ Signed-off-by: David Abdurachmanov --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig -@@ -566,6 +566,14 @@ config BUILTIN_DTB - depends on OF - default y if XIP_KERNEL +@@ -711,6 +711,14 @@ config PORTABLE + select OF + select MMU +menu "CPU Power Management" + @@ -35,7 +35,7 @@ Signed-off-by: David Abdurachmanov i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; -+ clocks = <&prci PRCI_CLK_COREPLL>; ++ clocks = <&prci FU540_PRCI_CLK_COREPLL>; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -43,7 +43,7 @@ Signed-off-by: David Abdurachmanov reg = <1>; riscv,isa = "rv64imafdc"; tlb-split; -+ clocks = <&prci PRCI_CLK_COREPLL>; ++ clocks = <&prci FU540_PRCI_CLK_COREPLL>; next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; @@ -51,7 +51,7 @@ Signed-off-by: David Abdurachmanov reg = <2>; riscv,isa = "rv64imafdc"; tlb-split; -+ clocks = <&prci PRCI_CLK_COREPLL>; ++ clocks = <&prci FU540_PRCI_CLK_COREPLL>; next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; @@ -59,7 +59,7 @@ Signed-off-by: David Abdurachmanov reg = <3>; riscv,isa = "rv64imafdc"; tlb-split; -+ clocks = <&prci PRCI_CLK_COREPLL>; ++ clocks = <&prci FU540_PRCI_CLK_COREPLL>; next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; @@ -67,13 +67,13 @@ Signed-off-by: David Abdurachmanov reg = <4>; riscv,isa = "rv64imafdc"; tlb-split; -+ clocks = <&prci PRCI_CLK_COREPLL>; ++ clocks = <&prci FU540_PRCI_CLK_COREPLL>; next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; --- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts -@@ -84,6 +84,40 @@ +@@ -80,6 +80,40 @@ label = "d4"; }; }; diff --git a/target/linux/sifiveu/patches-6.1/0006-riscv-sbi-srst-support.patch b/target/linux/sifiveu/patches-6.1/0006-riscv-sbi-srst-support.patch deleted file mode 100644 index 409001bcfa8..00000000000 --- a/target/linux/sifiveu/patches-6.1/0006-riscv-sbi-srst-support.patch +++ /dev/null @@ -1,301 +0,0 @@ -From mboxrd@z Thu Jan 1 00:00:00 1970 -Return-Path: -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -X-Spam-Level: -X-Spam-Status: No, score=-21.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, - DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, - INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,MSGID_FROM_MTA_HEADER, - SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable - autolearn_force=no version=3.4.0 -Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) - by smtp.lore.kernel.org (Postfix) with ESMTP id 9A34CC48BCD - for ; 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Wed, 9 Jun 2021 - 12:13:47 +0000 -From: Anup Patel -To: Palmer Dabbelt , - Palmer Dabbelt , - Paul Walmsley , Albert Ou -Cc: Atish Patra , - Alistair Francis , - Anup Patel , linux-riscv@lists.infradead.org, - linux-kernel@vger.kernel.org, Anup Patel -Subject: [PATCH v7 1/1] RISC-V: Use SBI SRST extension when available -Date: Wed, 9 Jun 2021 17:43:22 +0530 -Message-Id: <20210609121322.3058-2-anup.patel@wdc.com> -X-Mailer: git-send-email 2.25.1 -In-Reply-To: <20210609121322.3058-1-anup.patel@wdc.com> -References: <20210609121322.3058-1-anup.patel@wdc.com> -X-Originating-IP: [122.172.176.125] -X-ClientProxiedBy: MA1PR0101CA0036.INDPRD01.PROD.OUTLOOK.COM - (2603:1096:a00:22::22) To CO6PR04MB7812.namprd04.prod.outlook.com - (2603:10b6:303:138::6) -MIME-Version: 1.0 -X-MS-Exchange-MessageSentRepresentingType: 1 -Received: from wdc.com (122.172.176.125) by - MA1PR0101CA0036.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::22) with - Microsoft SMTP Server (version=TLS1_2, - cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.21 via Frontend - Transport; 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charset="us-ascii" -Content-Transfer-Encoding: 7bit -Sender: "linux-riscv" -Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org - -The SBI SRST extension provides a standard way to poweroff and -reboot the system irrespective to whether Linux RISC-V S-mode -is running natively (HS-mode) or inside Guest/VM (VS-mode). - -The SBI SRST extension is available in the SBI v0.3 specification. -(Refer, https://github.com/riscv/riscv-sbi-doc/releases/tag/v0.3.0-rc1) - -This patch extends Linux RISC-V SBI implementation to detect -and use SBI SRST extension. - -Signed-off-by: Anup Patel -Reviewed-by: Atish Patra ---- - arch/riscv/include/asm/sbi.h | 24 ++++++++++++++++++++++++ - arch/riscv/kernel/sbi.c | 35 +++++++++++++++++++++++++++++++++++ - 2 files changed, 59 insertions(+) - ---- a/arch/riscv/include/asm/sbi.h -+++ b/arch/riscv/include/asm/sbi.h -@@ -27,6 +27,7 @@ enum sbi_ext_id { - SBI_EXT_IPI = 0x735049, - SBI_EXT_RFENCE = 0x52464E43, - SBI_EXT_HSM = 0x48534D, -+ SBI_EXT_SRST = 0x53525354, - }; - - enum sbi_ext_base_fid { -@@ -70,6 +71,21 @@ enum sbi_hsm_hart_status { - SBI_HSM_HART_STATUS_STOP_PENDING, - }; - -+enum sbi_ext_srst_fid { -+ SBI_EXT_SRST_RESET = 0, -+}; -+ -+enum sbi_srst_reset_type { -+ SBI_SRST_RESET_TYPE_SHUTDOWN = 0, -+ SBI_SRST_RESET_TYPE_COLD_REBOOT, -+ SBI_SRST_RESET_TYPE_WARM_REBOOT, -+}; -+ -+enum sbi_srst_reset_reason { -+ SBI_SRST_RESET_REASON_NONE = 0, -+ SBI_SRST_RESET_REASON_SYS_FAILURE, -+}; -+ - #define SBI_SPEC_VERSION_DEFAULT 0x1 - #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 - #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f -@@ -148,6 +164,14 @@ static inline unsigned long sbi_minor_ve - return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK; - } - -+/* Make SBI version */ -+static inline unsigned long sbi_mk_version(unsigned long major, -+ unsigned long minor) -+{ -+ return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << -+ SBI_SPEC_VERSION_MAJOR_SHIFT) | minor; -+} -+ - int sbi_err_map_linux_errno(int err); - #else /* CONFIG_RISCV_SBI */ - static inline int sbi_remote_fence_i(const unsigned long *hart_mask) { return -1; } ---- a/arch/riscv/kernel/sbi.c -+++ b/arch/riscv/kernel/sbi.c -@@ -7,6 +7,7 @@ - - #include - #include -+#include - #include - #include - -@@ -501,6 +502,32 @@ int sbi_remote_hfence_vvma_asid(const un - } - EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid); - -+static void sbi_srst_reset(unsigned long type, unsigned long reason) -+{ -+ sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason, -+ 0, 0, 0, 0); -+ pr_warn("%s: type=0x%lx reason=0x%lx failed\n", -+ __func__, type, reason); -+} -+ -+static int sbi_srst_reboot(struct notifier_block *this, -+ unsigned long mode, void *cmd) -+{ -+ sbi_srst_reset((mode == REBOOT_WARM || mode == REBOOT_SOFT) ? -+ SBI_SRST_RESET_TYPE_WARM_REBOOT : -+ SBI_SRST_RESET_TYPE_COLD_REBOOT, -+ SBI_SRST_RESET_REASON_NONE); -+ return NOTIFY_DONE; -+} -+ -+static struct notifier_block sbi_srst_reboot_nb; -+ -+static void sbi_srst_power_off(void) -+{ -+ sbi_srst_reset(SBI_SRST_RESET_TYPE_SHUTDOWN, -+ SBI_SRST_RESET_REASON_NONE); -+} -+ - /** - * sbi_probe_extension() - Check if an SBI extension ID is supported or not. - * @extid: The extension ID to be probed. -@@ -608,6 +635,14 @@ void __init sbi_init(void) - } else { - __sbi_rfence = __sbi_rfence_v01; - } -+ if ((sbi_spec_version >= sbi_mk_version(0, 3)) && -+ (sbi_probe_extension(SBI_EXT_SRST) > 0)) { -+ pr_info("SBI SRST extension detected\n"); -+ pm_power_off = sbi_srst_power_off; -+ sbi_srst_reboot_nb.notifier_call = sbi_srst_reboot; -+ sbi_srst_reboot_nb.priority = 192; -+ register_restart_handler(&sbi_srst_reboot_nb); -+ } - } else { - __sbi_set_timer = __sbi_set_timer_v01; - __sbi_send_ipi = __sbi_send_ipi_v01; From 10867ec4bc170709f89595ec4c3a2c7d9a7b13d2 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sat, 23 Sep 2023 17:28:55 +0200 Subject: [PATCH 26/30] sifiveu: refresh 6.1 config Add new config symbols as required. Signed-off-by: Zoltan HERPAI --- target/linux/sifiveu/config-6.1 | 51 +++++++++++++++++++++------------ 1 file changed, 33 insertions(+), 18 deletions(-) diff --git a/target/linux/sifiveu/config-6.1 b/target/linux/sifiveu/config-6.1 index de3fe5b46f7..7d865bf4c0f 100644 --- a/target/linux/sifiveu/config-6.1 +++ b/target/linux/sifiveu/config-6.1 @@ -4,19 +4,19 @@ CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_ARCH_MMAP_RND_BITS_MAX=24 CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -# CONFIG_ARCH_RV32I is not set CONFIG_ARCH_RV64I=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_ATA=y CONFIG_ATA_VERBOSE_ERROR=y CONFIG_BLK_DEV_SD=y CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_MQ_VIRTIO=y CONFIG_CAVIUM_PTP=y CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y @@ -27,6 +27,7 @@ CONFIG_CLZ_TAB=y CONFIG_CMODEL_MEDANY=y # CONFIG_CMODEL_MEDLOW is not set CONFIG_COMMON_CLK=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 # CONFIG_COMPAT_32BIT_TIME is not set CONFIG_COMPAT_BRK=y CONFIG_CONSOLE_TRANSLATIONS=y @@ -44,7 +45,6 @@ CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_DRBG_HMAC=y CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 @@ -71,7 +71,9 @@ CONFIG_EFI=y CONFIG_EFIVAR_FS=m # CONFIG_EFI_BOOTLOADER_CONTROL is not set # CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_COCO_SECRET is not set # CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set CONFIG_EFI_EARLYCON=y CONFIG_EFI_ESRT=y CONFIG_EFI_GENERIC_STUB=y @@ -79,12 +81,16 @@ CONFIG_EFI_PARAMS_FROM_FDT=y CONFIG_EFI_RUNTIME_WRAPPERS=y CONFIG_EFI_STUB=y # CONFIG_EFI_TEST is not set +# CONFIG_EFI_ZBOOT is not set CONFIG_ELF_CORE=y CONFIG_ERRATA_SIFIVE=y CONFIG_ERRATA_SIFIVE_CIP_1200=y CONFIG_ERRATA_SIFIVE_CIP_453=y +# CONFIG_ERRATA_THEAD is not set +CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_EXT4_FS=y CONFIG_FAILOVER=y +CONFIG_FAT_FS=y CONFIG_FHANDLE=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y @@ -97,6 +103,8 @@ CONFIG_FS_IOMAP=y CONFIG_FS_MBCACHE=y CONFIG_FWNODE_MDIO=y CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC11_NO_ARRAY_BOUNDS=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y CONFIG_GENERIC_BUG=y @@ -108,6 +116,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_IRQ_INJECTION=y CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_IRQ_SHOW=y @@ -122,13 +131,12 @@ CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GLOB=y -CONFIG_GPIOLIB=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y CONFIG_GPIO_SIFIVE=y -CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y @@ -141,6 +149,7 @@ CONFIG_HOTPLUG_PCI_SHPC=y CONFIG_HVC_DRIVER=y CONFIG_HVC_RISCV_SBI=y CONFIG_HW_CONSOLE=y +CONFIG_HZ_PERIODIC=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y @@ -174,7 +183,6 @@ CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y CONFIG_MEMFD_CREATE=y -CONFIG_MFD_CORE=y CONFIG_MFD_SYSCON=y CONFIG_MICROSEMI_PHY=y CONFIG_MIGRATION=y @@ -202,11 +210,13 @@ CONFIG_NET_SELFTESTS=y CONFIG_NLS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y +# CONFIG_NONPORTABLE is not set CONFIG_NR_CPUS=8 CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y CONFIG_OF=y CONFIG_OF_ADDRESS=y +CONFIG_OF_DMA_DEFAULT_COHERENT=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_FLATTREE=y CONFIG_OF_GPIO=y @@ -215,9 +225,11 @@ CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y CONFIG_OID_REGISTRY=y CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xffffffe000000000 +CONFIG_PAGE_OFFSET=0xff60000000000000 +CONFIG_PAGE_POOL=y CONFIG_PAGE_REPORTING=y -CONFIG_PA_BITS=56 +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PCI=y CONFIG_PCIEAER=y CONFIG_PCIEAER_INJECT=m @@ -243,11 +255,12 @@ CONFIG_PCI_HOST_GENERIC=y CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_SW_SWITCHTEC=y -CONFIG_PGTABLE_LEVELS=3 +CONFIG_PGTABLE_LEVELS=5 CONFIG_PHYLIB=y CONFIG_PHYLINK=y CONFIG_PHYS_ADDR_T_64BIT=y -# CONFIG_PHYS_RAM_BASE_FIXED is not set +CONFIG_PORTABLE=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_GPIO_RESTART=y @@ -266,21 +279,21 @@ CONFIG_RCU_TRACE=y CONFIG_RD_GZIP=y CONFIG_REALTEK_PHY=y CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_IRQ=y CONFIG_REGMAP_MMIO=y # CONFIG_RESET_ATTACK_MITIGATION is not set CONFIG_RESET_CONTROLLER=y CONFIG_RESET_SIMPLE=y -CONFIG_RFS_ACCEL=y CONFIG_RISCV=y -CONFIG_RISCV_ERRATA_ALTERNATIVE=y +CONFIG_RISCV_ALTERNATIVE=y +# CONFIG_RISCV_BOOT_SPINWAIT is not set +CONFIG_RISCV_DMA_NONCOHERENT=y CONFIG_RISCV_INTC=y CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_RISCV_ISA_ZICBOM=y CONFIG_RISCV_SBI=y CONFIG_RISCV_SBI_V01=y CONFIG_RISCV_TIMER=y -CONFIG_RPS=y CONFIG_RTC_CLASS=y # CONFIG_RTC_DRV_EFI is not set CONFIG_RTC_I2C_AND_SPI=y @@ -301,13 +314,14 @@ CONFIG_SERIAL_SIFIVE_CONSOLE=y CONFIG_SERIO=y CONFIG_SERIO_SERPORT=y CONFIG_SG_POOL=y -CONFIG_SIFIVE_L2=y +CONFIG_SIFIVE_CCACHE=y CONFIG_SIFIVE_PLIC=y CONFIG_SLUB_DEBUG=y CONFIG_SMP=y CONFIG_SOCK_RX_QUEUE_MAPPING=y # CONFIG_SOC_MICROCHIP_POLARFIRE is not set CONFIG_SOC_SIFIVE=y +# CONFIG_SOC_STARFIVE is not set # CONFIG_SOC_VIRT is not set CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSE_IRQ=y @@ -321,12 +335,14 @@ CONFIG_STACKTRACE=y CONFIG_SWIOTLB=y CONFIG_SWPHY=y CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSFB=y # CONFIG_SYSFB_SIMPLEFB is not set CONFIG_THREAD_INFO_IN_TASK=y CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y +CONFIG_TOOLCHAIN_HAS_ZICBOM=y +CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y CONFIG_TRACE_CLOCK=y CONFIG_TREE_RCU=y CONFIG_TREE_SRCU=y @@ -347,7 +363,6 @@ CONFIG_USB_SUPPORT=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y # CONFIG_USB_XHCI_PLATFORM is not set -CONFIG_VA_BITS=39 CONFIG_VFAT_FS=y CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 From eb273ef640674de1b5c1dba8a35bf7be044016f8 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 18 Sep 2023 21:28:01 +0800 Subject: [PATCH 27/30] uboot-mediatek: sync spi-nand driver with SDK When adding new router support, I found that uboot could not recognize flash: "unknown raw ID xxx". Sync SPI-NAND driver for mediatek to fixes this: * Add support for Winbond W25N01KV 1Gbit chip. * Add support for Etron SPI-NAND chip. Signed-off-by: Chukun Pan --- ...i-nand-backport-from-upstream-kernel.patch | 270 +++++++++++++++--- 1 file changed, 232 insertions(+), 38 deletions(-) diff --git a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch index 358461a2b70..0e233bb1d29 100644 --- a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch +++ b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch @@ -1,4 +1,4 @@ -From a3c5878599d530330027412eb8be12f816ac215c Mon Sep 17 00:00:00 2001 +From 8d0665327819c41fce2c8d50f19c967b22eae564 Mon Sep 17 00:00:00 2001 From: Weijie Gao Date: Wed, 27 Jul 2022 16:36:13 +0800 Subject: [PATCH 57/71] mtd: spi-nand: backport from upstream kernel @@ -7,30 +7,34 @@ Backport new features from upstream kernel Signed-off-by: Weijie Gao --- - drivers/mtd/nand/spi/Kconfig | 8 + - drivers/mtd/nand/spi/core.c | 101 ++++++---- + drivers/mtd/nand/spi/Kconfig | 1 + + drivers/mtd/nand/spi/Makefile | 2 +- + drivers/mtd/nand/spi/core.c | 102 ++++++---- + drivers/mtd/nand/spi/etron.c | 181 +++++++++++++++++ drivers/mtd/nand/spi/gigadevice.c | 322 ++++++++++++++++++++++++++---- drivers/mtd/nand/spi/macronix.c | 173 +++++++++++++--- drivers/mtd/nand/spi/micron.c | 50 ++--- drivers/mtd/nand/spi/toshiba.c | 66 +++--- - drivers/mtd/nand/spi/winbond.c | 171 +++++++++++++--- - include/linux/mtd/spinand.h | 86 +++++--- - 8 files changed, 753 insertions(+), 224 deletions(-) + drivers/mtd/nand/spi/winbond.c | 164 ++++++++++++--- + include/linux/mtd/spinand.h | 87 +++++--- + 10 files changed, 923 insertions(+), 225 deletions(-) + create mode 100644 drivers/mtd/nand/spi/etron.c --- a/drivers/mtd/nand/spi/Kconfig +++ b/drivers/mtd/nand/spi/Kconfig -@@ -5,3 +5,11 @@ menuconfig MTD_SPI_NAND +@@ -5,3 +5,4 @@ menuconfig MTD_SPI_NAND select SPI_MEM help This is the framework for the SPI NAND device drivers. + -+config MTD_SPI_NAND_W25N01KV -+ tristate "Winbond W25N01KV Support" -+ select MTD_SPI_NAND -+ default n -+ help -+ Winbond W25N01KV share the same ID with W25N01GV. However, they have -+ different attributes. +--- a/drivers/mtd/nand/spi/Makefile ++++ b/drivers/mtd/nand/spi/Makefile +@@ -1,4 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 + +-spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o ++spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o etron.o + obj-$(CONFIG_MTD_SPI_NAND) += spinand.o --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -17,6 +17,7 @@ @@ -75,7 +79,15 @@ Signed-off-by: Weijie Gao static int spinand_lock_block(struct spinand_device *spinand, u8 lock) { return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock); -@@ -836,24 +826,63 @@ static const struct spinand_manufacturer +@@ -829,6 +819,7 @@ static const struct nand_ops spinand_ops + }; + + static const struct spinand_manufacturer *spinand_manufacturers[] = { ++ &etron_spinand_manufacturer, + &gigadevice_spinand_manufacturer, + ¯onix_spinand_manufacturer, + µn_spinand_manufacturer, +@@ -836,24 +827,63 @@ static const struct spinand_manufacturer &winbond_spinand_manufacturer, }; @@ -147,7 +159,7 @@ Signed-off-by: Weijie Gao static int spinand_manufacturer_init(struct spinand_device *spinand) { if (spinand->manufacturer->ops->init) -@@ -909,9 +938,9 @@ spinand_select_op_variant(struct spinand +@@ -909,9 +939,9 @@ spinand_select_op_variant(struct spinand * @spinand: SPI NAND object * @table: SPI NAND device description table * @table_size: size of the device description table @@ -159,7 +171,7 @@ Signed-off-by: Weijie Gao * entry in the SPI NAND description table. If a match is found, the spinand * object will be initialized with information provided by the matching * spinand_info entry. -@@ -920,8 +949,10 @@ spinand_select_op_variant(struct spinand +@@ -920,8 +950,10 @@ spinand_select_op_variant(struct spinand */ int spinand_match_and_init(struct spinand_device *spinand, const struct spinand_info *table, @@ -171,7 +183,7 @@ Signed-off-by: Weijie Gao struct nand_device *nand = spinand_to_nand(spinand); unsigned int i; -@@ -929,13 +960,17 @@ int spinand_match_and_init(struct spinan +@@ -929,13 +961,17 @@ int spinand_match_and_init(struct spinan const struct spinand_info *info = &table[i]; const struct spi_mem_op *op; @@ -190,7 +202,7 @@ Signed-off-by: Weijie Gao spinand->select_target = table[i].select_target; op = spinand_select_op_variant(spinand, -@@ -967,17 +1002,7 @@ static int spinand_detect(struct spinand +@@ -967,17 +1003,7 @@ static int spinand_detect(struct spinand struct nand_device *nand = spinand_to_nand(spinand); int ret; @@ -209,6 +221,190 @@ Signed-off-by: Weijie Gao if (ret) { dev_err(spinand->slave->dev, "unknown raw ID %02x %02x %02x %02x\n", spinand->id.data[0], spinand->id.data[1], +--- /dev/null ++++ b/drivers/mtd/nand/spi/etron.c +@@ -0,0 +1,181 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2020 Etron Technology, Inc. ++ * ++ */ ++#ifndef __UBOOT__ ++#include ++#include ++#include ++#endif ++#include ++#include ++ ++#define SPINAND_MFR_ETRON 0xD5 ++ ++#define STATUS_ECC_LIMIT_BITFLIPS (3 << 4) ++ ++static SPINAND_OP_VARIANTS(read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(write_cache_variants, ++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD(true, 0, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(update_cache_variants, ++ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), ++ SPINAND_PROG_LOAD(false, 0, NULL, 0)); ++ ++static int etron_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (14 * section) + 72; ++ region->length = 14; ++ ++ return 0; ++} ++ ++static int etron_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ if (section) { ++ region->offset = 18 * section; ++ region->length = 18; ++ } else { ++ /* section 0 has one byte reserved for bad block mark */ ++ region->offset = 2; ++ region->length = 16; ++ } ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops etron_ooblayout = { ++ .ecc = etron_ooblayout_ecc, ++ .rfree = etron_ooblayout_free, ++}; ++ ++static int etron_ecc_get_status(struct spinand_device *spinand, ++ u8 status) ++{ ++ struct nand_device *nand = spinand_to_nand(spinand); ++ ++ switch (status & STATUS_ECC_MASK) { ++ case STATUS_ECC_NO_BITFLIPS: ++ return 0; ++ ++ case STATUS_ECC_UNCOR_ERROR: ++ return -EBADMSG; ++ ++ case STATUS_ECC_HAS_BITFLIPS: ++ return nand->eccreq.strength >> 1; ++ ++ case STATUS_ECC_LIMIT_BITFLIPS: ++ return nand->eccreq.strength; ++ ++ default: ++ break; ++ } ++ ++ return -EINVAL; ++} ++ ++static const struct spinand_info etron_spinand_table[] = { ++ /* EM73C 1Gb 3.3V */ ++ SPINAND_INFO("EM73C044VCF", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x25), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++ /* EM7xD 2Gb */ ++ SPINAND_INFO("EM73D044VCR", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++ SPINAND_INFO("EM73D044VCO", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3A), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++ SPINAND_INFO("EM78D044VCM", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8E), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++ /* EM7xE 4Gb */ ++ SPINAND_INFO("EM73E044VCE", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++ SPINAND_INFO("EM78E044VCD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8F), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++ /* EM7xF044VCA 8Gb */ ++ SPINAND_INFO("EM73F044VCA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15), ++ NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++ SPINAND_INFO("EM78F044VCA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x8D), ++ NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++}; ++ ++static const struct spinand_manufacturer_ops etron_spinand_manuf_ops = { ++}; ++ ++const struct spinand_manufacturer etron_spinand_manufacturer = { ++ .id = SPINAND_MFR_ETRON, ++ .name = "Etron", ++ .chips = etron_spinand_table, ++ .nchips = ARRAY_SIZE(etron_spinand_table), ++ .ops = &etron_spinand_manuf_ops, ++}; --- a/drivers/mtd/nand/spi/gigadevice.c +++ b/drivers/mtd/nand/spi/gigadevice.c @@ -22,8 +22,13 @@ @@ -1153,7 +1349,7 @@ Signed-off-by: Weijie Gao }; --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c -@@ -19,6 +19,25 @@ +@@ -19,6 +19,23 @@ #define WINBOND_CFG_BUF_READ BIT(3) @@ -1168,18 +1364,16 @@ Signed-off-by: Weijie Gao +#define W25N01_M02GV_STATUS_ECC_1_BITFLIPS (1 << 4) +#define W25N01_M02GV_STATUS_ECC_UNCOR_ERROR (2 << 4) + -+#if IS_ENABLED(CONFIG_MTD_SPI_NAND_W25N01KV) +#define W25N01KV_STATUS_ECC_MASK (3 << 4) +#define W25N01KV_STATUS_ECC_NO_BITFLIPS (0 << 4) +#define W25N01KV_STATUS_ECC_1_3_BITFLIPS (1 << 4) +#define W25N01KV_STATUS_ECC_4_BITFLIPS (3 << 4) +#define W25N01KV_STATUS_ECC_UNCOR_ERROR (2 << 4) -+#endif + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), -@@ -35,6 +54,35 @@ static SPINAND_OP_VARIANTS(update_cache_ +@@ -35,6 +52,35 @@ static SPINAND_OP_VARIANTS(update_cache_ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), SPINAND_PROG_LOAD(false, 0, NULL, 0)); @@ -1215,11 +1409,10 @@ Signed-off-by: Weijie Gao static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *region) { -@@ -78,8 +126,63 @@ static int w25m02gv_select_target(struct +@@ -78,8 +124,61 @@ static int w25m02gv_select_target(struct return spi_mem_exec_op(spinand->slave, &op); } -+#if IS_ENABLED(CONFIG_MTD_SPI_NAND_W25N01KV) +static int w25n01kv_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ @@ -1242,7 +1435,6 @@ Signed-off-by: Weijie Gao + + return -EINVAL; +} -+#endif + +static int w25n02kv_n04kv_ecc_get_status(struct spinand_device *spinand, + u8 status) @@ -1280,28 +1472,26 @@ Signed-off-by: Weijie Gao NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2), NAND_ECCREQ(1, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -88,7 +191,19 @@ static const struct spinand_info winbond +@@ -88,7 +187,17 @@ static const struct spinand_info winbond 0, SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL), SPINAND_SELECT_TARGET(w25m02gv_select_target)), - SPINAND_INFO("W25N01GV", 0xAA, -+#if IS_ENABLED(CONFIG_MTD_SPI_NAND_W25N01KV) + SPINAND_INFO("W25N01KV", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21), -+ NAND_MEMORG(1, 2048, 96, 64, 1024, 1, 1, 1), ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, w25n01kv_ecc_get_status)), -+#else + SPINAND_INFO("W25N01GV", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21), NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), NAND_ECCREQ(1, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -@@ -96,32 +211,31 @@ static const struct spinand_info winbond +@@ -96,32 +205,30 @@ static const struct spinand_info winbond &update_cache_variants), 0, SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), @@ -1320,7 +1510,6 @@ Signed-off-by: Weijie Gao - /* - * Winbond SPI NAND read ID need a dummy byte, - * so the first byte in raw_id is dummy. -+#endif + SPINAND_INFO("W25N02KV", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22), + NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), @@ -1358,7 +1547,7 @@ Signed-off-by: Weijie Gao static int winbond_spinand_init(struct spinand_device *spinand) { -@@ -142,12 +256,13 @@ static int winbond_spinand_init(struct s +@@ -142,12 +249,13 @@ static int winbond_spinand_init(struct s } static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = { @@ -1495,7 +1684,7 @@ Signed-off-by: Weijie Gao int (*init)(struct spinand_device *spinand); void (*cleanup)(struct spinand_device *spinand); }; -@@ -192,11 +219,16 @@ struct spinand_manufacturer_ops { +@@ -192,15 +219,21 @@ struct spinand_manufacturer_ops { * struct spinand_manufacturer - SPI NAND manufacturer instance * @id: manufacturer ID * @name: manufacturer name @@ -1512,7 +1701,12 @@ Signed-off-by: Weijie Gao const struct spinand_manufacturer_ops *ops; }; -@@ -268,7 +300,7 @@ struct spinand_ecc_info { + /* SPI NAND manufacturers */ ++extern const struct spinand_manufacturer etron_spinand_manufacturer; + extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; + extern const struct spinand_manufacturer macronix_spinand_manufacturer; + extern const struct spinand_manufacturer micron_spinand_manufacturer; +@@ -268,7 +301,7 @@ struct spinand_ecc_info { */ struct spinand_info { const char *model; @@ -1521,7 +1715,7 @@ Signed-off-by: Weijie Gao u32 flags; struct nand_memory_organization memorg; struct nand_ecc_req eccreq; -@@ -282,6 +314,13 @@ struct spinand_info { +@@ -282,6 +315,13 @@ struct spinand_info { unsigned int target); }; @@ -1535,7 +1729,7 @@ Signed-off-by: Weijie Gao #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \ { \ .read_cache = __read, \ -@@ -440,9 +479,10 @@ static inline void spinand_set_ofnode(st +@@ -440,9 +480,10 @@ static inline void spinand_set_ofnode(st } #endif /* __UBOOT__ */ From 1db949a632607aa1df2987b7701da0be3e473260 Mon Sep 17 00:00:00 2001 From: Jianhui Zhao Date: Sun, 24 Sep 2023 22:15:00 +0800 Subject: [PATCH 28/30] generic: net: phy: realtek: add interrupt support for RTL8221B This commit introduces interrupt support for RTL8221B. Signed-off-by: Jianhui Zhao --- ...ealtek-support-interrupt-of-RTL8221B.patch | 63 +++++++++++++++++++ ...ealtek-support-interrupt-of-RTL8221B.patch | 63 +++++++++++++++++++ 2 files changed, 126 insertions(+) create mode 100644 target/linux/generic/pending-5.15/731-net-phy-realtek-support-interrupt-of-RTL8221B.patch create mode 100644 target/linux/generic/pending-6.1/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch diff --git a/target/linux/generic/pending-5.15/731-net-phy-realtek-support-interrupt-of-RTL8221B.patch b/target/linux/generic/pending-5.15/731-net-phy-realtek-support-interrupt-of-RTL8221B.patch new file mode 100644 index 00000000000..b2b41d9c61f --- /dev/null +++ b/target/linux/generic/pending-5.15/731-net-phy-realtek-support-interrupt-of-RTL8221B.patch @@ -0,0 +1,63 @@ +--- a/drivers/net/phy/realtek.c ++++ b/drivers/net/phy/realtek.c +@@ -971,6 +971,51 @@ static int rtl8221b_config_init(struct p + return 0; + } + ++static int rtl8221b_ack_interrupt(struct phy_device *phydev) ++{ ++ int err; ++ ++ err = phy_read_mmd(phydev, RTL8221B_MMD_PHY_CTRL, 0xa4d4); ++ ++ return (err < 0) ? err : 0; ++} ++ ++static int rtl8221b_config_intr(struct phy_device *phydev) ++{ ++ int err; ++ ++ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { ++ err = rtl8221b_ack_interrupt(phydev); ++ if (err) ++ return err; ++ ++ err = phy_write_mmd(phydev, RTL8221B_MMD_PHY_CTRL, 0xa4d2, 0x7ff); ++ } else { ++ err = phy_write_mmd(phydev, RTL8221B_MMD_PHY_CTRL, 0xa4d2, 0x0); ++ if (err) ++ return err; ++ ++ err = rtl8221b_ack_interrupt(phydev); ++ } ++ ++ return err; ++} ++ ++static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev) ++{ ++ int err; ++ ++ err = rtl8221b_ack_interrupt(phydev); ++ if (err) { ++ phy_error(phydev); ++ return IRQ_NONE; ++ } ++ ++ phy_trigger_machine(phydev); ++ ++ return IRQ_HANDLED; ++} ++ + static struct phy_driver realtek_drvs[] = { + { + PHY_ID_MATCH_EXACT(0x00008201), +@@ -1119,6 +1164,8 @@ static struct phy_driver realtek_drvs[] + .get_features = rtl822x_get_features, + .config_init = rtl8221b_config_init, + .config_aneg = rtl822x_config_aneg, ++ .config_intr = rtl8221b_config_intr, ++ .handle_interrupt = rtl8221b_handle_interrupt, + .probe = rtl822x_probe, + .read_status = rtl822x_read_status, + .suspend = genphy_suspend, diff --git a/target/linux/generic/pending-6.1/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch b/target/linux/generic/pending-6.1/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch new file mode 100644 index 00000000000..55a9e3529d0 --- /dev/null +++ b/target/linux/generic/pending-6.1/741-net-phy-realtek-support-interrupt-of-RTL8221B.patch @@ -0,0 +1,63 @@ +--- a/drivers/net/phy/realtek.c ++++ b/drivers/net/phy/realtek.c +@@ -979,6 +979,51 @@ static int rtl8221b_config_init(struct p + return 0; + } + ++static int rtl8221b_ack_interrupt(struct phy_device *phydev) ++{ ++ int err; ++ ++ err = phy_read_mmd(phydev, RTL8221B_MMD_PHY_CTRL, 0xa4d4); ++ ++ return (err < 0) ? err : 0; ++} ++ ++static int rtl8221b_config_intr(struct phy_device *phydev) ++{ ++ int err; ++ ++ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { ++ err = rtl8221b_ack_interrupt(phydev); ++ if (err) ++ return err; ++ ++ err = phy_write_mmd(phydev, RTL8221B_MMD_PHY_CTRL, 0xa4d2, 0x7ff); ++ } else { ++ err = phy_write_mmd(phydev, RTL8221B_MMD_PHY_CTRL, 0xa4d2, 0x0); ++ if (err) ++ return err; ++ ++ err = rtl8221b_ack_interrupt(phydev); ++ } ++ ++ return err; ++} ++ ++static irqreturn_t rtl8221b_handle_interrupt(struct phy_device *phydev) ++{ ++ int err; ++ ++ err = rtl8221b_ack_interrupt(phydev); ++ if (err) { ++ phy_error(phydev); ++ return IRQ_NONE; ++ } ++ ++ phy_trigger_machine(phydev); ++ ++ return IRQ_HANDLED; ++} ++ + static struct phy_driver realtek_drvs[] = { + { + PHY_ID_MATCH_EXACT(0x00008201), +@@ -1139,6 +1184,8 @@ static struct phy_driver realtek_drvs[] + .get_features = rtl822x_get_features, + .config_init = rtl8221b_config_init, + .config_aneg = rtl822x_config_aneg, ++ .config_intr = rtl8221b_config_intr, ++ .handle_interrupt = rtl8221b_handle_interrupt, + .probe = rtl822x_probe, + .read_status = rtl822x_read_status, + .suspend = genphy_suspend, From e3aa645b267ca4f08773b5366583e9b0020fc3e9 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Thu, 4 May 2023 23:10:03 +0800 Subject: [PATCH 29/30] mt76: drop default eeprom file for mt7986-firmware The mt76 driver usually reads the eeprom on the mtd partition at dts. For emmc device we need to use caldata_extract script to read the eeprom. However, the default eeprom file breaks the caldata script execution, so remove it. Signed-off-by: Chukun Pan --- package/kernel/mt76/Makefile | 2 -- 1 file changed, 2 deletions(-) diff --git a/package/kernel/mt76/Makefile b/package/kernel/mt76/Makefile index 9a3597f770c..cc8221d7ce1 100644 --- a/package/kernel/mt76/Makefile +++ b/package/kernel/mt76/Makefile @@ -586,8 +586,6 @@ define KernelPackage/mt7986-firmware/install $(PKG_BUILD_DIR)/firmware/mt7986_wm.bin \ $(PKG_BUILD_DIR)/firmware/mt7986_rom_patch_mt7975.bin \ $(PKG_BUILD_DIR)/firmware/mt7986_rom_patch.bin \ - $(PKG_BUILD_DIR)/firmware/mt7986_eeprom_mt7975_dual.bin \ - $(PKG_BUILD_DIR)/firmware/mt7986_eeprom_mt7976_dual.bin \ $(1)/lib/firmware/mediatek endef From fe10f9743935d6986e80e7cb082469e6bc5a03f0 Mon Sep 17 00:00:00 2001 From: Jianhui Zhao Date: Sun, 24 Sep 2023 22:34:12 +0800 Subject: [PATCH 30/30] filogic: add support for GL.iNet GL-MT6000 Hardware specification: * SoC: MediaTek MT7986A 4x A53 * Flash: 8GB EMMC * RAM: 1GB DDR4 * Ethernet: * 2x2.5G RJ45 port (RTL8221B) * 4x1G RJ45 ports (MT7531AE) * WLAN: * 2.4GHz: MT7976GN 4T4R * 5GHz: MT7976AN 4T4R * Button: Reset * LED: 1 x dual color LED * USB: 1 x USB 3.0 * Power: DC 12V 4A * UART: 3V3 115200 8N1 (Pinout: GND TX RX VCC) * JTAG: 9 PIN If you want to use u-boot from OpenWrt, you can upgrade it safely. * bl2: openwrt-mediatek-filogic-glinet_gl-mt6000-preloader.bin * fip: openwrt-mediatek-filogic-glinet_gl-mt6000-bl31-uboot.fip `openwrt-mediatek-filogic-glinet_gl-mt6000-squashfs-factory.bin` is used in OpenWrt's u-boot. Signed-off-by: Jianhui Zhao --- .../uboot-envtools/files/mediatek_filogic | 4 + package/boot/uboot-mediatek/Makefile | 13 + .../patches/436-add-glinet-mt6000.patch | 274 ++++++++++++++++ .../mediatek/dts/mt7986a-glinet-gl-mt6000.dts | 306 ++++++++++++++++++ .../filogic/base-files/etc/board.d/02_network | 6 + .../etc/hotplug.d/firmware/11-mt76-caldata | 7 + .../etc/hotplug.d/ieee80211/11_fix_wifi_mac | 5 + .../base-files/lib/upgrade/platform.sh | 6 + target/linux/mediatek/image/filogic.mk | 15 + 9 files changed, 636 insertions(+) create mode 100644 package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch create mode 100644 target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts diff --git a/package/boot/uboot-envtools/files/mediatek_filogic b/package/boot/uboot-envtools/files/mediatek_filogic index 803800ce1c7..4b8fe6b8012 100644 --- a/package/boot/uboot-envtools/files/mediatek_filogic +++ b/package/boot/uboot-envtools/files/mediatek_filogic @@ -40,6 +40,10 @@ bananapi,bpi-r3) glinet,gl-mt3000) ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x20000" ;; +glinet,gl-mt6000) + local envdev=$(find_mmc_part "u-boot-env") + ubootenv_add_uci_config "$envdev" "0x0" "0x80000" + ;; mercusys,mr90x-v1) local envdev=/dev/mtd$(find_mtd_index "u-boot-env") ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x20000" "1" diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index 62199871e6b..1a97570031c 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -357,6 +357,18 @@ define U-Boot/mt7986_bananapi_bpi-r3-nor FIP_COMPRESS:=1 endef +define U-Boot/mt7986_glinet_gl-mt6000 + NAME:=GL.iNet GL-MT6000 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=glinet_gl-mt6000 + UBOOT_CONFIG:=mt7986a_glinet_gl-mt6000 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-emmc-ddr4 +endef + define U-Boot/mt7986_tplink_tl-xdr4288 NAME:=TP-LINK TL-XDR4288 BUILD_SUBTARGET:=filogic @@ -496,6 +508,7 @@ UBOOT_TARGETS := \ mt7986_bananapi_bpi-r3-sdmmc \ mt7986_bananapi_bpi-r3-snand \ mt7986_bananapi_bpi-r3-nor \ + mt7986_glinet_gl-mt6000 \ mt7986_tplink_tl-xdr4288 \ mt7986_tplink_tl-xdr6086 \ mt7986_tplink_tl-xdr6088 \ diff --git a/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch b/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch new file mode 100644 index 00000000000..ad138acfd92 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch @@ -0,0 +1,274 @@ +--- /dev/null ++++ b/arch/arm/dts/mt7986a-glinet-gl-mt6000.dts +@@ -0,0 +1,135 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++/dts-v1/; ++#include ++#include ++ ++#include "mt7986.dtsi" ++ ++/ { ++ model = "GL.iNet GL-MT6000"; ++ compatible = "glinet,gl-mt6000", "mediatek,mt7986-emmc-rfb", "mediatek,mt7986"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x40000000>; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ wps { ++ label = "reset"; ++ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_status_blue: green { ++ label = "blue:status"; ++ gpios = <&gpio 28 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led_status_white: blue { ++ label = "white:status"; ++ gpios = <&gpio 27 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ mmc0_pins_default: mmc0default { ++ mux { ++ function = "flash"; ++ groups = "emmc_51"; ++ }; ++ ++ conf-cmd-dat { ++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", ++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", ++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; ++ input-enable; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ conf-clk { ++ pins = "EMMC_CK"; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ ++ conf-dsl { ++ pins = "EMMC_DSL"; ++ bias-pull-down = ; ++ }; ++ ++ conf-rst { ++ pins = "EMMC_RSTB"; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ cap-mmc-highspeed; ++ cap-mmc-hw-reset; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_1p8v>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&wmcpu_emi { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/configs/mt7986a_glinet_gl-mt6000_defconfig +@@ -0,0 +1,105 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x80000 ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-glinet-gl-mt6000" ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7986=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_DEBUG_UART=y ++CONFIG_AHCI=y ++CONFIG_FIT=y ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-glinet-gl-mt6000.dtb" ++CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="glinet_gl-mt6000_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_HEXDUMP=y ++CONFIG_LMB_MAX_REGIONS=64 +--- /dev/null ++++ b/glinet_gl-mt6000_env +@@ -0,0 +1,25 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++bootdelay=3 ++bootfile_bl2=openwrt-mediatek-filogic-glinet_gl-mt6000-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-glinet_gl-mt6000-bl31-uboot.fip ++bootfile_firmware=openwrt-mediatek-filogic-glinet_gl-mt6000-squashfs-factory.bin ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_title= *** U-Boot Boot Menu for GL-iNet GL-MT6000 *** ++bootmenu_0=Startup system (Default).=run boot_system ++bootmenu_1=Load Firmware via TFTP then write to eMMC.=run boot_tftp_firmware ; run bootmenu_confirm_return ++bootmenu_2=Load BL31+U-Boot FIP via TFTP then write to eMMC.=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_3=mLoad BL2 preloader via TFTP then write to eMMC.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_4=Reboot.=reset ++bootmenu_5=Reset all settings to factory defaults.=run reset_factory ; reset ++filesize_to_blk=setexpr cnt $filesize + 0x1ff && setexpr cnt $cnt / 0x200 ++mmc_read_kernel=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr $part_addr $image_size ++boot_system=part start mmc 0 kernel part_addr && part size mmc 0 kernel part_size && run mmc_read_kernel && bootm ++boot_tftp_firmware=tftpboot $loadaddr $bootfile_firmware && run emmc_write_firmware ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2 ++emmc_write_firmware=part start mmc 0 kernel part_addr && run filesize_to_blk && mmc write $loadaddr $part_addr $cnt ++emmc_write_bl2=run filesize_to_blk && test 0x$cnt -le 0x800 && mmc partconf 0 1 1 1 && && mmc write $loadaddr 0x0 0x800 ; mmc partconf 0 1 1 0 ++emmc_write_fip=part start mmc 0 fip part_addr && part size mmc 0 fip part_size && run filesize_to_blk && test 0x$cnt -le 0x$part_size && mmc write $loadaddr $part_addr $cnt ++reset_factory=eraseenv && reset diff --git a/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts b/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts new file mode 100644 index 00000000000..2be1907f632 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + model = "GL.iNet GL-MT6000"; + compatible = "glinet,gl-mt6000", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-append = " root=PARTLABEL=rootfs rootwait"; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1.8vd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_run: led@0 { + label = "blue:run"; + gpios = <&pio 38 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led@1 { + label = "white:system"; + gpios = <&pio 37 GPIO_ACTIVE_LOW>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpios = <&pio 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + phy-handle = <&phy1>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <1>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + reset-gpios = <&pio 10 GPIO_ACTIVE_LOW>; + interrupt-parent = <&pio>; + interrupts = <46 IRQ_TYPE_LEVEL_LOW>; + realtek,aldps-enable; + }; + + phy7: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + reset-gpios = <&pio 19 GPIO_ACTIVE_LOW>; + interrupt-parent = <&pio>; + interrupts = <47 IRQ_TYPE_LEVEL_LOW>; + realtek,aldps-enable; + }; + + switch: switch@31 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 18 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan2"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan4"; + }; + + port@3 { + reg = <3>; + label = "lan5"; + }; + + port@5 { + reg = <5>; + label = "lan1"; + phy-handle = <&phy7>; + phy-mode = "2500base-x"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&pio { + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; +}; + +&crypto { + status = "okay"; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + pinctrl-names = "default"; + pinctrl-0 = <&wf_2g_5g_pins>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 42490cf8b3a..590c1fb2a66 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -48,6 +48,7 @@ mediatek_setup_interfaces() qihoo,360t7) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" wan ;; + glinet,gl-mt6000|\ tplink,tl-xdr4288|\ tplink,tl-xdr6088) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" eth1 @@ -90,6 +91,11 @@ mediatek_setup_macs() wan_mac=$(macaddr_add "$lan_mac" 3) label_mac=$lan_mac ;; + glinet,gl-mt6000) + label_mac=$(mmc_get_mac_binary factory 0x0a) + wan_mac=$label_mac + lan_mac=$(macaddr_add "$label_mac" 2) + ;; h3c,magic-nx30-pro) wan_mac=$(mtd_get_mac_ascii pdt_data_1 ethaddr) lan_mac=$(macaddr_add "$wan_mac" 1) diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata index f6f18272cc3..e4d33879c6d 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata @@ -36,6 +36,13 @@ case "$FIRMWARE" in ;; esac ;; +"mediatek/mt7986_eeprom_mt7976_dual.bin") + case "$board" in + glinet,gl-mt6000) + caldata_extract_mmc "factory" 0x0 0x1000 + ;; + esac + ;; *) exit 1 ;; diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index 0fc90bd41b1..115ff2201ec 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -43,6 +43,11 @@ case "$board" in [ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress ;; + glinet,gl-mt6000) + addr=$(mmc_get_mac_binary factory 0x04) + [ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress + ;; h3c,magic-nx30-pro) addr=$(mtd_get_mac_ascii pdt_data_1 ethaddr) [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index 6155ddab726..42156aefb4d 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -84,6 +84,11 @@ platform_do_upgrade() { cudy,wr3000-v1) default_do_upgrade "$1" ;; + glinet,gl-mt6000) + CI_KERNPART="kernel" + CI_ROOTPART="rootfs" + emmc_do_upgrade "$1" + ;; mercusys,mr90x-v1) CI_UBIPART="ubi0" nand_do_upgrade "$1" @@ -150,6 +155,7 @@ platform_copy_config() { ;; esac ;; + glinet,gl-mt6000|\ ubnt,unifi-6-plus) emmc_copy_config ;; diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index c9cf30b1cea..6082cf5f47e 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -239,6 +239,21 @@ define Device/glinet_gl-mt3000 endef TARGET_DEVICES += glinet_gl-mt3000 +define Device/glinet_gl-mt6000 + DEVICE_VENDOR := GL.iNet + DEVICE_MODEL := GL-MT6000 + DEVICE_DTS := mt7986a-glinet-gl-mt6000 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-usb2 kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware e2fsprogs f2fsck mkf2fs + IMAGES += factory.bin + IMAGE/factory.bin := append-kernel | pad-to 32M | append-rootfs + IMAGE/sysupgrade.bin := sysupgrade-tar | append-gl-metadata + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := mt7986-bl2 emmc-ddr4 + ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot glinet_gl-mt6000 +endef +TARGET_DEVICES += glinet_gl-mt6000 + define Device/h3c_magic-nx30-pro DEVICE_VENDOR := H3C DEVICE_MODEL := Magic NX30 Pro