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qualcommbe: v6.12: add NSSCC clock and reset fixes

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Port reset and clock fixes from target/linux/qualcommbe/patches-6.6.
Modifications of v6.6 patches are noted in each commit body.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18796
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Alexandru Gagniuc 2025-05-13 22:13:55 -05:00 committed by Robert Marko
parent 26ea222e21
commit 627daef0cf
3 changed files with 161 additions and 0 deletions
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73
target/linux/qualcommbe/patches-6.12/0358-clk-qcom-nsscc-Attach-required-NSSNOC-clock-to-PM-do.patch Normal file
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@ -0,0 +1,73 @@
From 6417cb20e854194a845d4ab092b92fd753c0e405 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 30 Jan 2025 16:11:14 +0100
Subject: [PATCH] clk: qcom: nsscc: Attach required NSSNOC clock to PM domain
There is currently a problem with ICC clock disabling the NSSNOC clock
as there isn't any user for them on calling sync_state.
This cause the kernel to stall if NSS is enabled and reboot with the watchdog.
This is caused by the fact that the NSSNOC clock nsscc, snoc and snoc_1
are actually required to make the NSS work and make the system continue
booting.
To attach these clock, setup pm-clk in nsscc and setup the correct
resume/suspend OPs.
With this change, the clock gets correctly attached and are not disabled
when ICC call the sync_state.
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Alex G: Retrieve clocks by name rather than index.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
drivers/clk/qcom/nsscc-ipq9574.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
--- a/drivers/clk/qcom/nsscc-ipq9574.c
+++ b/drivers/clk/qcom/nsscc-ipq9574.c
@@ -3060,6 +3060,7 @@ MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_m
static int nss_cc_ipq9574_probe(struct platform_device *pdev)
{
+ struct device *dev = &pdev->dev;
struct regmap *regmap;
int ret;
@@ -3075,6 +3076,18 @@ static int nss_cc_ipq9574_probe(struct p
if (ret)
return dev_err_probe(&pdev->dev, ret, "Fail to add bus clock\n");
+ ret = pm_clk_add(&pdev->dev, "nssnoc");
+ if (ret)
+ return dev_err_probe(dev, ret,"failed to acquire nssnoc clock\n");
+
+ ret = pm_clk_add(&pdev->dev, "snoc");
+ if (ret)
+ return dev_err_probe(dev, ret,"failed to acquire snoc clock\n");
+
+ ret = pm_clk_add(&pdev->dev, "snoc_1");
+ if (ret)
+ return dev_err_probe(dev, ret,"failed to acquire snoc_1 clock\n");
+
ret = pm_runtime_resume_and_get(&pdev->dev);
if (ret)
return dev_err_probe(&pdev->dev, ret, "Fail to resume\n");
@@ -3089,8 +3102,16 @@ static int nss_cc_ipq9574_probe(struct p
clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
ret = qcom_cc_really_probe(&pdev->dev, &nss_cc_ipq9574_desc, regmap);
+ if (ret)
+ goto err_put_pm;
+
pm_runtime_put(&pdev->dev);
+ return 0;
+
+err_put_pm:
+ pm_runtime_put_sync(dev);
+
return ret;
}

42
target/linux/qualcommbe/patches-6.12/0359-arm64-dts-qcom-ipq9574-add-NSSNOC-clock-to-nss-node.patch Normal file
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@ -0,0 +1,42 @@
From 372bbae100ffe14908bfd8448143c6cdbea17e8d Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 30 Jan 2025 16:23:03 +0100
Subject: [PATCH] arm64: dts: qcom: ipq9574: add NSSNOC clock to nss node
Add NSSNOC clock to nss node to attach the clock with PM clock and fix
the boot stall after ICC sync_state.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Alex G: Do not remove GCC_NSSCC_CLK ("bus") clock
Add clock-names for the new clocks
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -1253,7 +1253,10 @@
<&pcs_uniphy1 1>,
<&pcs_uniphy2 0>,
<&pcs_uniphy2 1>,
- <&gcc GCC_NSSCC_CLK>;
+ <&gcc GCC_NSSCC_CLK>,
+ <&gcc GCC_NSSNOC_NSSCC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_1_CLK>;
clock-names = "xo",
"nss_1200",
"ppe_353",
@@ -1264,7 +1267,10 @@
"uniphy1_tx",
"uniphy2_rx",
"uniphy2_tx",
- "bus";
+ "bus",
+ "nssnoc",
+ "snoc",
+ "snoc_1";
#clock-cells = <1>;
#reset-cells = <1>;
#interconnect-cells = <1>;

46
target/linux/qualcommbe/patches-6.12/0360-clk-qcom-nsscc-ipq9574-fix-port5-clock-config.patch Normal file
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@ -0,0 +1,46 @@
From fa691ff57c72a8f0bfeff1a9e86ae2d78765b0da Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Mon, 31 Mar 2025 15:39:59 +0300
Subject: [PATCH] clk: qcom: nsscc-ipq9574: fix port5 clock config
Currently there is no configuration to derive 25/125MHz port5 clock
from uniphy1 running at 125MHz. This is needed for SGMII mode when
port5 is using uniphy1.
Fix this by adding option such clock config option.
Signed-off-by: Mantas Pucka <mantas@8devices.com>
---
drivers/clk/qcom/nsscc-ipq9574.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/drivers/clk/qcom/nsscc-ipq9574.c
+++ b/drivers/clk/qcom/nsscc-ipq9574.c
@@ -383,11 +383,13 @@ static const struct freq_multi_tbl ftbl_
static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_25[] = {
C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY1_NSS_RX_CLK, 5, 0, 0),
C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
};
static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_125[] = {
C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
};
@@ -408,11 +410,13 @@ static const struct freq_multi_tbl ftbl_
static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_25[] = {
C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0),
+ C(P_UNIPHY1_NSS_TX_CLK, 5, 0, 0),
C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
};
static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_125[] = {
C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0),
+ C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
};