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qualcommbe: v6.12: enable ethernet for RDP433

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Now that ethernet is supported on IPQ9574, add the port nodes and
other requirements to enable ethernet on RDP433.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18796
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Alexandru Gagniuc 2025-05-13 22:08:55 -05:00 committed by Robert Marko
parent f3fc278fcb
commit 26ea222e21
3 changed files with 292 additions and 0 deletions
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197
target/linux/qualcommbe/patches-6.12/0355-arm64-dts-qcom-Add-IPQ9574-RDP433-port-node.patch Normal file
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@ -0,0 +1,197 @@
From 001b663ecc5f838dac143623badae0e472749d8a Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Tue, 14 May 2024 10:53:27 +0800
Subject: [PATCH] arm64: dts: qcom: Add IPQ9574 RDP433 port node
There are 6 PPE MAC ports available on RDP433. The port1-port4 are
connected with QCA8075 QUAD PHYs through UNIPHY0 PCS channel0-channel3.
The port5 is connected with Aquantia PHY through UNIPHY1 PCS channel0
and the port6 is connected with Aquantia PHY through UNIPHY2 PCS
channel0.
Change-Id: Ic16efdef2fe2cff7b1e80245619c0f82afb24cb9
Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
---
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 167 ++++++++++++++++++++
1 file changed, 167 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
@@ -55,6 +55,46 @@
status = "okay";
};
+&mdio {
+ reset-gpios = <&tlmm 60 GPIO_ACTIVE_LOW>;
+ clock-frequency = <6250000>;
+ status = "okay";
+
+ ethernet-phy-package@0 {
+ compatible = "qcom,qca8075-package";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10>;
+ qcom,package-mode = "qsgmii";
+
+ phy0: ethernet-phy@10 {
+ reg = <0x10>;
+ };
+
+ phy1: ethernet-phy@11 {
+ reg = <0x11>;
+ };
+
+ phy2: ethernet-phy@12 {
+ reg = <0x12>;
+ };
+
+ phy3: ethernet-phy@13 {
+ reg = <0x13>;
+ };
+ };
+
+ phy4: ethernet-phy@8 {
+ compatible ="ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ };
+
+ phy5: ethernet-phy@0 {
+ compatible ="ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ };
+};
+
&tlmm {
pcie1_default: pcie1-default-state {
@@ -161,3 +201,130 @@
};
};
};
+
+&qcom_ppe {
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ phy-handle = <&phy0>;
+ pcs-handle = <&pcsuniphy0_ch0>;
+ clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>,
+ <&nsscc NSS_CC_PORT1_RX_CLK>,
+ <&nsscc NSS_CC_PORT1_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ resets = <&nsscc PORT1_MAC_ARES>,
+ <&nsscc PORT1_RX_ARES>,
+ <&nsscc PORT1_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ };
+
+ port@2 {
+ reg = <2>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ phy-handle = <&phy1>;
+ pcs-handle = <&pcsuniphy0_ch1>;
+ clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>,
+ <&nsscc NSS_CC_PORT2_RX_CLK>,
+ <&nsscc NSS_CC_PORT2_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ resets = <&nsscc PORT2_MAC_ARES>,
+ <&nsscc PORT2_RX_ARES>,
+ <&nsscc PORT2_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ };
+
+ port@3 {
+ reg = <3>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ phy-handle = <&phy2>;
+ pcs-handle = <&pcsuniphy0_ch2>;
+ clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>,
+ <&nsscc NSS_CC_PORT3_RX_CLK>,
+ <&nsscc NSS_CC_PORT3_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ resets = <&nsscc PORT3_MAC_ARES>,
+ <&nsscc PORT3_RX_ARES>,
+ <&nsscc PORT3_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ };
+
+ port@4 {
+ reg = <4>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ phy-handle = <&phy3>;
+ pcs-handle = <&pcsuniphy0_ch3>;
+ clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>,
+ <&nsscc NSS_CC_PORT4_RX_CLK>,
+ <&nsscc NSS_CC_PORT4_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ resets = <&nsscc PORT4_MAC_ARES>,
+ <&nsscc PORT4_RX_ARES>,
+ <&nsscc PORT4_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ };
+
+ port@5 {
+ reg = <5>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ phy-handle = <&phy4>;
+ pcs-handle = <&pcsuniphy1_ch0>;
+ clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>,
+ <&nsscc NSS_CC_PORT5_RX_CLK>,
+ <&nsscc NSS_CC_PORT5_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ resets = <&nsscc PORT5_MAC_ARES>,
+ <&nsscc PORT5_RX_ARES>,
+ <&nsscc PORT5_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ };
+
+ port@6 {
+ reg = <6>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ phy-handle = <&phy5>;
+ pcs-handle = <&pcsuniphy2_ch0>;
+ clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>,
+ <&nsscc NSS_CC_PORT6_RX_CLK>,
+ <&nsscc NSS_CC_PORT6_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ resets = <&nsscc PORT6_MAC_ARES>,
+ <&nsscc PORT6_RX_ARES>,
+ <&nsscc PORT6_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ };
+ };
+};

33
target/linux/qualcommbe/patches-6.12/0356-arm64-dts-qcom-add-AQR-NVMEM-node-for-IPQ9574-RDP433.patch Normal file
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@ -0,0 +1,33 @@
From 30b751f5984e295f0b5e7a2308b6103fae3322d2 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 9 Dec 2024 18:10:43 +0100
Subject: [PATCH] arm64: dts: qcom: add AQR NVMEM node for IPQ9574 RDP433 board
Add Aquantia NVMEM node for IPQ9574 RDP433 board to load the firmware
for the Aquantia PHY.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
@@ -87,11 +87,17 @@
phy4: ethernet-phy@8 {
compatible ="ethernet-phy-ieee802.3-c45";
reg = <8>;
+
+ nvmem-cells = <&aqr_fw>;
+ nvmem-cell-names = "firmware";
};
phy5: ethernet-phy@0 {
compatible ="ethernet-phy-ieee802.3-c45";
reg = <0>;
+
+ nvmem-cells = <&aqr_fw>;
+ nvmem-cell-names = "firmware";
};
};

62
target/linux/qualcommbe/patches-6.12/0357-arm64-dts-qcom-Add-label-to-EDMA-port-for-IPQ9574-RD.patch Normal file
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@ -0,0 +1,62 @@
From b297d12d434191845cf8ae359466dcd8312ed21d Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Wed, 4 Dec 2024 01:49:09 +0100
Subject: [PATCH] arm64: dts: qcom: Add label to EDMA port for IPQ9574 RDP433
Add label to EDMA port for IPQ9574 RDP433 board.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
@@ -217,6 +217,7 @@
reg = <1>;
phy-mode = "qsgmii";
managed = "in-band-status";
+ label = "lan1";
phy-handle = <&phy0>;
pcs-handle = <&pcsuniphy0_ch0>;
clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>,
@@ -237,6 +238,7 @@
reg = <2>;
phy-mode = "qsgmii";
managed = "in-band-status";
+ label = "lan2";
phy-handle = <&phy1>;
pcs-handle = <&pcsuniphy0_ch1>;
clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>,
@@ -257,6 +259,7 @@
reg = <3>;
phy-mode = "qsgmii";
managed = "in-band-status";
+ label = "lan3";
phy-handle = <&phy2>;
pcs-handle = <&pcsuniphy0_ch2>;
clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>,
@@ -277,6 +280,7 @@
reg = <4>;
phy-mode = "qsgmii";
managed = "in-band-status";
+ label = "lan4";
phy-handle = <&phy3>;
pcs-handle = <&pcsuniphy0_ch3>;
clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>,
@@ -297,6 +301,7 @@
reg = <5>;
phy-mode = "usxgmii";
managed = "in-band-status";
+ label = "lan5";
phy-handle = <&phy4>;
pcs-handle = <&pcsuniphy1_ch0>;
clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>,
@@ -317,6 +322,7 @@
reg = <6>;
phy-mode = "usxgmii";
managed = "in-band-status";
+ label = "wan";
phy-handle = <&phy5>;
pcs-handle = <&pcsuniphy2_ch0>;
clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>,