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u-boot/board/freescale/imx8ulp_evk
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Jacky Bai fd3cb1d977 imx8ulp_evk: Update the DDR timing 
Update the dram timing to support PLL bypass mode
for F1.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2023-03-29 20:15:42 +02:00
..
ddr_init.c arm: imx: add i.MX8ULP EVK support 2021-08-09 14:46:51 +02:00
imx8ulp_evk.c imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion 2023-03-29 20:15:42 +02:00
Kconfig nxp: Make board/freescale/common/Kconfig safe to include once in arch/Kconfig 2022-07-05 17:03:02 -04:00
lpddr4_timing.c imx8ulp_evk: Update the DDR timing 2023-03-29 20:15:42 +02:00
lpddr4_timing_266.c imx: imx8ulp: add ND/LD clock 2022-04-12 17:33:56 +02:00
MAINTAINERS arm: imx: add i.MX8ULP EVK support 2021-08-09 14:46:51 +02:00
Makefile imx: imx8ulp: add ND/LD clock 2022-04-12 17:33:56 +02:00
spl.c imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 only 2023-03-29 20:15:42 +02:00