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u-boot/arch/arm/cpu/armv7/omap5
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Lokesh Vutla ea8eff1fe0 arm: dra7xx: clock: Add the dplls data 
A new DPLL DDR is added in DRA7XX socs. Now clocks to
EMIF CD is from DPLL DDR. So DPLL DDR should be locked
before initializing RAM.
Also adding other dpll data which are different from OMAP5 ES2.0.
SYS_CLK running at 20MHz is introduced in DRA7xx socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
..
config.mk omap5: Add minimal support for omap5430. 2011-11-15 22:25:50 +01:00
emif.c omap5: emif: Add emif/ddr configurations required for omap5 evm 2011-11-15 22:25:50 +01:00
hw_data.c arm: dra7xx: clock: Add the dplls data 2013-03-11 11:06:11 -04:00
hwinit.c arm: dra7xx: clock: Add the prcm changes 2013-03-11 11:06:11 -04:00
Makefile ARM: OMAP4+: Clean up the pmic code 2013-03-11 11:06:10 -04:00
prcm-regs.c arm: dra7xx: clock: Add the prcm changes 2013-03-11 11:06:11 -04:00
sdram.c ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs 2013-03-11 11:06:10 -04:00