cf04d0326b
Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
79 lines
2 KiB
C
79 lines
2 KiB
C
/*
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* hardware_am43xx.h
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*
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* AM43xx hardware specific header
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __AM43XX_HARDWARE_AM43XX_H
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#define __AM43XX_HARDWARE_AM43XX_H
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/* Module base addresses */
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/* UART Base Address */
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#define UART0_BASE 0x44E09000
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/* GPIO Base address */
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#define GPIO2_BASE 0x481AC000
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/* Watchdog Timer */
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#define WDT_BASE 0x44E35000
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/* Control Module Base Address */
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#define CTRL_BASE 0x44E10000
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#define CTRL_DEVICE_BASE 0x44E10600
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/* PRCM Base Address */
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#define PRCM_BASE 0x44DF0000
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#define CM_WKUP 0x44DF2800
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#define CM_PER 0x44DF8800
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#define CM_DPLL 0x44DF4200
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#define CM_RTC 0x44DF8500
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#define PRM_RSTCTRL (PRCM_BASE + 0x4000)
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#define PRM_RSTST (PRM_RSTCTRL + 4)
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/* VTP Base address */
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#define VTP0_CTRL_ADDR 0x44E10E0C
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#define VTP1_CTRL_ADDR 0x48140E10
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/* DDR Base address */
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#define DDR_PHY_CMD_ADDR 0x44E12000
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#define DDR_PHY_DATA_ADDR 0x44E120C8
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#define DDR_PHY_CMD_ADDR2 0x47C0C800
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#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
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#define DDR_DATA_REGS_NR 2
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/* CPSW Config space */
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#define CPSW_MDIO_BASE 0x4A101000
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/* RTC base address */
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#define RTC_BASE 0x44E3E000
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/* USB Clock Control */
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#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
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#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
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#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1)
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#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
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#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
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#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
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#define USBPHYOCPSCP_MODULE_EN (1 << 1)
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/* Control status register */
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#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
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#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31
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#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29)
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#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29
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#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22)
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#define CTRL_SYSBOOT_15_14_SHIFT 22
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#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0
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#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1
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#define NUM_CRYSTAL_FREQ 0x4
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#endif /* __AM43XX_HARDWARE_AM43XX_H */
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