This change allows to keep board description clean and minimalistic. This is especially helpful if one board may house different CPUs with different features. It is applicable to both FPGA-based boards or those that have CPUs mounted on interchnagable daughter-boards. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
5 lines
No EOL
119 B
Text
5 lines
No EOL
119 B
Text
CONFIG_ARC=y
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CONFIG_TARGET_AXS101=y
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CONFIG_SYS_CLK_FREQ=750000000
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CONFIG_ARC_CACHE_LINE_SHIFT=5
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CONFIG_SYS_DCACHE_OFF=y |