ba6a169811
Currently the non-secure switch is only done for the boot processor. To enable full SMP support, we have to switch all secondary cores into non-secure state also. So we add an entry point for secondary CPUs coming out of low-power state and make sure we put them into WFI again after having switched to non-secure state. For this we acknowledge and EOI the wake-up IPI, then go into WFI. Once being kicked out of it later, we sanity check that the start address has actually been changed (since another attempt to switch to non-secure would block the core) and jump to the new address. The actual CPU kick is done by sending an inter-processor interrupt via the GIC to all CPU interfaces except the requesting processor. The secondary cores will then setup their respective GIC CPU interface. While this approach is pretty universal across several ARMv7 boards, we make this function weak in case someone needs to tweak this for a specific board. The way of setting the secondary's start address is board specific, but mostly different only in the actual SMP pen address, so we also provide a weak default implementation and just depend on the proper address to be set in the config file. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
175 lines
5.2 KiB
ArmAsm
175 lines
5.2 KiB
ArmAsm
/*
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* code for switching cores into non-secure state
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*
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* Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/gic.h>
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#include <asm/armv7.h>
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.arch_extension sec
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/* the vector table for secure state */
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_monitor_vectors:
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.word 0 /* reset */
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.word 0 /* undef */
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adr pc, _secure_monitor
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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/*
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* secure monitor handler
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* U-boot calls this "software interrupt" in start.S
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* This is executed on a "smc" instruction, we use a "smc #0" to switch
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* to non-secure state.
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* We use only r0 and r1 here, due to constraints in the caller.
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*/
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.align 5
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_secure_monitor:
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mrc p15, 0, r1, c1, c1, 0 @ read SCR
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bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits
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orr r1, r1, #0x31 @ enable NS, AW, FW bits
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mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
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movs pc, lr @ return to non-secure SVC
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/*
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* Secondary CPUs start here and call the code for the core specific parts
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* of the non-secure and HYP mode transition. The GIC distributor specific
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* code has already been executed by a C function before.
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* Then they go back to wfi and wait to be woken up by the kernel again.
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*/
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ENTRY(_smp_pen)
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mrs r0, cpsr
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orr r0, r0, #0xc0
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msr cpsr, r0 @ disable interrupts
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ldr r1, =_start
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mcr p15, 0, r1, c12, c0, 0 @ set VBAR
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bl _nonsec_init
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ldr r1, [r0, #GICC_IAR] @ acknowledge IPI
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str r1, [r0, #GICC_EOIR] @ signal end of interrupt
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adr r0, _smp_pen @ do not use this address again
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b smp_waitloop @ wait for IPIs, board specific
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ENDPROC(_smp_pen)
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/*
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* Switch a core to non-secure state.
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*
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* 1. initialize the GIC per-core interface
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* 2. allow coprocessor access in non-secure modes
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* 3. switch the cpu mode (by calling "smc #0")
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*
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* Called from smp_pen by secondary cores and directly by the BSP.
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* Do not assume that the stack is available and only use registers
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* r0-r3 and r12.
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*
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* PERIPHBASE is used to get the GIC address. This could be 40 bits long,
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* though, but we check this in C before calling this function.
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*/
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ENTRY(_nonsec_init)
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#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
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ldr r2, =CONFIG_ARM_GIC_BASE_ADDRESS
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#else
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mrc p15, 4, r2, c15, c0, 0 @ read CBAR
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bfc r2, #0, #15 @ clear reserved bits
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#endif
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add r3, r2, #GIC_DIST_OFFSET @ GIC dist i/f offset
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mvn r1, #0 @ all bits to 1
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str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts
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mrc p15, 0, r0, c0, c0, 0 @ read MIDR
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ldr r1, =MIDR_PRIMARY_PART_MASK
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and r0, r0, r1 @ mask out variant and revision
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ldr r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK
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cmp r0, r1 @ check for Cortex-A7
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ldr r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK
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cmpne r0, r1 @ check for Cortex-A15
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movne r1, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9
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moveq r1, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
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add r3, r2, r1 @ r3 = GIC CPU i/f addr
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mov r1, #1 @ set GICC_CTLR[enable]
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str r1, [r3, #GICC_CTLR] @ and clear all other bits
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mov r1, #0xff
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str r1, [r3, #GICC_PMR] @ set priority mask register
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movw r1, #0x3fff
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movt r1, #0x0006
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mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec
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/* The CNTFRQ register of the generic timer needs to be
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* programmed in secure state. Some primary bootloaders / firmware
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* omit this, so if the frequency is provided in the configuration,
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* we do this here instead.
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* But first check if we have the generic timer.
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*/
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#ifdef CONFIG_SYS_CLK_FREQ
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mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
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and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
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cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
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ldreq r1, =CONFIG_SYS_CLK_FREQ
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mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
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#endif
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adr r1, _monitor_vectors
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mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors
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mrc p15, 0, ip, c12, c0, 0 @ save secure copy of VBAR
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isb
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smc #0 @ call into MONITOR mode
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mcr p15, 0, ip, c12, c0, 0 @ write non-secure copy of VBAR
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mov r1, #1
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str r1, [r3, #GICC_CTLR] @ enable non-secure CPU i/f
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add r2, r2, #GIC_DIST_OFFSET
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str r1, [r2, #GICD_CTLR] @ allow private interrupts
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mov r0, r3 @ return GICC address
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bx lr
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ENDPROC(_nonsec_init)
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#ifdef CONFIG_SMP_PEN_ADDR
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/* void __weak smp_waitloop(unsigned previous_address); */
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ENTRY(smp_waitloop)
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wfi
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ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
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ldr r1, [r1]
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cmp r0, r1 @ make sure we dont execute this code
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beq smp_waitloop @ again (due to a spurious wakeup)
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mov pc, r1
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ENDPROC(smp_waitloop)
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.weak smp_waitloop
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#endif
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