a76a6f3e04
K2G GP doesn't require the MR2 register to be programed since the default is good enough. However, newer K2G boards do need to change this register value. Therefore, instead of not writing this register if ran on a K2G board just program the value to be written to match the default/reset value. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
64 lines
1.6 KiB
C
64 lines
1.6 KiB
C
/*
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* K2G: DDR3 initialization
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*
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* (C) Copyright 2015
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include "ddr3_cfg.h"
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#include <asm/arch/ddr3.h>
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struct ddr3_phy_config ddr3phy_800_2g = {
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.pllcr = 0x000DC000ul,
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.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
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.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
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.ptr0 = 0x42C21590ul,
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.ptr1 = 0xD05612C0ul,
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.ptr2 = 0,
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.ptr3 = 0x06C30D40ul,
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.ptr4 = 0x06413880ul,
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.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
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.dcr_val = ((1 << 10)),
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.dtpr0 = 0x550F6644ul,
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.dtpr1 = 0x328341E0ul,
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.dtpr2 = 0x50022A00ul,
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.mr0 = 0x00001430ul,
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.mr1 = 0x00000006ul,
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.mr2 = 0x00000000ul,
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.dtcr = 0x710035C7ul,
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.pgcr2 = 0x00F03D09ul,
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.zq0cr1 = 0x0001005Dul,
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.zq1cr1 = 0x0001005Bul,
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.zq2cr1 = 0x0001005Bul,
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.pir_v1 = 0x00000033ul,
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.pir_v2 = 0x00000F81ul,
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};
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struct ddr3_emif_config ddr3_800_2g = {
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.sdcfg = 0x62005662ul,
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.sdtim1 = 0x0A385033ul,
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.sdtim2 = 0x00001CA5ul,
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.sdtim3 = 0x21ADFF32ul,
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.sdtim4 = 0x533F067Ful,
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.zqcfg = 0x70073200ul,
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.sdrfc = 0x00000C34ul,
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};
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u32 ddr3_init(void)
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{
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/* Reset DDR3 PHY after PLL enabled */
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ddr3_reset_ddrphy();
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ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
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ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
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return 0;
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}
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inline int ddr3_get_size(void)
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{
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return 2;
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}
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