676ae068d9
Kill off ehci-core.h It was used to specify some static controller data. To support more than one controller being active at any time we have to carry the controller data ourselfes. Change the ehci interface accordingly. NOTE: OMAP implemented the ehci stuff a bit backwards and should be fixed to do the same thing as other platforms. But the change for now is at least compile clean. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Marek Vasut <marex@denx.de>
142 lines
3.7 KiB
C
142 lines
3.7 KiB
C
/*
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* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <usb/ehci-fsl.h>
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#include <errno.h>
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#include "ehci.h"
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#define USBCTRL_OTGBASE_OFFSET 0x600
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#ifdef CONFIG_MX25
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#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6)
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#define MX25_USB_CTRL_HSTD_BIT (1<<5)
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#define MX25_USB_CTRL_USBTE_BIT (1<<4)
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#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3)
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#endif
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#ifdef CONFIG_MX31
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#define MX31_OTG_SIC_SHIFT 29
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#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
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#define MX31_OTG_PM_BIT (1 << 24)
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#define MX31_H2_SIC_SHIFT 21
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#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
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#define MX31_H2_PM_BIT (1 << 16)
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#define MX31_H2_DT_BIT (1 << 5)
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#define MX31_H1_SIC_SHIFT 13
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#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
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#define MX31_H1_PM_BIT (1 << 8)
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#define MX31_H1_DT_BIT (1 << 4)
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#endif
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static int mxc_set_usbcontrol(int port, unsigned int flags)
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{
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unsigned int v;
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#ifdef CONFIG_MX25
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v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
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MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
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#endif
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#ifdef CONFIG_MX31
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v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
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switch (port) {
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case 0: /* OTG port */
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v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK)
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<< MX31_OTG_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX31_OTG_PM_BIT;
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break;
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case 1: /* H1 port */
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v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT |
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MX31_H1_DT_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK)
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<< MX31_H1_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX31_H1_PM_BIT;
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if (!(flags & MXC_EHCI_TTL_ENABLED))
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v |= MX31_H1_DT_BIT;
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break;
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case 2: /* H2 port */
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v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT |
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MX31_H2_DT_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK)
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<< MX31_H2_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX31_H2_PM_BIT;
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if (!(flags & MXC_EHCI_TTL_ENABLED))
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v |= MX31_H2_DT_BIT;
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break;
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default:
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return -EINVAL;
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}
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#endif
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writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
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return 0;
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}
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int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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struct usb_ehci *ehci;
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#ifdef CONFIG_MX31
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struct clock_control_regs *sc_regs =
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(struct clock_control_regs *)CCM_BASE;
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__raw_readl(&sc_regs->ccmr);
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__raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
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#endif
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udelay(80);
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ehci = (struct usb_ehci *)(IMX_USB_BASE +
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(0x200 * CONFIG_MXC_USB_PORT));
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*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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setbits_le32(&ehci->usbmode, CM_HOST);
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__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
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mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
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udelay(10000);
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return 0;
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}
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/*
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* Destroy the appropriate control structures corresponding
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* the the EHCI host controller.
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*/
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int ehci_hcd_stop(int index)
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{
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return 0;
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}
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