Bryan Brinsko 97840b5d1f ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching ... The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>		2015-04-16 14:59:33 +02:00
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asm	ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching	2015-04-16 14:59:33 +02:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00