94d77fb656
Locking sequence for all the dplls is same. In the current code same sequence is done repeatedly for each dpll. Instead have a generic function for locking dplls and pass dpll data to that function. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
/*
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* clock.c
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*
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* Clock initialization for AM33XX boards.
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* Derived from OMAP4 boards
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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static void setup_post_dividers(const struct dpll_regs *dpll_regs,
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const struct dpll_params *params)
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{
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/* Setup post-dividers */
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if (params->m2 >= 0)
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writel(params->m2, dpll_regs->cm_div_m2_dpll);
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if (params->m3 >= 0)
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writel(params->m3, dpll_regs->cm_div_m3_dpll);
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if (params->m4 >= 0)
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writel(params->m4, dpll_regs->cm_div_m4_dpll);
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if (params->m5 >= 0)
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writel(params->m5, dpll_regs->cm_div_m5_dpll);
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if (params->m6 >= 0)
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writel(params->m6, dpll_regs->cm_div_m6_dpll);
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}
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static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
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{
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clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
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CM_CLKMODE_DPLL_DPLL_EN_MASK,
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DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
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}
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static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
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{
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if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
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(void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
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printf("DPLL locking failed for 0x%x\n",
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dpll_regs->cm_clkmode_dpll);
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hang();
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}
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}
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static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
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{
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clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
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CM_CLKMODE_DPLL_DPLL_EN_MASK,
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DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
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}
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static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
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{
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if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
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(void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
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printf("Bypassing DPLL failed 0x%x\n",
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dpll_regs->cm_clkmode_dpll);
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}
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}
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static void bypass_dpll(const struct dpll_regs *dpll_regs)
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{
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do_bypass_dpll(dpll_regs);
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wait_for_bypass(dpll_regs);
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}
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void do_setup_dpll(const struct dpll_regs *dpll_regs,
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const struct dpll_params *params)
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{
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u32 temp;
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if (!params)
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return;
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temp = readl(dpll_regs->cm_clksel_dpll);
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bypass_dpll(dpll_regs);
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/* Set M & N */
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temp &= ~CM_CLKSEL_DPLL_M_MASK;
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temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
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temp &= ~CM_CLKSEL_DPLL_N_MASK;
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temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
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writel(temp, dpll_regs->cm_clksel_dpll);
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setup_post_dividers(dpll_regs, params);
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/* Wait till the DPLL locks */
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do_lock_dpll(dpll_regs);
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wait_for_lock(dpll_regs);
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}
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void setup_dplls(void)
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{
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const struct dpll_params *params;
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do_setup_dpll(&dpll_core_regs, &dpll_core);
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
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do_setup_dpll(&dpll_per_regs, &dpll_per);
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writel(0x300, &cmwkup->clkdcoldodpllper);
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params = get_dpll_ddr_params();
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do_setup_dpll(&dpll_ddr_regs, params);
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}
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