Yanhong Wang 9087a6ae79 riscv: dts: jh7110: Add initial StarFive JH7110 device tree ... Add initial device tree for the JH7110 RISC-V SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>		2023-04-20 16:08:45 +08:00
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cpu	riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC	2023-04-20 16:08:44 +08:00
dts	riscv: dts: jh7110: Add initial StarFive JH7110 device tree	2023-04-20 16:08:45 +08:00
include/asm	riscv: cpu: jh7110: Add support for jh7110 SoC	2023-04-20 16:08:44 +08:00
lib	riscv: semihosting: replace inline assembly with assembly file	2023-03-06 19:24:34 -05:00
config.mk	Convert CONFIG_STANDALONE_LOAD_ADDR to Kconfig	2022-12-22 10:31:48 -05:00
Kconfig	board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig	2023-04-20 16:08:45 +08:00
Makefile	riscv: support building double-float modules	2022-10-20 15:22:21 +08:00