Lokesh Vutla 802bb57a58 ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value ... The value in SDRAM_REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value corresponding to 500us delay before starting DDR initialization sequence, and configure proper value at the end of sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>		2015-02-16 12:41:40 -05:00
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cpu	ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value	2015-02-16 12:41:40 -05:00
dts	Odroid-XU3: Add eMMC-reset node on DT	2015-02-13 17:17:10 +09:00
imx-common	imx: i2c: Zap unnecessary malloc() calls	2014-12-30 14:05:48 +01:00
include	ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value	2015-02-16 12:41:40 -05:00
lib	Merge branch 'master' of git://git.denx.de/u-boot-atmel	2015-01-26 06:42:40 -05:00
mvebu-common	arm: mvebu: Add Serdes PHY config code	2015-02-06 17:24:59 +01:00
config.mk	arm: build arch memset/memcpy in Thumb2 mode	2015-01-09 10:20:22 -05:00
Kconfig	dm: Move Raspberry Pi driver model CONFIGs to Kconfig	2015-02-12 10:35:34 -07:00
Kconfig.debug	arm: debug: add Kconfig entries for lowlevel debug	2014-10-26 22:23:12 +01:00
Makefile	Kbuild: introduce Makefile in arch/$ARCH/	2014-12-08 09:35:45 -05:00