Simon Glass 72cd085aae x86: ivybridge: Add additional LPC init ... Set up all the remaining pieces of the LPC (low-pin-count) peripheral in PCH (Peripheral Controller Hub). Signed-off-by: Simon Glass <sjg@chromium.org>		2014-11-25 06:34:01 -07:00
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cpu	x86: ivybridge: Add additional LPC init	2014-11-25 06:34:01 -07:00
dts	x86: ivybridge: Implement SDRAM init	2014-11-21 07:34:15 +01:00
include/asm	x86: ivybridge: Add PCH init	2014-11-25 06:34:00 -07:00
lib	x86: Set up edge triggering on interrupt 9	2014-11-25 06:34:00 -07:00
config.mk	x86: Remove REALMODE_BASE which is no longer used	2014-11-21 07:24:08 +01:00
Kconfig	x86: Rename chromebook-x86 to coreboot	2014-11-21 07:34:16 +01:00