6d9b82d085
LS1088A is compliant with the Layerscape Chassis Generation 3 with eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4 SDRAM memory controller with ECC, Data path acceleration architecture 2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs), QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
78 lines
2 KiB
Text
78 lines
2 KiB
Text
/*
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* NXP ls1088a SOC common device tree source
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*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/ {
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compatible = "fsl,ls1088a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x80000000>;
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/* DRAM space - 1, size : 2 GB DRAM */
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};
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gic: interrupt-controller@6000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
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<0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <1 9 0x4>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
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<1 14 0x8>, /* Physical Non-Secure PPI, active-low */
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<1 11 0x8>, /* Virtual PPI, active-low */
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<1 10 0x8>; /* Hypervisor PPI, active-low */
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};
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serial0: serial@21c0500 {
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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clock-frequency = <0>; /* Updated by bootloader */
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interrupts = <0 32 0x1>; /* edge triggered */
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};
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serial1: serial@21c0600 {
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0600 0x0 0x100>;
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clock-frequency = <0>; /* Updated by bootloader */
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interrupts = <0 32 0x1>; /* edge triggered */
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};
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fsl_mc: fsl-mc@80c000000 {
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compatible = "fsl,qoriq-mc";
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
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<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
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};
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dspi: dspi@2100000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <0 26 0x4>; /* Level high type */
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num-cs = <6>;
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};
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qspi: quadspi@1550000 {
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compatible = "fsl,vf610-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x20c0000 0x0 0x10000>,
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<0x0 0x20000000 0x0 0x10000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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num-cs = <4>;
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};
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};
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