u-boot/arch/riscv/cpu
Pragnesh Patel 5988bb9dbf riscv: ax25: cache: Remove SPL_RISCV_MMODE config check
CONFIG_IS_ENABLED(FOO) will check FOO config option for U-Boot,
SPL and TPL, so remove unnecessary CONFIG_IS_ENABLED()

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-23 10:13:23 +08:00
..
ax25 riscv: ax25: cache: Remove SPL_RISCV_MMODE config check 2020-04-23 10:13:23 +08:00
generic common: Move board_get_usable_ram_top() out of common.h 2019-12-02 18:25:04 -05:00
cpu.c riscv: add run mode configuration for SPL 2019-08-26 16:07:42 +08:00
Makefile riscv: Move trap handler codes to mtrap.S 2018-12-18 09:56:27 +08:00
mtrap.S riscv: Add option to print registers on exception 2020-02-10 14:51:08 +08:00
start.S riscv: Remove unnecessary instruction 2020-02-10 14:51:52 +08:00
u-boot-spl.lds riscv: Fix clear bss loop in the start-up code 2019-12-10 08:23:10 +08:00
u-boot.lds riscv: Fix breakage caused by linker relaxation 2020-02-10 14:50:53 +08:00