7048bb13b2
This patch fixes an stability issue seen on some vcoreiii targets, which was root caused to a cache inconsistency situation. The inconsistency was caused by having kuseg pointing to NOR area but used as a stack/gd/heap area during initialization, while only relatively late remapping the RAM area into kuseg position. The fix is to initialize the DDR right after the TLB setup, and then remapping it into position before gd/stack/heap usage. Reported-by: Ramin Seyed-Moussavi <ramin.moussavi@yacoub.de> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
70 lines
1.3 KiB
C
70 lines
1.3 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/types.h>
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#include <mach/tlb.h>
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#include <mach/ddr.h>
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DECLARE_GLOBAL_DATA_PTR;
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static inline int vcoreiii_train_bytelane(void)
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{
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int ret;
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ret = hal_vcoreiii_train_bytelane(0);
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#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
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defined(CONFIG_SOC_SERVALT) || defined(CONFIG_SOC_SERVAL)
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if (ret)
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return ret;
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ret = hal_vcoreiii_train_bytelane(1);
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#endif
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return ret;
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}
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int vcoreiii_ddr_init(void)
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{
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register int res;
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if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT)
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& ICPU_MEMCTRL_STAT_INIT_DONE)) {
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hal_vcoreiii_init_memctl();
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hal_vcoreiii_wait_memctl();
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if (hal_vcoreiii_init_dqs() || vcoreiii_train_bytelane())
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hal_vcoreiii_ddr_failed();
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}
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res = dram_check();
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if (res == 0)
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hal_vcoreiii_ddr_verified();
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else
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hal_vcoreiii_ddr_failed();
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/* Remap DDR to kuseg: Clear boot-mode */
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clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
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ICPU_GENERAL_CTRL_BOOT_MODE_ENA);
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/* - and read-back to activate/verify */
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readl(BASE_CFG + ICPU_GENERAL_CTRL);
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return res;
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}
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int print_cpuinfo(void)
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{
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printf("MSCC VCore-III MIPS 24Kec\n");
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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