Yu Chien Peter Lin 487c211ef6 configs: ae350: Enable v5l2 cache for AE350 platforms in SPL ... To reduce the code size, CONFIG_V5L2_CACHE was disabled since commit: ca06444aac Turing on does not significantly increase the size of u-boot-spl.bin, so we enable it by default to improve performance. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>		2023-02-17 19:07:48 +08:00
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cpu	configs: ae350: Enable v5l2 cache for AE350 platforms in SPL	2023-02-17 19:07:48 +08:00
dts	riscv: ae350: dts: Update L2 cache compatible string	2023-02-17 19:07:48 +08:00
include/asm	riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()	2023-02-17 19:07:48 +08:00
lib	Correct SPL uses of LMB	2023-02-10 07:41:39 -05:00
config.mk	Convert CONFIG_STANDALONE_LOAD_ADDR to Kconfig	2022-12-22 10:31:48 -05:00
Kconfig	riscv: clarify meaning of CONFIG_SBI_V02	2022-11-15 15:37:17 +08:00
Makefile	riscv: support building double-float modules	2022-10-20 15:22:21 +08:00