u-boot/arch/riscv
Conor Dooley 3f3527044d riscv: dts: fix the mpfs's reference clock frequency
The initial devicetree for PolarFire SoC incorrectly created a fixed
frequency clock in the devicetree to represent the msspll, but the
msspll is not a fixed frequency clock. The actual reference clock on a
board is either 125 or 100 MHz, 125 MHz in the case of the icicle kit.
Swap the incorrect representation of the msspll out for the actual
reference clock.

Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-15 15:37:17 +08:00
..
cpu riscv: Rename Andes PLIC to PLICSW 2022-11-03 13:27:56 +08:00
dts riscv: dts: fix the mpfs's reference clock frequency 2022-11-15 15:37:17 +08:00
include/asm riscv: Rename Andes PLIC to PLICSW 2022-11-03 13:27:56 +08:00
lib riscv: Rename Andes PLIC to PLICSW 2022-11-03 13:27:56 +08:00
config.mk kconfig / kbuild: Re-sync with Linux 4.19 2020-04-10 11:18:32 -04:00
Kconfig riscv: Rename Andes PLIC to PLICSW 2022-11-03 13:27:56 +08:00
Makefile riscv: support building double-float modules 2022-10-20 15:22:21 +08:00