Pragnesh Patel 329e023868 riscv: sifive: dts: fu540: set ethernet clock rate ... Set ethernet clock rate to 125 Mhz so that it will work with 1000Mbps, Earlier this is done by FSBL. With this change We can remove the ethernet clock rate code from FSBL. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>		2020-06-04 09:44:09 +08:00
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cpu	riscv: Add _image_binary_end for SPL	2020-06-04 09:44:08 +08:00
dts	riscv: sifive: dts: fu540: set ethernet clock rate	2020-06-04 09:44:09 +08:00
include/asm	riscv: Move all SMP related SBI calls to SBI_v01	2020-05-26 15:50:08 +08:00
lib	riscv: Move all SMP related SBI calls to SBI_v01	2020-05-26 15:50:08 +08:00
config.mk	kconfig / kbuild: Re-sync with Linux 4.19	2020-04-10 11:18:32 -04:00
Kconfig	riscv: Make SBI v0.2 the default SBI version	2020-04-23 10:14:06 +08:00
Makefile	riscv: add Kconfig entries for the code model	2018-12-18 09:56:26 +08:00