20476b51aa
Currently the driver will go through the clock ID-s and set/enable them as needed. But if the ID is unknown it will fall through the switch case to the default case which will always return 0. This is not correct and default cases should return a error code since clock ID is unknown. So lets return -EINVAL instead. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
80 lines
1.5 KiB
C
80 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Clock drivers for Qualcomm IPQ40xx
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*
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* Copyright (c) 2020 Sartura Ltd.
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*
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* Author: Robert Marko <robert.marko@sartura.hr>
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*
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*/
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#include <clk-uclass.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
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struct msm_clk_priv {
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phys_addr_t base;
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};
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ulong msm_set_rate(struct clk *clk, ulong rate)
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{
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switch (clk->id) {
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case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
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/* This clock is already initialized by SBL1 */
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return 0;
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default:
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return -EINVAL;
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}
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}
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static int msm_clk_probe(struct udevice *dev)
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{
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struct msm_clk_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr(dev);
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if (priv->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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return 0;
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}
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static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
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{
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return msm_set_rate(clk, rate);
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}
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static int msm_enable(struct clk *clk)
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{
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switch (clk->id) {
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case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
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/* This clock is already initialized by SBL1 */
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return 0;
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case GCC_PRNG_AHB_CLK: /*PRNG*/
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/* This clock is already initialized by SBL1 */
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return 0;
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default:
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return -EINVAL;
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}
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}
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static struct clk_ops msm_clk_ops = {
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.set_rate = msm_clk_set_rate,
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.enable = msm_enable,
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};
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static const struct udevice_id msm_clk_ids[] = {
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{ .compatible = "qcom,gcc-ipq4019" },
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{ }
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};
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U_BOOT_DRIVER(clk_msm) = {
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.name = "clk_msm",
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.id = UCLASS_CLK,
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.of_match = msm_clk_ids,
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.ops = &msm_clk_ops,
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.priv_auto_alloc_size = sizeof(struct msm_clk_priv),
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.probe = msm_clk_probe,
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};
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