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Prabhakar Kushwaha 1d384eca61 powerpc/mpc85xx:Update processor defines for T1040 
T1040 SoC has
    - DDR controller ver 5.0
    - 2 PLLs
    - 8 IFC Chip select
    - FMAN Muram 192K
    - No Srio
    - Sec controller ver 5.0
    - Max CPU update for its personalities

So, update the defines accordingly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16 16:13:11 -07:00
..
cpu powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2 2013-10-16 16:13:11 -07:00
include/asm powerpc/mpc85xx:Update processor defines for T1040 2013-10-16 16:13:11 -07:00
lib Merge branch 'master' of git://git.denx.de/u-boot-i2c 2013-07-24 09:50:24 -04:00
config.mk Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00