This patch implements a workaround to fix DDR3 memory issue. The code for workaround detects PGSR0 errors and then preps for and executes a software-controlled hard reset.In board_early_init, where logic has been added to identify whether or not the previous reset was a PORz. PLL initialization is skipped in the case of a software-controlled hard reset. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Keegan Garcia <kgarcia@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> |
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am43xx | ||
am335x | ||
am3517crane | ||
beagle | ||
dra7xx | ||
evm | ||
ks2_evm | ||
omap5_uevm | ||
panda | ||
sdp3430 | ||
sdp4430 | ||
ti814x | ||
ti816x | ||
tnetv107xevm |