Chris Kuethe 1005ccda97 patch - arm - define SYS_CACHELINE_SIZE for mx5 ... mx5 is a cortex-a8 which has 64 byte cache lines. i'll need this for adding gadget support to usbarmory, but it's a property common the the entire SoC family - may as well make it available to all MX5 boards Works on usbarmory; compile-tested on mx53loco and mx51_efikamx too Signed-off-by: Chris Kuethe <chris.kuethe@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Matthew Starr <mstarr@hedonline.com> Cc: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Chris Kuethe <chris.kuethe@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>		2015-06-09 12:00:42 +02:00
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asm	patch - arm - define SYS_CACHELINE_SIZE for mx5	2015-06-09 12:00:42 +02:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00