This updates supports_extension() implementation to use the desc
string from the cpu driver whenever possible, which avoids the
reading of misa CSR for S-mode U-Boot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
This adds all exception codes in encoding.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
The standard RISC-V ISA sets aside a 12-bit encoding space for up
to 4096 CSRs. This adds all known CSR numbers as defined in the
RISC-V Privileged Architecture Version 1.10.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
With DM CPU driver, the non-DM version of print_cpuinfo() is no
longer needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
This calls cpu_probe_all() to probe all available cpus.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Increase the heap size for the pre-relocation stage, so that CPU
driver can be loaded.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Add the QEMU RISC-V platform-specific Kconfig options, to include
CPU and timer drivers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
This adds an implementation of riscv_get_time() API that is using
rdtime instruction.
This is the case for S-mode U-Boot, and is useful for processors
that support rdtime in M-mode too.
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
This adds U-Boot syscon driver for SiFive's Core Local Interruptor
(CLINT). The CLINT block holds memory-mapped control and status
registers associated with software and timer interrupts.
This driver implements the riscv_get_time() API as required by
the generic RISC-V timer driver, as well as some other APIs that
are needed for handling IPI.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
So far we have a Kconfig option for supervisor mode. This adds an
option for the machine mode.
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
There is no need to expose RISCV_NDS to the Kconfig menu as it is
an ax25-specific option. Introduce a dedicated Kconfig option for
the cache ops of ax25 platform and use that to guard the cache ops.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
To enumerate devices on the /soc/ node, create a "simple-bus"
driver to match "riscv-virtio-soc".
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
RISC-V has two code models, medium low (medlow) and medium any (medany).
Medlow limits addressable memory to a single 2 GiB range between the
absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory
to any single 2 GiB address range.
By default, medlow is selected for U-Boot on both 32-bit and 64-bit
systems.
The -mcmodel compiler flag is selected according to the Kconfig
configuration.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
[bmeng: adjust to make medlow the default code model for U-Boot]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Add the initial support for Elgin R1 board, which is based on the
RV1108 SoC and has the following features currently supported in
U-Boot:
- UART
- eMMC
- USB
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This is a sync with kernel mainline dts.
The U-Boot eMMC does not need to care about the power for Rockchip
SoCs, because if the board is using eMMC, the power will default on
(for bootrom), so the 'vmmc', 'vqmmc' is only useful for SD in U-Boot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
vcc5v0_host and usbhub_enable share gpio4 RK_PA3,
which is a problem during probing (the second probe
will trigger a -EBUSY, when trying to get the gpio handle).
An analysis of the situation shows, that both regulators
are actually describing the same supply.
This patch removes the (currenlty not successful probing)
regulator vcc5v0_host from the DTS and adds the pinctrl-*
setting to usbhub_enable.
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Phiilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Commit 4687919684 ("serial: Remove DM_FLAG_PRE_RELOC flag in various
drivers") essentially drops flag DM_FLAG_PRE_RELOC from serial_pl01x
driver for Poplar platform, because the platform falls into the
following strategy category made by the commit.
Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device tree
Before the commit lands, Poplar platform works by statically declaring
pl011 serial device via U_BOOT_DEVICE() with DM_FLAG_PRE_RELOC flag set
in the driver. But since Poplar also supports device configuration from
device tree, the commit practically drops the flag for Poplar, and hence
breaks the platform from booting.
This patch changes platform code and device tree to initiate pl011
serial device from device tree rather than static declaration, so that
above strategy about DM_FLAG_PRE_RELOC applies to Poplar, and therefore
the reported boot failure gets fixed.
Reported-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Fixes: 4687919684 ("serial: Remove DM_FLAG_PRE_RELOC flag in various drivers")
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When DM_USB is used, either the USB controllers are bound when the DTB
is parsed (when OF_CONTROL is enabled) or they are bound using the
U_BOOT_DEVICES() macro.
In the later case, the platform data is passed in a struct ti_musb_platdata
because it cannot be read from the DTB.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable DM for USB peripheral in the musb-new driver.
Also make sure that the driver can be used in the SPL.
This implies that:
* the driver must work with and without the OF_CONTROL option. That
in turn, implies that the platform data can be passed in a struct
ti_musb_platdata or be read from the dtb
* usb.o is linked in the SPL if host support is enabled
Another change is that the driver does not fail to bind (and stop the boot
process) if one of the child driver does not bind. Reporting the error is
enough. This kind of error would appear if the port is configured in the
DTS but the driver is not activated in the config.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
USB1 can be used by the romboot on all am4372 platforms to download a
firmware (SPL in our case).
It makes sense to enable USB1 in the SPL to download u-boot.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This file is used to override the values found in am4372.dtsi
Use it to fix the "compatible" options for the controllers used
to support the USB (parent bus and syscons).
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
At present these parameters are hard-coded in the sdl interface code.
Allow them to be specified by the driver instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Update sandbox's device tree and config to use driver model for sound. Use
the double buffer for sound output so that we don't need to wait for the
sound to complete before returning.
Signed-off-by: Simon Glass <sjg@chromium.org>
Update snow's device tree and config to use driver model for sound. Also
update the others as best we can.
Spring does not appear to have audio support in the kernel. The smdk5250
and smdk5420 boards use a wolfson codec which I cannot test with. So the
only boards that is tested and known to work are snow, pit and pi.
Signed-off-by: Simon Glass <sjg@chromium.org>
Allow setting the i2s pinmux correctly on exyno5420 so that i2c can be
used on that SoC. Also rename EXYNOS_AUDSS to something consistent with
other naming.
Signed-off-by: Simon Glass <sjg@chromium.org>
The current dev_read...() functions use s32 and u32 which are convenient
for device tree but not so useful for normal code, which often wants to
use normal integers for values.
Add a helper which supports returning an unsigned int. Also add signed
versions of the unsigned readers.
Signed-off-by: Simon Glass <sjg@chromium.org>
The sound driver pulls together the audio codec and i2s drivers in order
to actually make sounds. It supports setup() and play() methods. The
sound_find_codec_i2s() function allows locating the linked codec and i2s
devices. They can be referred to from uclass-private data.
Add a uclass and a test for sound.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present we use a single buffer for sound which means we cannot be
playing one sound while queueing up the next. This wouldn't matter except
that a long sound (more than a second) has to be created as a single
buffer, thus using a lot of memory. To better mimic what real sound
drivers do, add support for double buffering in sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
The i2s bus is commonly used with audio codecs. It provides a way to
stream digital data sychronously in both directions. U-Boot only supports
audio output, so this uclass is very simple, with a single tx_data()
method.
Add a uclass and a test for i2s.
Signed-off-by: Simon Glass <sjg@chromium.org>
An audio codec provides a way to convert digital data to sound and vice
versa. Add a simple uclass which just supports setting the parameters for
the codec.
Signed-off-by: Simon Glass <sjg@chromium.org>
The U-Boot sound system provides basic support for beeping. At present it
does not use driver model, but it needs to be converted. Add an option to
enable driver model for sound. For now it is not connected to anything.
Future work will add drivers which use this option. It will then be
removed once everything is converted.
Signed-off-by: Simon Glass <sjg@chromium.org>
For snow the codec is at address 0x11 on the i2c bus, in 7-bit format.
The device tree and code are in 8-bit format (i.e. shifted left one bit).
Fix both. Fix pit in a similar way.
Signed-off-by: Simon Glass <sjg@chromium.org>
There is no need for an embedded device tree for this board so let the
build process generate a separate u-boot.dtb file instead.
Signed-off-by: Felix Brack <fb@ltec.ch>
Add support for lx2160a SoC
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Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq
Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC
[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini <trini@konsulko.com>
- init DRAM for RK322x in SPL
- add FAN53555 PMIC/regulator driver
- update MicroCrystal RV3029 driver to Kconfig and sync from Linux
- add bootcount uclass and first DM-driver for bootcount
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Merge tag 'for-master-20181210' of git://git.denx.de/u-boot-rockchip
Improvements:
- init DRAM for RK322x in SPL
- add FAN53555 PMIC/regulator driver
- update MicroCrystal RV3029 driver to Kconfig and sync from Linux
- add bootcount uclass and first DM-driver for bootcount
Now that we have FAN53555 support, we can enable the regulators in our
DTS. To make these easier to identify on the U-Boot commandline, we
rename them to the names of the voltage rails they control.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The DRA7 platforms requires that the dtb used in the SPL really matches the
platform to have the best MMC performances.
To detect the board type/version an I2C EEPROM is read. This requires that
DM is initialized before the detection. As a consequence we must reset the
DM after the board detection is a new dtb would better match the platform.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C
API when DM_I2C is used. The goal is to eventually remove DM_I2C_COMPAT
when all I2C "clients" have been migrated to use the DM API.
This a step in that direction for the TI based platforms.
Build tested with buildman:
buildman -dle am33xx ti omap3 omap4 omap5 davinci keystone
boot tested with:
am335x_evm, am335x_boneblack, am335x_boneblack_vboot (DM version),
am57xx_evm, dra7xx_evm, k2g_evm, am437x_evm
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
In order to use DM_I2C, we need to move the board detection after the
early SPL initialization.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
If DM_I2C is used , the I2C controllers must be registered as U_BOOT_DEVICE
because OF_CONTROL is not used in the SPL.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This allows the driver to be used without OF_CONTROL.
AM335x support DM_SPL but does not use SPL_OF_CONTROL. Enabling DM_I2C in
SPL thus requires that the omap I2C can be passed platdata.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Move away from SoC specific headers to handle different register layout.
Instead use driver data to get appropriate register layouts like in the
kernel. While at it, perform some mostly cosmetic alignment/cleanup in
the functions being updated.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Up until now the call to initialize the USB subsystem was hardcoded
for U-Boot running as an EFI payload. This was used to enable the
use of a USB keyboard in the U-Boot shell. However not all boards
might need this functionality. As initializing the USB subsystem can
take a considerable amount of time (several seconds on some boards),
we now initialize the USB subsystem only if U-Boot is configured to
use USB keyboards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Up until now the call to initialize the USB subsystem was hardcoded
for U-Boot running as a coreboot payload. This was used to enable
the use of a USB keyboard in the U-Boot shell. However not all boards
might need this functionality. As initializing the USB subsystem can
take a considerable amount of time (several seconds on some boards),
we now initialize the USB subsystem only if U-Boot is configured to
use USB keyboards.
Signed-off-by: Thomas RIENOESSL <thomas.rienoessl@bachmann.info>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
At present the Kconfig options (CONFIG_I8259_PIC and CONFIG_APIC)
do not include a prompt message, which makes it impossible to
be disabled from a board defconfig file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
mask_irq(), unmask_irq() and specific_eoi() are provided by the
i8259 PIC driver and should be wrapped with CONFIG_I8259_PIC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
There are still systems running which do not have any LAPIC or even
IOAPIC. Responsible MSRs for those do not exist and the systems are
crashing on trying to setup LAPIC.
This commit makes the APIC stuff able to switch off for those boards
which dont' have an LAPIC / IOAPIC.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Make the indentation aligned with what used elsewhere in U-Boot.
No functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Intel Tangier SoC has RTC inside. So, enable it in ACPI.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Similar to Clearfog rev 2.1, GPIO 19 also used to reset onboard ethernet
PHY.
This patch depend on
net: mvneta: Add GPIO configuration support
[URL: https://patchwork.ozlabs.org/patch/1007736/]
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-By: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-By: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Enable SPI flash support under U-Boot and SPL. The ENV size and offset,
ported from U-Boot 2013.01 Marvell version: 2015_T1.0p16
To create U-Boot image for SPI flash, user would need to replace
* CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC with CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
* CONFIG_ENV_IS_IN_MMC with CONFIG_ENV_IS_IN_SPI_FLASH
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-By: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-By: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Enable Marvell I2C driver and I2C IO expander. Set default bus to
external I2C bus. Define I2C aliases in device tree so it can be
recognized by the driver.
Signed-off-by: Aditya Prayoga <aditya@kobol.io>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-By: Dennis Gilmore <dgilmore@redhat.com>
Reviewed-By: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
When we clear a pmic_bus bit, we do a read-modify-write operation.
We waste some time however, by writing back the exact samea value
that was already set in the chip. Let us thus only do the write
in case data was changed.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Priit Laes <plaes@plaes.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
For a small SPL, it should be possible to build without SPI(-flash) drivers
or wihout MMC drivers.
For this to work, we have to change from 'select'ing options to 'imply'ing
them.
With this change, I can have SPL trimmed to my hard-wired starting method
(SPI-NOR or MMC) while still including all drivers in U-Boot.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This is required when DM_USB is used, to bind the USB phys.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
syscon_regmap_lookup_by_phandle() can be used to get the regmap of a syscon
device from a reference in the DTS. It operates similarly to the linux
version of the namesake function.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Using CONFIG_DM_USB for this purpose prevents using DM_USB for host and not
for device.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
This patch fixes the problem that u-boot will not start unless icache is
enabled early.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This patch fixes the problem that "main memory domain AXI secure access
protection error" occurs. Exclude the area (0x43f00000 to 0x47DFFFFF)
set by DBSC from the map area.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This patch fixes the problem that "main memory domain AXI secure
access protection error" occurs when booting Cortex-A53. Exclude
the area (0x43f00000 to 0x47DFFFFF) set by DBSC from the map area.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This patch synchronizes the am33xx SoC specific files with those from
Linux 4.20.0. Hence all board maintainers of am33xx based boards are
on the cc list.
The main purpose of this patch is to prevent further diverging of the
dts files from U-Boot and those from Linux. It aims to set the stage
for the synchronization of board specific dts files. Example: I'm the
maintainer of the PDU001 board: once this patch is applied successfully
I will make changes to the board specific dts file in Linux only and
then post a patch with a copy of this exact dts file to U-Boot. This
will make U-Boot and Linux remain in sync.
The stumbling block of https://patchwork.ozlabs.org/patch/943627 was
removed by the patch https://patchwork.ozlabs.org/patch/962428 from
Lokesh Vutla (many thanks!). This omap-serial driver allows using the
Linux am33xx.dtsi file in U-Boot.
Other changes to dts and dtsi files made by this patch are mainly to
prevent _new_ warnings during the build process. Especially the warning
at pinmux@800 stating 'unnecessary #address-cells/#size-cells without
"ranges" or child "reg"' was not removed. This warning is a good example
showing the benefit of the synchronization: if it needs to be fixed it
will be fixed in Linux and ported back to U-Boot.
Buildman reports all 46 am33xx SoC based boards to build fine, with
warnings of course. Nevertheless this patch should be tested thoroughly
on as many boards as possible to prevent any collateral damage.
Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
In some STM32 SoC packages, GPIO bank has not always 16 gpios.
Several cases can occur, gpio hole can be located at the beginning,
middle or end of the gpio bank or a combination of these 3
configurations.
For that, gpio bindings offer the gpio-ranges DT property which
described the gpio bank mapping.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This patch enables CONFIG_BLK as well as CONFIG_DM_MMC for the PDU001
board. It depends on Patrice Chotard's patch 'power: regulator: denied
disable on always-on regulator' which prevents power cycling the vmmc
supply. Without this patch the board will not boot as vmmc is
unfortunately used by other board components, not just eMMC and micro SD
card. Furthermore my patch 'dts: am335x-pdu001: Fix polarity of card
detection input' is required to boot from external micro SD card. Without
this patch no SD card will be detected and hence booting will fail.
Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
When a micro SD card is inserted in the PDU001 card cage, the card
detection switch is opened and the corresponding GPIO input is driven
by a pull-up. Hence change the active level of the card detection
input from low to high.
Signed-off-by: Felix Brack <fb@ltec.ch>
Add test for the SPL binary size and the bss section size.
This will throw an error at build time if the SPL sections
do not fit in the designated RAM area, thus avoiding oversizing the SPL.
Based on original work by Wenyou Yang.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Protect configuration registers with a hardware spinlock.
If a hwspinlock is defined in the device-tree node used it
to be sure that none of the others processors on the SoC could
change the configuration at the same time.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Implement hardware spinlock support for STM32MP1.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This is uclass for Hardware Spinlocks.
It implements two mandatory operations: lock and unlock
and one optional relax operation.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
NXP layerscape architecture Chassis 3.2 builds upon chassis3
architecture with changes like DDR Memory map change,
removal of IFC and support of upto 8 I2C controller.
Patch add README.lsch3_2 and the above changes under
macro CONFIG_NXP_LSCH3_2.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Some lsch3 based SoCs like lx2160a contains three
serdes modules.
Add support for third serdes protocol in lsch3
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
One ls2080a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
One ls1088a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
