Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.
Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Without a prompt in Kconfig, SECURE_BOOT cannot be selected by
defconfig. The option was dropped unintentionally when defconfig
files were cleaned up. Three targets were impacted
ls1043ardb_SECURE_BOOT, ls2080ardb_SECURE_BOOT,
ls2080aqds_SECURE_BOOT.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Update bootscript and its hdr addresses for Layerscape Chasis 3
based platforms instead of individual SoCs.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch binds the sys_info->freq_systembus to Platform PLL, and
implements the IPs' clock function individually.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
like LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of differences, for instance, the IP modules have different
dividers to derive its clock from Platform PLL. And the core
cluster PLL and platform PLL maybe have different reference
clocks, such as LS1012A. Another problem is which clock/PLL
should be described by sys_info->freq_systembus, it is confused
in Layerscape Chissis 2.
This patch is to bind the sys_info->freq_systembus to the Platform
PLL, and handle the different divider of IP modules separately
between different SoCs, and separate reference clocks of core
cluster PLL and platform PLL.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.
For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The LS1012A processor has two integrated USB controllers.
One is USB2.0 controller, the other is USB3.0 controller that
allow direct connection to the USB ports with appropriate
protection circuitry and power supplies.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Clear the content to zero and the ECC error bit of OCRAM1/2.
The OCRAM must be initialized to ZERO by the unit of 8-Byte before
accessing it, or else it will generate ECC error. And the IBR has
accessed the OCRAM before this initialization, so the ECC error
status bit should to be cleared.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The real size of OCRAM is 128KiB, so correct the size of OCRAM.
And OCRAM reserved 2MiB space, then add a new macro to describe
it, which is used for MMU setup.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The patch enables PCIe in ls2080a defconfigs and
removes unused PCIe related macro defines.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For the function alloc_stream_ids() append_mmu_masters() and
fdt_fixup_smmu_pcie() there are no related definitions and they
are never called. So the patch removes the unnecessary declares.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
It is recommended to set forced-order mode in RNI-6,
RNI-20 for performance optimization in LS2088A.
Both LS2080A, LS2088A families has CONFIG_LS2080A define.
As above update is required only for LS2088A, skip this
for LS2080A SoC family.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add the i2c_5 node and pmic as its child node.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
For Getting from uclass, use the "max8998-pmic" as name.
It also needs to change the dt-node's name as "max8998-pmic".
Otherwise, it doesn't find the pmic device.
Because it's only searching for 'max8998_pmic'.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Initialize SBC and Support Card in U-Boot proper instead of SPL.
We may run different firmware (ex. ARM Trusted Firmware) before
U-Boot, and basic SoC initialization may be done there. In that
case, SPL may not be used.
The motivation for preparing SBC and Support Card in SPL was to use
LED for early debugging, but this is not mandatory to boot SoCs.
With this commit, LED will be unavailable in SPL, but we can use a
debug serial instead. So, this change will not be a big deal.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Merge init-*.c into a single file using a table of callbacks because
the initialization flow is almost common among SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The code here is cluttered due to the switch statement. Introduce a
table of callbacks to clean up the initialization code across SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Splitting reset assertion (support_card_reset) and deassertion
(support_card_init) is not adding much value any more. Handle
all the initialization of Support Card in support_card_init(),
then remove support_card_reset().
Also, detect_num_flash_banks() can have a static qualifier.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, memconf-sld3.c and memconf-pxs2.c duplicate the code.
There are 3 patterns in terms of MEMCONF init:
- DRAM 2 channels: LD4, sLD8, Pro4, Pro5, LD11
- DRAM 3 channels: sLD3
- DRAM 3 channels (Ch2 is disable by MEMCONF[21]): Pxs2, LD20
All of them can be moved into a single file by a little more
refactoring.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The clock enable bits for UMC are more SoC-specific than for
the other hardware blocks. Separate the UMC clocks and the other
clocks for better code reuse across SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
At first, we thought the LD20 PLL setting would be board dependent,
but this argument turned out unneeded after all.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Dropped becuase
- driver not used any board.
- no dm conversion.
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Richard Retanubun <richardretanubun@ruggedcom.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
Acked-by: Angelo Dureghello <angelo@sysam.it>
The OrangePi Zero can happily use the EMAC along with its integrated
PHY to use Ethernet (for TFTP booting, for instance).
Add the emac node to the board .dts by copying it from the OrangePi One
DT.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add a proper device tree file for Orange Pi Zero boards from Xunlong,
which come with a Allwinner H2+ SoC (similar to H3).
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The nanopi already had the CONFIG_SUN8I_EMAC=y enabled in it's defconfig
file, but was missing the &emac the device tree entry.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Right now the SPL is trying to load u-boot based on defines, i.e. one
has to define CONFIG_SPL_NAND_SIMPLE to boot from NAND,
or CONFIG_SPL_SPI_LOAD to boot from SPI FLASH, etc...
This prevent us from having a single SPL image that is able to boot from
all media, and one need to build an image for each medium. This
commit is replacing the #ifdef that select the boot medium by reading
the value of the boot pins (via the BOOTCFG register).
Now a single SPL image will be able to read from the boot pin to know
which device should be used to load u-boot.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Using CONFIG_IS_ENABLED() doesn't work in SPL. This patch replaces the only
occurrence of CONFIG_IS_ENABLED() in start.S to a regular #if defined().
It also adds "&& !defined(CONFIG_SPL_BUILD)" to that #if statement because
the spin-table code can't currently work in SPL, and the spin-table file
isn't even compiled in SPL.
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
On AM33xx devices the secure ROM uses a different call index for
signature verification, the function and arguments are the same.
Signed-off-by: Andrew F. Davis <afd@ti.com>
This re-syncs the MACH_TYPE_xxx values from the Linux Kernel v4.9
release. In addition this removes all of the machine_arch_type and
machine_is_xxx logic that is unused in U-Boot. This removal removes a
large number of otherwise unused CONFIG values from the list to be
converted.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Adam Ford <aford173@gmail.com>
Isp-camera preview image will be broken when dual screen display mode.
This patch set isp/vop qos level higher to solve this problem.
We have verified this patch on rk3288-miniarm board.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
rk3399 has two clock-controller: cru and pmucru, update the
rockchip_get_crui() API, and rockchip_get_clk() do not used for
other module.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The popmetal board using a HOST_VBUS_DRV gpio signal to control the
USB host port 5V power, add a fix regulator and pinctrl for it, and
enable the USB host1 controller with the vbus-supply.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip: tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
With entry_point now being an unsigned long we need to adapt the last
two debug prints to use %lX not %X.
Fixes: 11e1479b9e ("SPL: make struct spl_image 64-bit safe")
Signed-off-by: Tom Rini <trini@konsulko.com>
Move (and rename) the following CONFIG options to Kconfig:
CONFIG_DAVINCI_MMC (renamed to CONFIG_MMC_DAVINCI)
CONFIG_OMAP_HSMMC (renamed to CONFIG_MMC_OMAP_HS)
CONFIG_MXC_MMC (renamed to CONFIG_MMC_MXC)
CONFIG_MXS_MMC (renamed to CONFIG_MMC_MXS)
CONFIG_TEGRA_MMC (renamed to CONFIG_MMC_SDHCI_TEGRA)
CONFIG_SUNXI_MMC (renamed to CONFIG_MMC_SUNXI)
They are the same option names as used in Linux.
This commit was created as follows:
[1] Rename the options with the following command:
find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e '
s/CONFIG_DAVINCI_MMC/CONFIG_MMC_DAVINCI/g
s/CONFIG_OMAP_HSMMC/CONFIG_MMC_OMAP_HS/g
s/CONFIG_MXC_MMC/CONFIG_MMC_MXC/g
s/CONFIG_MXS_MMC/CONFIG_MMC_MXS/g
s/CONFIG_TEGRA_MMC/CONFIG_MMC_SDHCI_TEGRA/g
s/CONFIG_SUNXI_MMC/CONFIG_MMC_SUNXI/g
'
[2] Commit the changes
[3] Create entries in driver/mmc/Kconfig.
(copied from Linux)
[4] Move the options with the following command
tools/moveconfig.py -y -r HEAD \
MMC_DAVINCI MMC_OMAP_HS MMC_MXC MMC_MXS MMC_SDHCI_TEGRA MMC_SUNXI
[5] Sort and align drivers/mmc/Makefile for readability
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
MIPS no longer needs to have its own version of this macro now.
Fixes: 2a6713b09b ("move UL() macro from armv8/mmu.h into common.h")
Signed-off-by: Tom Rini <trini@konsulko.com>
Xilinx ATF extending options for passing images from BL2(FSBL)
to BL31. U-Boot SPL is FSBL replacement that's why it should generate
handoff structure the same. Support only one entry which is U-Boot in
EL2 itself. When FIT image is adopted structure generate should be data
driven.
Currently ATF is placing this structure at the beggining of OCM which is
rewriting early parts of ATF which should be unused at that time.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add a string description for SYS_VENDOR to allow configuring boards from
other vendors than just "xilinx".
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core
which fixes some silicon bugs that needed software workarounds
in Version 1.0 that was used on Zynq systems.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable and use the clock driver routine
defined in clock driver toset required
clock appropriately.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Added the idle-states node to describe zynqmp idle states. Only cpu-sleep-0
idle state is added in this patch. References to the idle-states node are
added in all CPU nodes. Time values: entry/exit latencies and min-residency,
needs to be tuned. arm,psci-suspend-param is selected to comply with PSCIv1.0
and Extended StateID format.
Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com>
Acked-by: Will Wong <willw@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Just sync between version. Others zynqmp boards have this setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The watchdog clock node is missing.
Add the same. This solves the below error.
cdns-wdt fd4d0000.watchdog: input clock not found
cdns-wdt: probe of fd4d0000.watchdog failed with error -2
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Though the keyboard driver for GPIO buttons(gpio-keys) will continue to
check for/support the legacy "gpio-key,wakeup" boolean property to
enable gpio buttons as wakeup source, "wakeup-source" is the new
standard binding.
This patch replaces the legacy "gpio-key,wakeup" with the unified
"wakeup-source" property in order to avoid any futher copy-paste
duplication.
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi-max-frequency for spi bus depends on devices which are
connected to it. Remove this parameter from dtsi file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add usb ether gadget device with usb_ether_init() when
CONFIG_DM_ETH and CONFIG_USB_ETHER are defined.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The SPL load address changes based on boot type in HS devices,
ISW_ENTRY_ADDR is used to set this address for AM43xx based SoCs
for similar reasons. Add this same logic for AM33xx devices.
Also make the default value for ISW_ENTRY_ADDR correct for GP
devices based on SoC, HS devices already pick the correct
value in their defconfig.
Signed-off-by: Andrew F. Davis <afd@ti.com>
When TI_SECURE_DEV_PKG is not defined we warn that the file '*_HS' was
not generated but generate an unsigned one anyway, first fix this
warning to say that it was generated but not secured.
When the user then exports TI_SECURE_DEV_PKG after getting this warning,
and tries to re-build, 'make' will detect the build artifacts as
unchanged and so assume they do not need to be re-generated. This causes
it to fail to sign the files and it will pack unsigned files into the
final image, even though TI_SECURE_DEV_PKG is now correctly defined and
working.
Fix this by using FORCE on the targets causes them to be re-run even if
the dependent files have not changed.
This then causes another issue. We currently rename the signed dtb files
to overwrite the non-signed ones. We do this so the 'mkimage' tool gives
the packaged dtb sections the correct name. If we do not rename the files
then SPL will not find them during boot.
Fix this by renaming the dtb files by appending _HS to the end of the
filename, after the ".dtb", this causes them to still be named correctly
in the FIT blob.
Signed-off-by: Andrew F. Davis <afd@ti.com>
These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.
Signed-off-by: York Sun <york.sun@nxp.com>
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.
Signed-off-by: York Sun <york.sun@nxp.com>
Add option SYS_FSL_ERRATUM_ESDHC111, SYS_FSL_ERRATUM_ESDHC13,
SYS_FSL_ERRATUM_ESDHC135, SYS_FSL_ERRATUM_ESDHC_A001 to mmc Kconfig.
Move existing macros to related Kconfig.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate bk4r1]
Signed-off-by: Tom Rini <trini@konsulko.com>
Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini <trini@konsulko.com>
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC
and ARM SoCs, move it to Kconfig under the driver.
Signed-off-by: York Sun <york.sun@nxp.com>
Use Kconfig SYS_PPC_E500_DEBUG_TLB and clean up existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate 8572]
Signed-off-by: Tom Rini <trini@konsulko.com>
Now that the SPL is ready to be compiled in AArch64 and the DRAM
init code is ready, enable SPL support for the A64 SoC and in the
Pine64 defconfig.
For now we keep the boot0 header in the U-Boot proper, as this allows
to still use boot0 as an SPL replacement without hurting the SPL use
case.
We disable FEL support for now by making its compilation conditional
and disabling it for ARM64, as the code isn't ready yet.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Fix the output of the DRAM size on AArch64 SPLs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
According to Jens disabling the on-die-termination should set bit 5,
not bit 1 in the respective register. Fix this.
Reported-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The A64 DRAM controller is very similar to the H3 one,
so the code can be reused with some small changes.
This refactoring does not change the code size for the existing H3 part.
[Andre: rework from #ifdefs to using socid parameters in static
functions, minor fixes, merging in fixes from Jens]
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as
well) only applied coarse delay line settings, with one delay value for
all the data lines in each byte lane and one value for the control lines.
Instead of setting the delays for whole bytes only allow setting it for
each individual bit. Also add support for address/command lane delays.
For the purpose of this patch the rules for the existing coarse settings
were just applied to the new scheme, so the actual register writes don't
change for the H3. Other SoCs will utilize this feature later properly.
With a stock GCC 5.3.0 this increases the dram_sun8i_h3.o code size from
2296 to 2344 Bytes.
[Andre: move delay parameters into macros to ease later sharing, use
defines for numbers of delay registers, extend commit message]
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The IOCR registers got renamed to BDLR to match the public
documentation of similar controllers.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
So far the MBUS priority setup was done by writing "magic" values taken
from a DRAM controller register dump after a boot0 run.
By peeking at the Linux (sic!) MBUS driver [1] from the Allwinner BSP
kernel, we learned more about the actual meaning of those bits.
Add macros and refactor the setup function to make the MBUS setup much
more readable and meaningful.
The actual values used now are a transformation of the values used
before, which are assembled by the new code to result in the same register
writes. So this rework does not change any settings, also the code size
stays the same.
The respective source files in the BSP kernel had a proper GPL header,
so lifting this code and information into U-Boot is legal.
[Andre: provide a convenience macro to fit definitions on one line]
[1] https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65/drivers/bus/sunxi_mbus.c
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The Allwinner A64 SoC starts execution in AArch32 mode, and both
the boot ROM and Allwinner's boot0 keep running in this mode.
So U-Boot gets entered in 32-bit, although we want it to run in AArch64.
By using a "magic" instruction, which happens to be an almost-NOP in
AArch64 and a branch in AArch32, we differentiate between being
entered in 64-bit or 32-bit mode.
If in 64-bit mode, we proceed with the branch to reset, but in 32-bit
mode we trigger an RMR write to bring the core into AArch64/EL3 and
re-enter U-Boot at CONFIG_SYS_TEXT_BASE.
This allows a 64-bit U-Boot to be both entered in 32 and 64-bit mode,
so we can use the same start code for the SPL and the U-Boot proper.
We use the existing custom header (boot0.h) functionality, but restrict
the existing boot0 header reservation to the non-SPL build now. A SPL
wouldn't need such header anyway. This allows to have both options
defined and lets us use one for the SPL and the other for U-Boot proper.
Also add arch/arm/mach-sunxi/rmr_switch.S, which contains the original
ARM assembly code and instructions how to re-generate the encoded
version.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
For prepending some board specific header area to U-Boot images we
were so far including a header file with a macro definition containing
the actual header specification.
This works fine if there are just a few statements and if there is only
one alternative.
However adding more complex code quickly gets messy with this approach,
so let's just drop that intermediate macro and let the #include actually
insert the code directly.
This converts the callers and the callees, but doesn't change anything
at this point.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
