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Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next

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This commit is contained in:
Tom Rini 2022-09-26 11:27:30 -04:00
commit ffa2c88bcf
27 changed files with 217 additions and 1287 deletions
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51
arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
View file

@ -129,6 +129,57 @@
phy-reset-post-delay = <1>;
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
lan1: port@0 {
phy-handle = <&sw_phy0>;
};
lan2: port@1 {
phy-handle = <&sw_phy1>;
};
lan3: port@2 {
phy-handle = <&sw_phy2>;
};
lan4: port@3 {
phy-handle = <&sw_phy3>;
};
};
mdios {
#address-cells = <1>;
#size-cells = <0>;
mdio@0 {
reg = <0>;
compatible = "microchip,ksz-mdio";
#address-cells = <1>;
#size-cells = <0>;
sw_phy0: ethernet-phy@0 {
reg = <0x0>;
};
sw_phy1: ethernet-phy@1 {
reg = <0x1>;
};
sw_phy2: ethernet-phy@2 {
reg = <0x2>;
};
sw_phy3: ethernet-phy@3 {
reg = <0x3>;
};
};
};
};
&pinctrl_fec1 {
u-boot,dm-spl;
};

59
arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
View file

@ -162,6 +162,65 @@
u-boot,dm-spl;
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
lan1: port@0 {
phy-handle = <&sw_phy0>;
};
lan2: port@1 {
phy-handle = <&sw_phy1>;
};
lan3: port@2 {
phy-handle = <&sw_phy2>;
};
lan4: port@3 {
phy-handle = <&sw_phy3>;
};
lan5: port@4 {
phy-handle = <&sw_phy4>;
};
};
mdios {
#address-cells = <1>;
#size-cells = <0>;
mdio@0 {
reg = <0>;
compatible = "microchip,ksz-mdio";
#address-cells = <1>;
#size-cells = <0>;
sw_phy0: ethernet-phy@0 {
reg = <0x0>;
};
sw_phy1: ethernet-phy@1 {
reg = <0x1>;
};
sw_phy2: ethernet-phy@2 {
reg = <0x2>;
};
sw_phy3: ethernet-phy@3 {
reg = <0x3>;
};
sw_phy4: ethernet-phy@4 {
reg = <0x4>;
};
};
};
};
&usdhc2 {
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
assigned-clock-rates = <400000000>;

5
arch/arm/include/asm/arch-imx8m/imx-regs.h
View file

@ -27,6 +27,7 @@
#define IOMUXC_GPR_BASE_ADDR 0x30340000
#define OCOTP_BASE_ADDR 0x30350000
#define ANATOP_BASE_ADDR 0x30360000
#define SNVS_BASE_ADDR 0x30370000
#define CCM_BASE_ADDR 0x30380000
#define SRC_BASE_ADDR 0x30390000
#define GPC_BASE_ADDR 0x303A0000
@ -113,6 +114,10 @@
#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
#define SNVS_LPSR 0x4c
#define SNVS_LPLVDR 0x64
#define SNVS_LPPGDR_INIT 0x41736166
struct iomuxc_gpr_base_regs {
u32 gpr[47];
};

12
arch/arm/mach-imx/imx8m/soc.c
View file

@ -544,6 +544,16 @@ static int imx8m_check_clock(void *ctx, struct event *event)
}
EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock);
static void imx8m_setup_snvs(void)
{
/* Enable SNVS clock */
clock_enable(CCGR_SNVS, 1);
/* Initialize glitch detect */
writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
/* Clear interrupt status */
writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
}
int arch_cpu_init(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@ -594,6 +604,8 @@ int arch_cpu_init(void)
writel(0x200, &ocotp->ctrl_clr);
}
imx8m_setup_snvs();
return 0;
}

14
arch/riscv/Kconfig
View file

@ -269,6 +269,20 @@ config XIP
from a NOR flash memory without copying the code to ram.
Say yes here if U-Boot boots from flash directly.
config SPL_XIP
bool "Enable XIP mode for SPL"
help
If SPL starts in read-only memory (XIP for example) then we shouldn't
rely on lock variables (for example hart_lottery and available_harts_lock),
this affects only SPL, other stages should proceed as non-XIP.
config AVAILABLE_HARTS
bool "Send IPI by available harts"
default y
help
By default, IPI sending mechanism will depend on available_harts.
If disable this, it will send IPI by CPUs node numbers of device tree.
config SHOW_REGS
bool "Show registers on unhandled exception"

4
arch/riscv/cpu/cpu.c
View file

@ -19,15 +19,17 @@
* The variables here must be stored in the data section since they are used
* before the bss section is available.
*/
#ifndef CONFIG_XIP
#if !CONFIG_IS_ENABLED(XIP)
u32 hart_lottery __section(".data") = 0;
#ifdef CONFIG_AVAILABLE_HARTS
/*
* The main hart running U-Boot has acquired available_harts_lock until it has
* finished initialization of global data.
*/
u32 available_harts_lock = 1;
#endif
#endif
static inline bool supports_extension(char ext)
{

17
arch/riscv/cpu/start.S
View file

@ -122,7 +122,7 @@ call_board_init_f_0:
call_harts_early_init:
jal harts_early_init
#ifndef CONFIG_XIP
#if !CONFIG_IS_ENABLED(XIP)
/*
* Pick hart to initialize global data and run U-Boot. The other harts
* wait for initialization to complete.
@ -152,22 +152,24 @@ call_harts_early_init:
/* save the boot hart id to global_data */
SREG tp, GD_BOOT_HART(gp)
#ifndef CONFIG_XIP
#if !CONFIG_IS_ENABLED(XIP)
#ifdef CONFIG_AVAILABLE_HARTS
la t0, available_harts_lock
amoswap.w.rl zero, zero, 0(t0)
#endif
wait_for_gd_init:
la t0, available_harts_lock
li t1, 1
1: amoswap.w.aq t1, t1, 0(t0)
bnez t1, 1b
/*
* Set the global data pointer only when gd_t has been initialized.
* This was already set by arch_setup_gd on the boot hart, but all other
* harts' global data pointers gets set here.
*/
mv gp, s0
#ifdef CONFIG_AVAILABLE_HARTS
la t0, available_harts_lock
li t1, 1
1: amoswap.w.aq t1, t1, 0(t0)
bnez t1, 1b
/* register available harts in the available_harts mask */
li t1, 1
@ -177,6 +179,7 @@ wait_for_gd_init:
SREG t2, GD_AVAILABLE_HARTS(gp)
amoswap.w.rl zero, zero, 0(t0)
#endif
/*
* Continue on hart lottery winner, others branch to

4
arch/riscv/include/asm/global_data.h
View file

@ -27,9 +27,11 @@ struct arch_global_data {
#if CONFIG_IS_ENABLED(SMP)
struct ipi_data ipi[CONFIG_NR_CPUS];
#endif
#ifndef CONFIG_XIP
#if !CONFIG_IS_ENABLED(XIP)
#ifdef CONFIG_AVAILABLE_HARTS
ulong available_harts;
#endif
#endif
};
#include <asm-generic/global_data.h>

4
arch/riscv/lib/asm-offsets.c
View file

@ -16,8 +16,10 @@ int main(void)
{
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr));
#ifndef CONFIG_XIP
#if !CONFIG_IS_ENABLED(XIP)
#ifdef CONFIG_AVAILABLE_HARTS
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
#endif
#endif
return 0;

4
arch/riscv/lib/smp.c
View file

@ -45,10 +45,12 @@ static int send_ipi_many(struct ipi_data *ipi, int wait)
continue;
}
#ifndef CONFIG_XIP
#if !CONFIG_IS_ENABLED(XIP)
#ifdef CONFIG_AVAILABLE_HARTS
/* skip if hart is not available */
if (!(gd->arch.available_harts & (1 << reg)))
continue;
#endif
#endif
gd->arch.ipi[reg].addr = ipi->addr;

17
board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c
View file

@ -34,22 +34,6 @@ int board_phys_sdram_size(phys_size_t *size)
return 0;
}
/* IMX8M SNVS registers needed for the bootcount functionality */
#define SNVS_BASE_ADDR 0x30370000
#define SNVS_LPSR 0x4c
#define SNVS_LPLVDR 0x64
#define SNVS_LPPGDR_INIT 0x41736166
static void setup_snvs(void)
{
/* Enable SNVS clock */
clock_enable(CCGR_SNVS, 1);
/* Initialize glitch detect */
writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
/* Clear interrupt status */
writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
}
static void setup_mac_address(void)
{
unsigned char enetaddr[6];
@ -99,7 +83,6 @@ static void setup_boot_device(void)
int board_init(void)
{
setup_snvs();
return 0;
}

17
board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
View file

@ -37,22 +37,6 @@ int board_phys_sdram_size(phys_size_t *size)
return 0;
}
/* IMX8M SNVS registers needed for the bootcount functionality */
#define SNVS_BASE_ADDR 0x30370000
#define SNVS_LPSR 0x4c
#define SNVS_LPLVDR 0x64
#define SNVS_LPPGDR_INIT 0x41736166
static void setup_snvs(void)
{
/* Enable SNVS clock */
clock_enable(CCGR_SNVS, 1);
/* Initialize glitch detect */
writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
/* Clear interrupt status */
writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
}
static void setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
@ -145,7 +129,6 @@ int board_init(void)
{
setup_eqos();
setup_fec();
setup_snvs();
return 0;
}

17
board/menlo/mx8menlo/mx8menlo.c
View file

@ -12,24 +12,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <spl.h>
#define SNVS_BASE_ADDR 0x30370000
#define SNVS_LPSR 0x4c
#define SNVS_LPLVDR 0x64
#define SNVS_LPPGDR_INIT 0x41736166
static void setup_snvs(void)
{
/* Enable SNVS clock */
clock_enable(CCGR_SNVS, 1);
/* Initialize glitch detect */
writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
/* Clear interrupt status */
writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
}
void board_early_init(void)
{
init_uart_clk(1);
setup_snvs();
}

34
cmd/fdt.c
View file

@ -48,11 +48,27 @@ void set_working_fdt_addr(ulong addr)
/*
* Get a value from the fdt and format it to be set in the environment
*/
static int fdt_value_env_set(const void *nodep, int len, const char *var)
static int fdt_value_env_set(const void *nodep, int len,
const char *var, int index)
{
if (is_printable_string(nodep, len))
env_set(var, (void *)nodep);
else if (len == 4) {
if (is_printable_string(nodep, len)) {
const char *nodec = (const char *)nodep;
int i;
/*
* Iterate over all members in stringlist and find the one at
* offset $index. If no such index exists, indicate failure.
*/
for (i = 0; i < len; i += strlen(nodec) + 1) {
if (index-- > 0)
continue;
env_set(var, nodec + i);
return 0;
}
return 1;
} else if (len == 4) {
char buf[11];
sprintf(buf, "0x%08X", fdt32_to_cpu(*(fdt32_t *)nodep));
@ -426,10 +442,14 @@ static int do_fdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
return 0;
} else if (nodep && len > 0) {
if (subcmd[0] == 'v') {
int index = 0;
int ret;
if (argc == 7)
index = simple_strtoul(argv[6], NULL, 10);
ret = fdt_value_env_set(nodep, len,
var);
var, index);
if (ret != 0)
return ret;
} else if (subcmd[0] == 'a') {
@ -1085,7 +1105,9 @@ static char fdt_help_text[] =
"fdt resize [<extrasize>] - Resize fdt to size + padding to 4k addr + some optional <extrasize> if needed\n"
"fdt print <path> [<prop>] - Recursive print starting at <path>\n"
"fdt list <path> [<prop>] - Print one level starting at <path>\n"
"fdt get value <var> <path> <prop> - Get <property> and store in <var>\n"
"fdt get value <var> <path> <prop> [<index>] - Get <property> and store in <var>\n"
" In case of stringlist property, use optional <index>\n"
" to select string within the stringlist. Default is 0.\n"
"fdt get name <var> <path> <index> - Get name of node <index> and store in <var>\n"
"fdt get addr <var> <path> <prop> - Get start address of <property> and store in <var>\n"
"fdt get size <var> <path> [<prop>] - Get size of [<property>] or num nodes and store in <var>\n"

1
configs/ae350_rv32_spl_defconfig
View file

@ -48,3 +48,4 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_ATCSPI200_SPI=y
# CONFIG_BINMAN_FDT is not set
# CONFIG_AVAILABLE_HARTS is not set

2
configs/ae350_rv32_spl_xip_defconfig
View file

@ -11,7 +11,7 @@ CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_AX25_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_XIP=y
CONFIG_SPL_XIP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00

1
configs/ae350_rv64_spl_defconfig
View file

@ -49,3 +49,4 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_ATCSPI200_SPI=y
# CONFIG_BINMAN_FDT is not set
# CONFIG_AVAILABLE_HARTS is not set

2
configs/ae350_rv64_spl_xip_defconfig
View file

@ -12,7 +12,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_XIP=y
CONFIG_SPL_XIP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70

1
configs/kontron-sl-mx8mm_defconfig
View file

@ -39,7 +39,6 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
# CONFIG_SPL_FIT_IMAGE_TINY is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER=y

2
doc/imx/habv4/csf_examples/mx8m/csf.sh
View file

@ -40,7 +40,7 @@ dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc
# fitImage tree
fit_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SYS_TEXT_BASE=/ s@.*=@@p" .config) - $(sed -n "/CONFIG_FIT_EXTERNAL_OFFSET=/ s@.*=@@p" .config) - 0x200 - 0x40)) )
fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset))
fit_block_size=$(printf "0x%x" $(( ( $(fdtdump u-boot.itb 2>/dev/null | sed -n "/^...totalsize:/ s@.*\(0x[0-9a-f]\+\).*@\1@p") + 0x1000 - 0x1 ) & ~(0x1000 - 0x1) + 0x20 )) )
fit_block_size=$(printf "0x%x" $(( ( ($(fdtdump u-boot.itb 2>/dev/null | sed -n "/^...totalsize:/ s@.*\(0x[0-9a-f]\+\).*@\1@p") + 0x1000 - 0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) )
sed -i "/Blocks = / s@.*@ Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\", \\\\@" csf_fit.tmp
# U-Boot

2
drivers/serial/usbtty.h
View file

@ -13,8 +13,6 @@
#include <usbdevice.h>
#if defined(CONFIG_PPC)
#include <usb/mpc8xx_udc.h>
#elif defined(CONFIG_DW_UDC)
#include <usb/designware_udc.h>
#elif defined(CONFIG_CI_UDC)
#include <usb/ci_udc.h>
#endif

2
drivers/usb/Kconfig
View file

@ -48,7 +48,7 @@ config DM_USB
automatically probed when found on the bus.
config SPL_DM_USB
bool "Enable driver model for USB host most in SPL"
bool "Enable driver model for USB host mode in SPL"
depends on SPL_DM && DM_USB
default n if ARCH_MVEBU
default y

1
drivers/usb/gadget/Makefile
View file

@ -42,6 +42,5 @@ else
ifdef CONFIG_USB_DEVICE
obj-y += core.o
obj-y += ep0.o
obj-$(CONFIG_DW_UDC) += designware_udc.o
endif
endif

1021
drivers/usb/gadget/designware_udc.c
View file

File diff suppressed because it is too large Load diff

183
include/usb/designware_udc.h
View file

@ -1,183 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009
* Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
*/
#ifndef __DW_UDC_H
#define __DW_UDC_H
/*
* Defines for USBD
*
* The udc_ahb controller has three AHB slaves:
*
* 1. THe UDC registers
* 2. The plug detect
* 3. The RX/TX FIFO
*/
#define MAX_ENDPOINTS 16
struct udc_endp_regs {
u32 endp_cntl;
u32 endp_status;
u32 endp_bsorfn;
u32 endp_maxpacksize;
u32 reserved_1;
u32 endp_desc_point;
u32 reserved_2;
u32 write_done;
};
/* Endpoint Control Register definitions */
#define ENDP_CNTL_STALL 0x00000001
#define ENDP_CNTL_FLUSH 0x00000002
#define ENDP_CNTL_SNOOP 0x00000004
#define ENDP_CNTL_POLL 0x00000008
#define ENDP_CNTL_CONTROL 0x00000000
#define ENDP_CNTL_ISO 0x00000010
#define ENDP_CNTL_BULK 0x00000020
#define ENDP_CNTL_INT 0x00000030
#define ENDP_CNTL_NAK 0x00000040
#define ENDP_CNTL_SNAK 0x00000080
#define ENDP_CNTL_CNAK 0x00000100
#define ENDP_CNTL_RRDY 0x00000200
/* Endpoint Satus Register definitions */
#define ENDP_STATUS_PIDMSK 0x0000000f
#define ENDP_STATUS_OUTMSK 0x00000030
#define ENDP_STATUS_OUT_NONE 0x00000000
#define ENDP_STATUS_OUT_DATA 0x00000010
#define ENDP_STATUS_OUT_SETUP 0x00000020
#define ENDP_STATUS_IN 0x00000040
#define ENDP_STATUS_BUFFNAV 0x00000080
#define ENDP_STATUS_FATERR 0x00000100
#define ENDP_STATUS_HOSTBUSERR 0x00000200
#define ENDP_STATUS_TDC 0x00000400
#define ENDP_STATUS_RXPKTMSK 0x003ff800
struct udc_regs {
struct udc_endp_regs in_regs[MAX_ENDPOINTS];
struct udc_endp_regs out_regs[MAX_ENDPOINTS];
u32 dev_conf;
u32 dev_cntl;
u32 dev_stat;
u32 dev_int;
u32 dev_int_mask;
u32 endp_int;
u32 endp_int_mask;
u32 reserved_3[0x39];
u32 reserved_4; /* offset 0x500 */
u32 udc_endp_reg[MAX_ENDPOINTS];
};
/* Device Configuration Register definitions */
#define DEV_CONF_HS_SPEED 0x00000000
#define DEV_CONF_LS_SPEED 0x00000002
#define DEV_CONF_FS_SPEED 0x00000003
#define DEV_CONF_REMWAKEUP 0x00000004
#define DEV_CONF_SELFPOW 0x00000008
#define DEV_CONF_SYNCFRAME 0x00000010
#define DEV_CONF_PHYINT_8 0x00000020
#define DEV_CONF_PHYINT_16 0x00000000
#define DEV_CONF_UTMI_BIDIR 0x00000040
#define DEV_CONF_STATUS_STALL 0x00000080
/* Device Control Register definitions */
#define DEV_CNTL_RESUME 0x00000001
#define DEV_CNTL_TFFLUSH 0x00000002
#define DEV_CNTL_RXDMAEN 0x00000004
#define DEV_CNTL_TXDMAEN 0x00000008
#define DEV_CNTL_DESCRUPD 0x00000010
#define DEV_CNTL_BIGEND 0x00000020
#define DEV_CNTL_BUFFILL 0x00000040
#define DEV_CNTL_TSHLDEN 0x00000080
#define DEV_CNTL_BURSTEN 0x00000100
#define DEV_CNTL_DMAMODE 0x00000200
#define DEV_CNTL_SOFTDISCONNECT 0x00000400
#define DEV_CNTL_SCALEDOWN 0x00000800
#define DEV_CNTL_BURSTLENU 0x00010000
#define DEV_CNTL_BURSTLENMSK 0x00ff0000
#define DEV_CNTL_TSHLDLENU 0x01000000
#define DEV_CNTL_TSHLDLENMSK 0xff000000
/* Device Status Register definitions */
#define DEV_STAT_CFG 0x0000000f
#define DEV_STAT_INTF 0x000000f0
#define DEV_STAT_ALT 0x00000f00
#define DEV_STAT_SUSP 0x00001000
#define DEV_STAT_ENUM 0x00006000
#define DEV_STAT_ENUM_SPEED_HS 0x00000000
#define DEV_STAT_ENUM_SPEED_FS 0x00002000
#define DEV_STAT_ENUM_SPEED_LS 0x00004000
#define DEV_STAT_RXFIFO_EMPTY 0x00008000
#define DEV_STAT_PHY_ERR 0x00010000
#define DEV_STAT_TS 0xf0000000
/* Device Interrupt Register definitions */
#define DEV_INT_MSK 0x0000007f
#define DEV_INT_SETCFG 0x00000001
#define DEV_INT_SETINTF 0x00000002
#define DEV_INT_INACTIVE 0x00000004
#define DEV_INT_USBRESET 0x00000008
#define DEV_INT_SUSPUSB 0x00000010
#define DEV_INT_SOF 0x00000020
#define DEV_INT_ENUM 0x00000040
/* Endpoint Interrupt Register definitions */
#define ENDP0_INT_CTRLIN 0x00000001
#define ENDP1_INT_BULKIN 0x00000002
#define ENDP_INT_NONISOIN_MSK 0x0000AAAA
#define ENDP2_INT_BULKIN 0x00000004
#define ENDP0_INT_CTRLOUT 0x00010000
#define ENDP1_INT_BULKOUT 0x00020000
#define ENDP2_INT_BULKOUT 0x00040000
#define ENDP_INT_NONISOOUT_MSK 0x55540000
/* Endpoint Register definitions */
#define ENDP_EPDIR_OUT 0x00000000
#define ENDP_EPDIR_IN 0x00000010
#define ENDP_EPTYPE_CNTL 0x0
#define ENDP_EPTYPE_ISO 0x1
#define ENDP_EPTYPE_BULK 0x2
#define ENDP_EPTYPE_INT 0x3
/*
* Defines for Plug Detect
*/
struct plug_regs {
u32 plug_state;
u32 plug_pending;
};
/* Plug State Register definitions */
#define PLUG_STATUS_EN 0x1
#define PLUG_STATUS_ATTACHED 0x2
#define PLUG_STATUS_PHY_RESET 0x4
#define PLUG_STATUS_PHY_MODE 0x8
/*
* Defines for UDC FIFO (Slave Mode)
*/
struct udcfifo_regs {
u32 *fifo_p;
};
/*
* UDC endpoint definitions
*/
#define UDC_EP0 0
#define UDC_EP1 1
#define UDC_EP2 2
#define UDC_EP3 3
#endif /* __DW_UDC_H */

10
tools/binman/bintool.py
View file

@ -319,7 +319,7 @@ class Bintool:
return result.stdout
@classmethod
def build_from_git(cls, git_repo, make_target, bintool_path):
def build_from_git(cls, git_repo, make_target, bintool_path, flags=None):
"""Build a bintool from a git repo
This clones the repo in a temporary directory, builds it with 'make',
@ -330,6 +330,7 @@ class Bintool:
make_target (str): Target to pass to 'make' to build the tool
bintool_path (str): Relative path of the tool in the repo, after
build is complete
flags (list of str): Flags or variables to pass to make, or None
Returns:
tuple:
@ -341,8 +342,11 @@ class Bintool:
print(f"- clone git repo '{git_repo}' to '{tmpdir}'")
tools.run('git', 'clone', '--depth', '1', git_repo, tmpdir)
print(f"- build target '{make_target}'")
tools.run('make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}',
make_target)
cmd = ['make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}',
make_target]
if flags:
cmd += flags
tools.run(*cmd)
fname = os.path.join(tmpdir, bintool_path)
if not os.path.exists(fname):
print(f"- File '{fname}' was not produced")

17
tools/binman/btool/futility.py
View file

@ -160,8 +160,17 @@ class Bintoolfutility(bintool.Bintool):
Raises:
Valuerror: Fetching could not be completed
"""
if method != bintool.FETCH_BIN:
if method != bintool.FETCH_BUILD:
return None
fname, tmpdir = self.fetch_from_drive(
'1hdsInzsE4aJbmBeJ663kYgjOQyW1I-E0')
return fname, tmpdir
# The Chromium OS repo is here:
# https://chromium.googlesource.com/chromiumos/platform/vboot_reference/
#
# Unfortunately this requires logging in and obtaining a line for the
# .gitcookies file. So use a mirror instead.
result = self.build_from_git(
'https://github.com/sjg20/vboot_reference.git',
'all',
'build/futility/futility',
flags=['USE_FLASHROM=0'])
return result