arm: kirkwood: Dreamplug : Use Marvell uclass mvgbe and PHY driver for Ethernet
The Globalscale Technologies Dreamplug board has the network chip Marvell 88E1116R. Use uclass mvgbe and the compatible driver M88E1310 driver to bring up Ethernet. - Currently, CONFIG_RESET_PHY_R symbol is used in arch/arm/mach-kirkwood/include/mach/config.h for all Kirkwood boards with mv8831116 PHY, with each board defines the function reset_phy(). Undefine it for this board. - Add board_eth_init() to use uclass mvgbe to bring up both network port 0 and 1. And remove ad-hoc code. - Enable CONFIG_PHY_MARVELL to properly configure the network. - Add myself as maintainer (this board seems to be orphaned, could not contact Jason Cooper using current email). - Miscellaneous changes: Move constants to .c file and remove header file board/Marvell/dreamplug/dreamplug.h, cleanup comments. Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Pali Rohár <pali@kernel.org>
This commit is contained in:
Tony Dinh
Stefan Roese
parent
8597032512
commit
fb9ed23c22
5 changed files with 21 additions and 120 deletions
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@ -1,4 +1,5 @@
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DREAMPLUG BOARD
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M: Tony Dinh <mibodhi@gmail.com>
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M: Jason Cooper <u-boot@lakedaemon.net>
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S: Maintained
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F: board/Marvell/dreamplug/
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@ -1,8 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 Tony Dinh <mibodhi@gmail.com>
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* (C) Copyright 2011
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* Jason Cooper <u-boot@lakedaemon.net>
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* Copyright (C) 2021-2022 Tony Dinh <mibodhi@gmail.com>
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* Copyright (C) 2011 Jason Cooper <u-boot@lakedaemon.net>
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*
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* Based on work by:
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* Marvell Semiconductor <www.marvell.com>
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@ -11,16 +10,19 @@
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#include <common.h>
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#include <init.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <asm/global_data.h>
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#include "dreamplug.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define DREAMPLUG_OE_LOW (~(0))
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#define DREAMPLUG_OE_HIGH (~(0))
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#define DREAMPLUG_OE_VAL_LOW 0
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#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
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int board_early_init_f(void)
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{
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/*
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@ -90,83 +92,15 @@ int board_early_init_f(void)
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return 0;
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}
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int board_eth_init(struct bd_info *bis)
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{
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return cpu_eth_init(bis);
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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/* address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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static int fdt_get_phy_addr(const char *path)
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{
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const void *fdt = gd->fdt_blob;
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const u32 *reg;
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const u32 *val;
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int node, phandle, addr;
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/* Find the node by its full path */
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node = fdt_path_offset(fdt, path);
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if (node >= 0) {
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/* Look up phy-handle */
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val = fdt_getprop(fdt, node, "phy-handle", NULL);
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if (val) {
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phandle = fdt32_to_cpu(*val);
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if (!phandle)
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return -1;
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/* Follow it to its node */
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node = fdt_node_offset_by_phandle(fdt, phandle);
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if (node) {
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/* Look up reg */
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reg = fdt_getprop(fdt, node, "reg", NULL);
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if (reg) {
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addr = fdt32_to_cpu(*reg);
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return addr;
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}
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}
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}
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}
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return -1;
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}
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#ifdef CONFIG_RESET_PHY_R
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void mv_phy_88e1116_init(const char *name, const char *path)
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{
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u16 reg;
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int phyaddr;
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if (miiphy_set_current_dev(name))
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return;
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phyaddr = fdt_get_phy_addr(path);
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if (phyaddr < 0)
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return;
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL2_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL2_REG, reg);
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miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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miiphy_reset(name, phyaddr);
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printf("88E1116 Initialized on %s\n", name);
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}
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void reset_phy(void)
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{
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char *eth0_name = "ethernet-controller@72000";
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char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
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char *eth1_name = "ethernet-controller@76000";
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char *eth1_path = "/ocp@f1000000/ethernet-controller@76000/ethernet1-port@0";
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/* configure and initialize both PHY's */
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mv_phy_88e1116_init(eth0_name, eth0_path);
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mv_phy_88e1116_init(eth1_name, eth1_path);
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}
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#endif /* CONFIG_RESET_PHY_R */
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@ -1,25 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2011
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* Jason Cooper <u-boot@lakedaemon.net>
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*
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* Based on work by:
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Siddarth Gore <gores@marvell.com>
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*/
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#ifndef __DREAMPLUG_H
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#define __DREAMPLUG_H
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#define DREAMPLUG_OE_LOW (~(0))
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#define DREAMPLUG_OE_HIGH (~(0))
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#define DREAMPLUG_OE_VAL_LOW 0
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#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
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/* PHY related */
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#define MV88E1116_MAC_CTRL2_REG 21
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#define MV88E1116_PGADR_REG 22
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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#endif /* __DREAMPLUG_H */
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@ -50,6 +50,7 @@ CONFIG_SYS_ATA_ALT_OFFSET=0x100
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_PHY_MARVELL=y
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CONFIG_DM_ETH=y
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CONFIG_MVGBE=y
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CONFIG_MII=y
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2011
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* Jason Cooper <u-boot@lakedaemon.net>
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* (C) Copyright 2022 Tony Dinh <mibodhi@gmail.com>
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* (C) Copyright 2011 Jason Cooper <u-boot@lakedaemon.net>
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*
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* Based on work by:
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* Marvell Semiconductor <www.marvell.com>
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@ -13,15 +13,6 @@
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#include "mv-common.h"
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/*
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* Environment variables configurations
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*/
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/*
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* max 4k env size is enough, but in case of nand
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* it has to be rounded to sector size
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*/
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/*
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* Default environment variables
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*/
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@ -36,16 +27,15 @@
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/*
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* Ethernet Driver configuration
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*/
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#ifdef CONFIG_CMD_NET
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#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
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#define CONFIG_PHY_BASE_ADR 0
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#endif /* CONFIG_CMD_NET */
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#ifdef CONFIG_RESET_PHY_R
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#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */
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#endif
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/*
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* SATA Driver configuration
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*/
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#ifdef CONFIG_SATA
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#define CONFIG_LBA48
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#endif /* CONFIG_SATA */
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#endif /* _CONFIG_DREAMPLUG_H */
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