- fix Ethernet on Odroid-C2 by re-adding old bindings style PHY reset
- add G12A PCIe clock gates - add G12A PCIe PHY OPs - enable PCIe for Khadas VIM3/VIM3L boards DT - enable PCIe and NVME for Khadas VIM3/VIM3L boards config - update Amlogic board documentation for PCIe support -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmB9m44ACgkQd9zb2sjI SdGEUxAAhFpEB0NHO/aqV+Ydd81Sb7iJUSl4w6LRVDnjif4jwEU6AP+/euYpung1 0cZ364TT8Tj+3QyscbSfHwm6zOtkKzB2/5MzaWEQLn7dUS08TE0kBHNwhk6TPYoW NiauLp8uILgvs6JczM7nSgWor2ICnUivxPjcWJTJ7twIADOWxQY8n0acrmBdxxny BGcKmNewbJ2jYKw9mvJJ4E+br20pICc7WLRqnnuMmYfb2Fov9JVO0HJ69G5uDyUv pPU6Zm9ZCm3+pwkwKuF0kc9rlrYEinJSf29FcNeXn/35SwdqyXqkCC7lIeFWKuqd BlIZwpU0XA5b6WejCO6h0RL1F2xduOgRbOSLOn6IwPb67vzqZrjclau30VrLItPx G2UWzYK7QIVtAeXNetsU3aTRKdb3sICdtMZxbDMk6b8gmhBUIeZ7NHqC2GS9/w8W A3ItvSkYQ1f0WXNy8/p/M/cZywmI7gRtCx6TtdQFYIfBdVylV93UhZozyjmd60je 6W/1p1odzc958MXJzNQE4ASsgEM2C4V5TdYj4iIs3kxb5eHJOgsgFZymHC/AaenI LMoWVOz/qVuUFKc79ylJQQkV6InPW2+n4PuIUiCpHgwcYYjjweF42+awsHeZzu54 IyCRU1QtkMhNrXwRIjPlkHPgEAQHK2vdkzs4rPk+Y1cleq8OTOQ= =7B7I -----END PGP SIGNATURE----- Merge tag 'u-boot-amlogic-20210419' of https://source.denx.de/u-boot/custodians/u-boot-amlogic - fix Ethernet on Odroid-C2 by re-adding old bindings style PHY reset - add G12A PCIe clock gates - add G12A PCIe PHY OPs - enable PCIe for Khadas VIM3/VIM3L boards DT - enable PCIe and NVME for Khadas VIM3/VIM3L boards config - update Amlogic board documentation for PCIe support
This commit is contained in:
Tom Rini
commit
eed05148c2
8 changed files with 108 additions and 4 deletions
|
|
@ -29,6 +29,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
ðmac {
|
||||
snps,reset-gpio = <&gpio GPIOZ_14 0>;
|
||||
snps,reset-delays-us = <0 10000 1000000>;
|
||||
snps,reset-active-low;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,6 +10,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sd_emmc_c {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_4b_pins>, <&emmc_ds_pins>;
|
||||
|
|
|
|||
|
|
@ -88,3 +88,8 @@ CONFIG_BMP_16BPP=y
|
|||
CONFIG_BMP_24BPP=y
|
||||
CONFIG_BMP_32BPP=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_PCIE_DW_MESON=y
|
||||
CONFIG_NVME=y
|
||||
|
|
|
|||
|
|
@ -88,3 +88,8 @@ CONFIG_BMP_16BPP=y
|
|||
CONFIG_BMP_24BPP=y
|
||||
CONFIG_BMP_32BPP=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_PCIE_DW_MESON=y
|
||||
CONFIG_NVME=y
|
||||
|
|
|
|||
|
|
@ -70,6 +70,8 @@ This matrix concerns the actual source code version.
|
|||
+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
|
||||
| SoC (version) information | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** | **Yes** |
|
||||
+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
|
||||
| PCIe (+NVMe) | *N/A* | *N/A* | *N/A* | **Yes** | **Yes** | **Yes** | **Yes** |
|
||||
+-------------------------------+-----------+-----------------+--------------+------------+------------+-------------+--------------+
|
||||
|
||||
Board Documentation
|
||||
-------------------
|
||||
|
|
|
|||
|
|
@ -120,7 +120,9 @@ static struct meson_gate gates[NUM_CLKS] = {
|
|||
MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
|
||||
MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
|
||||
MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
|
||||
MESON_GATE(CLKID_PCIE_COMB, HHI_GCLK_MPEG1, 24),
|
||||
MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 25),
|
||||
MESON_GATE(CLKID_PCIE_PHY, HHI_GCLK_MPEG1, 27),
|
||||
MESON_GATE(CLKID_HTX_PCLK, HHI_GCLK_MPEG2, 4),
|
||||
MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
|
||||
MESON_GATE(CLKID_VPU_INTR, HHI_GCLK_MPEG2, 25),
|
||||
|
|
|
|||
|
|
@ -23,6 +23,9 @@
|
|||
#include <linux/compat.h>
|
||||
#include <linux/bitfield.h>
|
||||
|
||||
#define PHY_TYPE_PCIE 2
|
||||
#define PHY_TYPE_USB3 4
|
||||
|
||||
#define PHY_R0 0x00
|
||||
#define PHY_R0_PCIE_POWER_STATE GENMASK(4, 0)
|
||||
#define PHY_R0_PCIE_USB3_SWITCH GENMASK(6, 5)
|
||||
|
|
@ -55,6 +58,8 @@
|
|||
#define PHY_R5_PHY_CR_ACK BIT(16)
|
||||
#define PHY_R5_PHY_BS_OUT BIT(17)
|
||||
|
||||
#define PCIE_RESET_DELAY 500
|
||||
|
||||
struct phy_g12a_usb3_pcie_priv {
|
||||
struct regmap *regmap;
|
||||
#if CONFIG_IS_ENABLED(CLK)
|
||||
|
|
@ -202,8 +207,6 @@ static int phy_meson_g12a_usb3_init(struct phy *phy)
|
|||
unsigned int data;
|
||||
int ret;
|
||||
|
||||
/* TOFIX Handle PCIE mode */
|
||||
|
||||
ret = reset_assert_bulk(&priv->resets);
|
||||
udelay(1);
|
||||
ret |= reset_deassert_bulk(&priv->resets);
|
||||
|
|
@ -296,9 +299,79 @@ static int phy_meson_g12a_usb3_exit(struct phy *phy)
|
|||
return reset_assert_bulk(&priv->resets);
|
||||
}
|
||||
|
||||
static int phy_meson_g12a_usb3_pcie_init(struct phy *phy)
|
||||
{
|
||||
if (phy->id == PHY_TYPE_USB3)
|
||||
return phy_meson_g12a_usb3_init(phy);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phy_meson_g12a_usb3_pcie_exit(struct phy *phy)
|
||||
{
|
||||
if (phy->id == PHY_TYPE_USB3)
|
||||
return phy_meson_g12a_usb3_exit(phy);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phy_meson_g12a_usb3_pcie_power_on(struct phy *phy)
|
||||
{
|
||||
struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
|
||||
|
||||
if (phy->id == PHY_TYPE_USB3)
|
||||
return 0;
|
||||
|
||||
regmap_update_bits(priv->regmap, PHY_R0,
|
||||
PHY_R0_PCIE_POWER_STATE,
|
||||
FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phy_meson_g12a_usb3_pcie_power_off(struct phy *phy)
|
||||
{
|
||||
struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
|
||||
|
||||
if (phy->id == PHY_TYPE_USB3)
|
||||
return 0;
|
||||
|
||||
regmap_update_bits(priv->regmap, PHY_R0,
|
||||
PHY_R0_PCIE_POWER_STATE,
|
||||
FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1d));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phy_meson_g12a_usb3_pcie_reset(struct phy *phy)
|
||||
{
|
||||
struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
|
||||
int ret;
|
||||
|
||||
if (phy->id == PHY_TYPE_USB3)
|
||||
return 0;
|
||||
|
||||
ret = reset_assert_bulk(&priv->resets);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
udelay(PCIE_RESET_DELAY);
|
||||
|
||||
ret = reset_deassert_bulk(&priv->resets);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
udelay(PCIE_RESET_DELAY);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct phy_ops meson_g12a_usb3_pcie_phy_ops = {
|
||||
.init = phy_meson_g12a_usb3_init,
|
||||
.exit = phy_meson_g12a_usb3_exit,
|
||||
.init = phy_meson_g12a_usb3_pcie_init,
|
||||
.exit = phy_meson_g12a_usb3_pcie_exit,
|
||||
.power_on = phy_meson_g12a_usb3_pcie_power_on,
|
||||
.power_off = phy_meson_g12a_usb3_pcie_power_off,
|
||||
.reset = phy_meson_g12a_usb3_pcie_reset,
|
||||
};
|
||||
|
||||
int meson_g12a_usb3_pcie_phy_probe(struct udevice *dev)
|
||||
|
|
|
|||
|
|
@ -58,6 +58,12 @@
|
|||
#define BOOT_TARGET_DEVICES_USB(func)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_NVME
|
||||
#define BOOT_TARGET_NVME(func) func(NVME, nvme, 0)
|
||||
#else
|
||||
#define BOOT_TARGET_NVME(func)
|
||||
#endif
|
||||
|
||||
#ifndef BOOT_TARGET_DEVICES
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(ROMUSB, romusb, na) \
|
||||
|
|
@ -65,6 +71,7 @@
|
|||
func(MMC, mmc, 1) \
|
||||
func(MMC, mmc, 2) \
|
||||
BOOT_TARGET_DEVICES_USB(func) \
|
||||
BOOT_TARGET_NVME(func) \
|
||||
func(PXE, pxe, na) \
|
||||
func(DHCP, dhcp, na)
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue