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Merge branch 'master' into hpc2

Browse source 
Conflicts:

	drivers/cfi_flash.c

The patch by Heiko Schocher <hs@pollux.denx.de> on Jan, 19, 2007
fixes cfi_driver bug for mpc7448hpc2 board. The default cfi_driver can support
mpc7448hpc2 board.
This commit is contained in:
roy zang 2007-01-22 13:15:35 +08:00 committed by Zang Tiefei
commit ee460917af
77 changed files with 7686 additions and 291 deletions
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395
CHANGELOG
View file

@ -1,3 +1,394 @@
commit f539b7ba7d7ef6dd187c8209609001cb1cd95e39
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Fri Jan 19 19:57:10 2007 +0100
[PATCH] SC3 board: added CFG_CMD_AUTOSCRIPT.
Signed-off-by: Heiko Schocher <hs@denx.de>
commit d0b6e14087ddd8789f224a48e1d33f2a5df4d167
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Fri Jan 19 18:05:26 2007 +0100
[PATCH] CFI: define CFG_WRITE_SWAPPED_DATA for the CFI-Flash driver
if you must swap the bytes between reading/writing.
(Needed for the SC3 board)
Signed-off-by: Heiko Schocher <hs@denx.de>
commit 9d8d5a5bfb64768f29a0cb47fc37cd6f4c40e276
Author: Stefan Roese <sr@denx.de>
Date: Thu Jan 18 16:05:47 2007 +0100
[PATCH] Add support for Prodrive SCPU (PDNB3 variant) board
Signed-off-by: Stefan Roese <sr@denx.de>
commit 0057d758e3e874cbe7f24745d0cce8c1cb6c207e
Author: Stefan Roese <sr@denx.de>
Date: Thu Jan 18 11:54:52 2007 +0100
[PATCH] Update Prodrive P3Mx support
Signed-off-by: Stefan Roese <sr@denx.de>
commit 34167a36c29ee946b727465db5c014746a08e978
Author: Stefan Roese <sr@denx.de>
Date: Thu Jan 18 11:48:10 2007 +0100
[PATCH] Add missing Taishan config file
Signed-off-by: Stefan Roese <sr@denx.de>
commit cb4820725e9fc409c5cbc8e83054a6ed522d2111
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Thu Jan 18 11:28:51 2007 +0100
[PATCH] Fix: Compilerwarnings for SC3 board.
The EBC Configuration Register is now by CFG_EBC_CFG definable
Added JFFS2 support for the SC3 board.
Signed-off-by: Heiko Schocher <hs@denx.de>
commit 5fb692cae57d1710c8f52a427cf7f39a37383fcd
Author: Stefan Roese <sr@denx.de>
Date: Thu Jan 18 10:25:34 2007 +0100
[PATCH] Add support for AMCC Taishan PPC440GX eval board
Signed-off-by: Stefan Roese <sr@denx.de>
commit 6d3e0107235aa0e6a6dcb77f9884497280bf85ad
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Tue Jan 16 18:30:50 2007 +0100
Raname solidcard3 into sc3; add redundant env for sc3
commit 1bbbbdd20fcec9933697000dcf55ff7972622596
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Tue Jan 16 12:46:35 2007 +0100
Update default environment for Solidcard3
commit 5a5c56986a9ccf71642c8b6374eb18487b15fecd
Author: Stefan Roese <sr@denx.de>
Date: Mon Jan 15 09:46:29 2007 +0100
[PATCH] Fix 440SPe rev B detection from previous patch
Signed-off-by: Stefan Roese <sr@denx.de>
commit a443d31410c571ee8f970da819a44d698fdd6b1f
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Sun Jan 14 13:35:31 2007 +0100
[FIX] correct I2C Writes for the LM81 Sensor.
Signed-off-by: Heiko Schocher <hs@denx.de>
commit 0bba5452835f19a61204edcda3a58112fd8e2208
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Sat Jan 13 11:17:10 2007 +0100
Undo commit 3033ebb2: reset command does not take any arguments
Haiying Wang's modification to the reset command was broken, undo it.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 95981778cff0038fd9941044d6a3eda810e33258
Author: Stefan Roese <sr@denx.de>
Date: Sat Jan 13 08:01:03 2007 +0100
[PATCH] Update 440SP(e) cpu revisions
Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 77ddc5b9afb325262fd88752ba430a1dded1f0c7
Author: Stefan Roese <sr@denx.de>
Date: Sat Jan 13 07:59:56 2007 +0100
[PATCH] Update Yellowstone (440GR) to display board rev and PCI bus speed
Now the board revision and the current PCI bus speed are printed after
the board message.
Also the EBC initialising is now done via defines in the board config
file.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 36adff362c2c0141ff8a810d42a7e478f779130f
Author: Stefan Roese <sr@denx.de>
Date: Sat Jan 13 07:59:19 2007 +0100
[PATCH] Update Yosemite (440EP) to display board rev and PCI bus speed
Now the board revision and the current PCI bus speed are printed after
the board message.
Also the EBC initialising is now done via defines in the board config
file.
Signed-off-by: Stefan Roese <sr@denx.de>
commit e0b9ea8c8a294de6a5350ae638879d24b5b709d6
Author: Stefan Roese <sr@denx.de>
Date: Sat Jan 13 07:57:51 2007 +0100
[PATCH] Update Sequoia (440EPx) to display board rev and PCI bus speed
Now the board revision and the current PCI bus speed are printed after
the board message.
Signed-off-by: Stefan Roese <sr@denx.de>
commit ca43ba18e910206ef8063e4b22d282630bff3fd2
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Thu Jan 11 15:44:44 2007 +0100
Added support for the SOLIDCARD III board from Eurodesign
Signed-off-by: Heiko Schocher <hs@denx.de>
commit 6abaee42621c07e81a2cd189ad4368b5e8c50280
Author: Reinhard Thies <Reinhard.Thies@web.de>
Date: Wed Jan 10 14:41:14 2007 +0100
Adjusted default environment for cam5200 board.
commit bab5a90d4ccc1a46a8127b867fa59028cc623ad9
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Wed Jan 10 15:35:52 2007 +0100
Update CHANGELOG
commit 787fa15860a57833e50bd30555079a9cd4e519b8
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Wed Jan 10 01:28:39 2007 +0100
Fix auto_update for MCC200 board.
The invocation of do_auto_update() is moved to the end of the
misc_init_r() function, after the flash mappings have been
initialized. Please find attached a patch that implements that
change.
Also correct the decoding of the keypad status. With this update, the
key that will trigger the update is Column 2, Row 2.
commit d9384de2f571046e71081bae22b49e3d5ca2e3d5
Author: Marian Balakowicz <m8@semihalf.com>
Date: Wed Jan 10 00:26:15 2007 +0100
CAM5200 flash driver modifications:
- use CFI driver (replaces custom flash driver) for main 'cam5200' target
- add second build target 'cam5200_niosflash' which still uses custom driver
commit 67fea022fa957f59653b5238c7496f80a6b70432
Author: Markus Klotzbuecher <mk@denx.de>
Date: Tue Jan 9 16:02:48 2007 +0100
SPC1920: cleanup memory contoller setup
commit 8fc2102faa23593c80381437c09f7745a14deb40
Author: Markus Klotzbuecher <mk@denx.de>
Date: Tue Jan 9 14:57:14 2007 +0100
Fix the cpu speed setup to work with all boards.
commit 9295acb77481cf099ef9b40e1fa2d145b3c7490c
Author: Markus Klotzbuecher <mk@denx.de>
Date: Tue Jan 9 14:57:13 2007 +0100
SPC1920: add support for the FM18L08 Ramtron FRAM
commit 38ccd2fdf3364a53fe80e9b365303ecdafc9e223
Author: Markus Klotzbuecher <mk@denx.de>
Date: Tue Jan 9 14:57:13 2007 +0100
SPC1920: update the HPI register addresses to work with the second
generation of hardware
commit 5921e5313fc3eadd42770c2b99badd7fae5ecf1e
Author: Markus Klotzbuecher <mk@creamnet.de>
Date: Tue Jan 9 14:57:13 2007 +0100
Miscellanious spc1920 related cleanups
commit e4c2d37adc8bb1bf69dcf600cbc6c75f916a6120
Author: Markus Klotzbuecher <mk@denx.de>
Date: Tue Jan 9 14:57:12 2007 +0100
SPC1920 GO/NOGO led should be set to color red in U-Boot
commit 0be62728aac459ba268d6d752ed49ec0e2bc7348
Author: Markus Klotzbuecher <mk@creamnet.de>
Date: Tue Jan 9 14:57:12 2007 +0100
Add support for the DS3231 RTC
commit 8139567b60d678584b05f0718a681f2047c5e14f
Author: Markus Klotzbuecher <mk@creamnet.de>
Date: Tue Jan 9 14:57:11 2007 +0100
SMC1 uses external CLK4 instead of BRG on spc1920
commit d8d9de1a02fbd880b613d607143d1f57342affc7
Author: Markus Klotzbuecher <mk@creamnet.de>
Date: Tue Jan 9 14:57:10 2007 +0100
Update the SPC1920 CMB PLD driver
commit 3f34f869162750e5e999fd140f884f5de952bcfe
Author: Markus Klotzbuecher <mk@creamnet.de>
Date: Tue Jan 9 14:57:10 2007 +0100
Add / enable I2C support on the spc1920 board
commit d28707dbce1e9ac2017ad051da4133bf22b4204f
Author: Markus Klotzbuecher <mk@creamnet.de>
Date: Tue Jan 9 14:57:10 2007 +0100
Add support for the tms320671x host port interface (HPI)
commit f4eb54529bb3664c3a562e488b460fe075f79d67
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Sun Jan 7 00:13:11 2007 +0100
Prepare for release 1.2.0
commit f07ae7a9daef27a3d0213a4f3fe39d5342173c02
Author: Stefan Roese <sr@denx.de>
Date: Sat Jan 6 15:58:09 2007 +0100
[PATCH] 44x: Fix problem with DDR controller setup (refresh rate)
This patch fixes a problem with an incorrect setup for the refresh
timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c
Signed-off-by: Stefan Roese <sr@denx.de>
commit f16c1da9577f06c5fc08651a4065537407de4635
Author: Stefan Roese <sr@denx.de>
Date: Sat Jan 6 15:56:13 2007 +0100
[PATCH] Update ALPR board files
This update brings the ALPR board support to the newest version.
It also fixes a problem with the NAND driver.
Signed-off-by: Stefan Roese <sr@denx.de>
commit cd1d937f90250a32988c37b2b4af8364d25de8ed
Author: Stefan Roese <sr@denx.de>
Date: Fri Jan 5 11:46:05 2007 +0100
[PATCH] nand: Fix problem with oobsize calculation
Here the description from Brian Brelsford <Brian_Brelsford@dell.com>:
The Hynix part returns a 0x1d in the 4th ID byte. The Samsung part
returns a 0x15. In the code fragment below bits [1:0] determine the
page size, it is ANDed via "(extid & 0x3)" then shifted out. The
next field is also ANDed with 0x3. However this is a one bit field
as defined in the Hynix and Samsung parts in the 4th ID byte that
determins the oobsize, not a two bit field. It works on Samsung as
bits[3:2] are 01. However for the Hynix there is a 11 in these two
bits, so the oob size gets messed up.
I checked the correct linux code and the suggested fix from Brian is
also available in the linux nand mtd driver.
Signed-off-by: Stefan Roese <sr@denx.de>
commit a78bc443ae5a4a8ba87590587d5e35bf5a787b2e
Author: Stefan Roese <sr@denx.de>
Date: Fri Jan 5 10:40:36 2007 +0100
[PATCH] Clear PLB4A0_ACR[WRP] on Sequoia (440EPx)
This fix will make the MAL burst disabling patch for the Linux
EMAC driver obsolete.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 023889838282b6237b401664f22dd22dfba2c066
Author: Stefan Roese <sr@denx.de>
Date: Fri Jan 5 10:38:05 2007 +0100
[PATCH] Add DDR2 optimization code for Sequoia (440EPx) board
This code will optimize the DDR2 controller setup on a board specific
basis.
Note: This code doesn't work right now on the NAND booting image for the
Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.
Signed-off-by: Stefan Roese <sr@denx.de>
commit cce4acbb68398634b8d011ed7bb0d12269c84230
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Thu Dec 28 19:08:21 2006 +0100
Few V38B changes:
- fix a typo in V38B config file
- move watchdog initialisation earlier in the boot process
- add "wdt=off" to default kernel command line (disables kernel watchdog)
commit 92eb729bad876725aeea908d2addba0800620840
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Wed Dec 27 01:26:13 2006 +0100
Fix bug in adaption of Stefano Babic's CFI driver patch.
commit 9c0f42ecfe25f7ffce8ec7a815f03864d723ffe3
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Sun Dec 24 01:42:57 2006 +0100
Minor code cleanup.
commit d784fdb05900ada3686d5778783e1fb328e9fb66
Author: Stefano Babic <sbabic@denx.de>
Date: Tue Dec 12 00:22:42 2006 +0100
Fix cfi failure with Spansion Flash (Spansion Flash Devices have a different offset to go into CFI mode)
commit 1b3c360c235dc684ec06c2d5f183f0a282ce45e2
Author: Stefan Roese <sr@denx.de>
Date: Fri Dec 22 14:29:40 2006 +0100
[PATCH] Fix sequoia flash autodetection (finally correct)
Now 32MByte and 64MByte FLASH is know to work and other
configurations should work too.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 82e5236a8b719543643fd26d5827938ab2b94818
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Fri Dec 22 10:30:26 2006 +0100
Minor code cleanup; update CHANGELOG.
commit fa23044564091f05d9695beb7b5b9a931e7f41a4
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Thu Dec 21 17:17:02 2006 +0100
Added support for the TQM8272 board from TQ
Signed-off-by: Heiko Schocher <hs@denx.de>
commit 6dedf3d49dd14c3bf541c8ecee7ffaac5f0e1d6c
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Thu Dec 21 16:14:48 2006 +0100
[PATCH] Add support for the UC101 board from MAN.
Signed-off-by: Heiko Schocher <hs@denx.de>
commit c84bad0ef60e7055ab0bd49b93069509cecc382a
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Wed Dec 20 00:29:43 2006 +0100
@ -210,7 +601,7 @@ Date: Mon Nov 27 17:04:06 2006 +0100
[PATCH] Allow CONFIG_OF_FLAT_TREE to boot a non-arch/powerpc kernel
This patch allows an arch/ppc kernel to be booted by just passing 1 or 2
arguments to bootm. It removes the getenv("disable_of") test that used
arguments to bootm. It removes the getenv("disable_of") test that used
to be used for this purpose.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
@ -908,7 +1299,7 @@ Date: Tue Oct 24 23:47:37 2006 -0500
If a Multi-Image file contains a third image we try to use it as a
device tree. The device tree image is assumed to be uncompressed in the
image file. We automatically allocate space for the device tree in memory
image file. We automatically allocate space for the device tree in memory
and provide an 8k pad to allow more than a reasonable amount of growth.
Additionally, a device tree that was contained in flash will now automatically

2
MAINTAINERS
View file

@ -292,6 +292,7 @@ Stefan Roese <sr@denx.de>
pcs440ep PPC440EP
sequoia PPC440EPx
sycamore PPC405GPr
taishan PPC440GX
walnut PPC405GP
yellowstone PPC440GR
yosemite PPC440EP
@ -464,6 +465,7 @@ Stefan Roese <sr@denx.de>
ixdpg425 xscale
pdnb3 xscale
scpu xscale
Robert Schwebel <r.schwebel@pengutronix.de>

11
MAKEALL
View file

@ -85,10 +85,11 @@ LIST_4xx=" \
MIP405 MIP405T ML2 ml300 \
ocotea OCRTC ORSG p3p440 \
PCI405 pcs440ep PIP405 PLU405 \
PMC405 PPChameleonEVB sbc405 sequoia \
sequoia_nand VOH405 VOM405 W7OLMC \
W7OLMG walnut WUH405 XPEDITE1K \
yellowstone yosemite yucca \
PMC405 PPChameleonEVB sbc405 sc3 \
sequoia sequoia_nand taishan VOH405 \
VOM405 W7OLMC W7OLMG walnut \
WUH405 XPEDITE1K yellowstone yosemite \
yucca \
"
#########################################################################
@ -225,7 +226,7 @@ LIST_pxa=" \
xsengine zylonite \
"
LIST_ixp="ixdp425 ixdpg425 pdnb3"
LIST_ixp="ixdp425 ixdpg425 pdnb3 scpu"
LIST_arm=" \

28
Makefile
View file

@ -22,8 +22,8 @@
#
VERSION = 1
PATCHLEVEL = 1
SUBLEVEL = 6
PATCHLEVEL = 2
SUBLEVEL = 0
EXTRAVERSION =
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
VERSION_FILE = $(obj)include/version_autogenerated.h
@ -557,6 +557,7 @@ Total5200_Rev2_lowboot_config: unconfig
@$(MKCONFIG) -a Total5200 ppc mpc5xxx total5200
cam5200_config \
cam5200_niosflash_config \
fo300_config \
MiniFAP_config \
TQM5200S_config \
@ -574,6 +575,10 @@ TQM5200_STK100_config: unconfig
echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \
echo "... TQM5200S on Cam5200" ; \
}
@[ -z "$(findstring niosflash,$@)" ] || \
{ echo "#define CONFIG_CAM5200_NIOSFLASH" >>$(obj)include/config.h ; \
echo "... with NIOS flash driver" ; \
}
@[ -z "$(findstring fo300,$@)" ] || \
{ echo "#define CONFIG_FO300" >>$(obj)include/config.h ; \
echo "... TQM5200 on FO300" ; \
@ -597,6 +602,8 @@ TQM5200_STK100_config: unconfig
{ echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp ; \
}
@$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200
uc101_config: unconfig
@$(MKCONFIG) uc101 ppc mpc5xxx uc101
#########################################################################
## MPC8xx Systems
@ -1193,10 +1200,16 @@ sequoia_nand_config: unconfig
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
sc3_config:unconfig
@./mkconfig $(@:_config=) ppc ppc4xx sc3
sycamore_config: unconfig
@echo "Configuring for sycamore board as subset of walnut..."
@$(MKCONFIG) -a walnut ppc ppc4xx walnut amcc
taishan_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
VOH405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx voh405 esd
@ -2056,8 +2069,15 @@ pleb2_config : unconfig
logodl_config : unconfig
@$(MKCONFIG) $(@:_config=) arm pxa logodl
pdnb3_config : unconfig
@$(MKCONFIG) $(@:_config=) arm ixp pdnb3 prodrive
pdnb3_config \
scpu_config: unconfig
@if [ "$(findstring scpu_,$@)" ] ; then \
echo "#define CONFIG_SCPU" >>include/config.h ; \
echo "... on SCPU board variant" ; \
else \
>include/config.h ; \
fi
@$(MKCONFIG) -a pdnb3 arm ixp pdnb3 prodrive
pxa255_idp_config: unconfig
@$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp

2
board/amcc/sequoia/init.S
View file

@ -90,7 +90,7 @@ tlbtab:
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
*/
#ifndef CONFIG_NAND_SPL
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
#else

366
board/amcc/sequoia/sdram.c
View file

@ -1,4 +1,11 @@
/*
* (C) Copyright 2006
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
*
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
@ -18,10 +25,352 @@
* MA 02111-1307 USA
*/
/* define DEBUG for debug output */
#undef DEBUG
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <ppc440.h>
#include "sdram.h"
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
defined(CONFIG_DDR_DATA_EYE)
/*-----------------------------------------------------------------------------+
* wait_for_dlllock.
+----------------------------------------------------------------------------*/
static int wait_for_dlllock(void)
{
unsigned long val;
int wait = 0;
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_17);
val = DDR0_17_DLLLOCKREG_UNLOCKED;
while (wait != 0xffff) {
val = mfdcr(ddrcfgd);
if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
/* dlllockreg bit on */
return 0;
else
wait++;
}
debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
debug("Waiting for dlllockreg bit to raise\n");
return -1;
}
#endif
#if defined(CONFIG_DDR_DATA_EYE)
/*-----------------------------------------------------------------------------+
* wait_for_dram_init_complete.
+----------------------------------------------------------------------------*/
int wait_for_dram_init_complete(void)
{
unsigned long val;
int wait = 0;
/* --------------------------------------------------------------+
* Wait for 'DRAM initialization complete' bit in status register
* -------------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_00);
while (wait != 0xffff) {
val = mfdcr(ddrcfgd);
if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
/* 'DRAM initialization complete' bit */
return 0;
else
wait++;
}
debug("DRAM initialization complete bit in status register did not rise\n");
return -1;
}
#define NUM_TRIES 64
#define NUM_READS 10
/*-----------------------------------------------------------------------------+
* denali_core_search_data_eye.
+----------------------------------------------------------------------------*/
void denali_core_search_data_eye(unsigned long memory_size)
{
int k, j;
u32 val;
u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
volatile u32 *ram_pointer;
u32 test[NUM_TRIES] = {
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'wr_dqs_shift'
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_09);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'dqs_out_shift' = wr_dqs_shift + 32
* ----------------------------------------------------------*/
dqs_out_shift = wr_dqs_shift + 32;
mtdcr(ddrcfga, DDR0_22);
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
passing_cases = 0;
for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
/* -----------------------------------------------------------+
* Set 'dll_dqs_delay_X'.
* ----------------------------------------------------------*/
/* dll_dqs_delay_0 */
mtdcr(ddrcfga, DDR0_17);
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
if (wait_for_dlllock() != 0) {
printf("dlllock did not occur !!!\n");
printf("denali_core_search_data_eye!!!\n");
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
wr_dqs_shift, dll_dqs_delay_X);
hang();
}
ppcMsync();
ppcMbar();
if (wait_for_dram_init_complete() != 0) {
printf("dram init complete did not occur !!!\n");
printf("denali_core_search_data_eye!!!\n");
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
wr_dqs_shift, dll_dqs_delay_X);
hang();
}
udelay(100); /* wait 100us to ensure init is really completed !!! */
/* write values */
for (j=0; j<NUM_TRIES; j++) {
ram_pointer[j] = test[j];
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
}
/* read values back */
for (j=0; j<NUM_TRIES; j++) {
for (k=0; k<NUM_READS; k++) {
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
if (ram_pointer[j] != test[j])
break;
}
/* read error */
if (k != NUM_READS)
break;
}
/* See if the dll_dqs_delay_X value passed.*/
if (j < NUM_TRIES) {
/* Failed */
passing_cases = 0;
/* break; */
} else {
/* Passed */
if (passing_cases == 0)
dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
passing_cases++;
if (passing_cases >= max_passing_cases) {
max_passing_cases = passing_cases;
wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
dll_dqs_delay_X_end_window = dll_dqs_delay_X;
}
}
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
/* -----------------------------------------------------------+
* Largest passing window is now detected.
* ----------------------------------------------------------*/
/* Compute dll_dqs_delay_X value */
dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
debug("DQS calibration - Window detected:\n");
debug("max_passing_cases = %d\n", max_passing_cases);
debug("wr_dqs_shift = %d\n", wr_dqs_shift);
debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
debug("dll_dqs_delay_X window = %d - %d\n",
dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'wr_dqs_shift'
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_09);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
debug("DDR0_09=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Set 'dqs_out_shift' = wr_dqs_shift + 32
* ----------------------------------------------------------*/
dqs_out_shift = wr_dqs_shift + 32;
mtdcr(ddrcfga, DDR0_22);
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
debug("DDR0_22=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Set 'dll_dqs_delay_X'.
* ----------------------------------------------------------*/
/* dll_dqs_delay_0 */
mtdcr(ddrcfga, DDR0_17);
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_17=0x%08lx\n", val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_18=0x%08lx\n", val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_19=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
if (wait_for_dlllock() != 0) {
printf("dlllock did not occur !!!\n");
hang();
}
ppcMsync();
ppcMbar();
if (wait_for_dram_init_complete() != 0) {
printf("dram init complete did not occur !!!\n");
hang();
}
udelay(100); /* wait 100us to ensure init is really completed !!! */
}
#endif /* CONFIG_DDR_DATA_EYE */
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
@ -30,8 +379,6 @@
long int initdram (int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
volatile ulong val;
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_00, 0x0000190A);
@ -64,14 +411,15 @@ long int initdram (int board_type)
mtsdram(DDR0_44, 0x00000005);
mtsdram(DDR0_02, 0x00000001);
/*
* Wait for DCC master delay line to finish calibration
*/
mfsdram(DDR0_17, val);
while (((val >> 8) & 0x000007f) == 0) {
mfsdram(DDR0_17, val);
}
wait_for_dlllock();
#endif /* #ifndef CONFIG_NAND_U_BOOT */
#ifdef CONFIG_DDR_DATA_EYE
/* -----------------------------------------------------------+
* Perform data eye search if requested.
* ----------------------------------------------------------*/
denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
#endif
return (CFG_MBYTES_SDRAM << 20);
}

505
board/amcc/sequoia/sdram.h Normal file
View file

@ -0,0 +1,505 @@
/*
* (C) Copyright 2006
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SPD_SDRAM_DENALI_H_
#define _SPD_SDRAM_DENALI_H_
#define ppcMsync sync
#define ppcMbar eieio
/* General definitions */
#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */
#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */
#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */
#define SDRAM_NONE 0 /* No DIMM detected in Slot */
#define MAXRANKS 2 /* 2 ranks maximum */
/* Supported PLB Frequencies */
#define PLB_FREQ_133MHZ 133333333
#define PLB_FREQ_152MHZ 152000000
#define PLB_FREQ_160MHZ 160000000
#define PLB_FREQ_166MHZ 166666666
/* Denali Core Registers */
#define SDRAM_DCR_BASE 0x10
#define DDR_DCR_BASE 0x10
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
/*-----------------------------------------------------------------------------+
| Values for ddrcfga register - indirect addressing of these regs
+-----------------------------------------------------------------------------*/
#define DDR0_00 0x00
#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
#define DDR0_00_INT_ACK_ALL 0x7F000000
#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
/* Status */
#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
#define DDR0_00_INT_STATUS_BIT0 0x00010000
/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
#define DDR0_00_INT_STATUS_BIT1 0x00020000
/* Bit2. Single correctable ECC event detected */
#define DDR0_00_INT_STATUS_BIT2 0x00040000
/* Bit3. Multiple correctable ECC events detected. */
#define DDR0_00_INT_STATUS_BIT3 0x00080000
/* Bit4. Single uncorrectable ECC event detected. */
#define DDR0_00_INT_STATUS_BIT4 0x00100000
/* Bit5. Multiple uncorrectable ECC events detected. */
#define DDR0_00_INT_STATUS_BIT5 0x00200000
/* Bit6. DRAM initialization complete. */
#define DDR0_00_INT_STATUS_BIT6 0x00400000
/* Bit7. Logical OR of all lower bits. */
#define DDR0_00_INT_STATUS_BIT7 0x00800000
#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_01 0x01
#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_01_INT_MASK_MASK 0x000000FF
#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
#define DDR0_02 0x02
#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_02_START_MASK 0x00000001
#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_02_START_OFF 0x00000000
#define DDR0_02_START_ON 0x00000001
#define DDR0_03 0x03
#define DDR0_03_BSTLEN_MASK 0x07000000
#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_03_CASLAT_MASK 0x00070000
#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_03_INITAREF_MASK 0x0000000F
#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
#define DDR0_04 0x04
#define DDR0_04_TRC_MASK 0x1F000000
#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_04_TRRD_MASK 0x00070000
#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_04_TRTP_MASK 0x00000700
#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_05 0x05
#define DDR0_05_TMRD_MASK 0x1F000000
#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_05_TEMRS_MASK 0x00070000
#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_05_TRP_MASK 0x00000F00
#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
#define DDR0_05_TRAS_MIN_MASK 0x000000FF
#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#define DDR0_06 0x06
#define DDR0_06_WRITEINTERP_MASK 0x01000000
#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_06_TWTR_MASK 0x00070000
#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#define DDR0_06_TDLL_MASK 0x0000FF00
#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_06_TRFC_MASK 0x0000007F
#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_07 0x07
#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_07_TFAW_MASK 0x001F0000
#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_07_AREFRESH_MASK 0x00000001
#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_08 0x08
#define DDR0_08_WRLAT_MASK 0x07000000
#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_08_TCPD_MASK 0x00FF0000
#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_08_DQS_N_EN_MASK 0x00000100
#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_09 0x09
#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_09_RTT_0_MASK 0x00030000
#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_10 0x0A
#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_10_CS_MAP_MASK 0x00000300
#define DDR0_10_CS_MAP_NO_MEM 0x00000000
#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
#define DDR0_11 0x0B
#define DDR0_11_SREFRESH_MASK 0x01000000
#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_11_TXSNR_MASK 0x00FF0000
#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_11_TXSR_MASK 0x0000FF00
#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_12 0x0C
#define DDR0_12_TCKE_MASK 0x0000007
#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
#define DDR0_13 0x0D
#define DDR0_14 0x0E
#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
#define DDR0_14_REDUC_MASK 0x00010000
#define DDR0_14_REDUC_64BITS 0x00000000
#define DDR0_14_REDUC_32BITS 0x00010000
#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_15 0x0F
#define DDR0_16 0x10
#define DDR0_17 0x11
#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_18 0x12
#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_19 0x13
#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_20 0x14
#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_21 0x15
#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_22 0x16
/* ECC */
#define DDR0_22_CTRL_RAW_MASK 0x03000000
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
#define DDR0_23 0x17
#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_24 0x18
#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
#define DDR0_25 0x19
#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
#define DDR0_26 0x1A
#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
#define DDR0_26_TREF_MASK 0x00003FFF
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
#define DDR0_27 0x1B
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
#define DDR0_27_TINIT_MASK 0x0000FFFF
#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
#define DDR0_28 0x1C
#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
#define DDR0_29 0x1D
#define DDR0_30 0x1E
#define DDR0_31 0x1F
#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
#define DDR0_32 0x20
#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_33 0x21
#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_34 0x22
#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_35 0x23
#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_36 0x24
#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_37 0x25
#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_38 0x26
#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_39 0x27
#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_40 0x28
#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_41 0x29
#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
#define DDR0_42 0x2A
#define DDR0_42_ADDR_PINS_MASK 0x07000000
#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
#define DDR0_43 0x2B
#define DDR0_43_TWR_MASK 0x07000000
#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
#define DDR0_43_APREBIT_MASK 0x000F0000
#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
#define DDR0_44 0x2C
#define DDR0_44_TRCD_MASK 0x000000FF
#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
#endif /* _SPD_SDRAM_DENALI_H_ */

22
board/amcc/sequoia/sequoia.c
View file

@ -35,9 +35,9 @@ ulong flash_get_size (ulong base, int banknum);
int board_early_init_f(void)
{
unsigned long sdr0_cust0;
unsigned long sdr0_pfc1, sdr0_pfc2;
register uint reg;
u32 sdr0_cust0;
u32 sdr0_pfc1, sdr0_pfc2;
u32 reg;
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
@ -142,6 +142,7 @@ int misc_init_r(void)
{
uint pbcr;
int size_val = 0;
u32 reg;
#ifdef CONFIG_440EPX
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
@ -335,18 +336,33 @@ int misc_init_r(void)
}
#endif /* CONFIG_440EPX */
/*
* Clear PLB4A0_ACR[WRP]
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
mtdcr(plb4_acr, reg);
return 0;
}
int checkboard(void)
{
char *s = getenv("serial#");
u8 rev;
u8 val;
#ifdef CONFIG_440EPX
printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
#else
printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
#endif
rev = *(u8 *)(CFG_CPLD + 0);
val = *(u8 *)(CFG_CPLD + 5) & 0x01;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {
puts(", serial# ");
puts(s);

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#
# (C) Copyright 2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o lcd.o update.o showinfo.o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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#
# (C) Copyright 2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMCC 440GX Reference Platform (Taishan) board
#
#TEXT_BASE = 0xFFFE0000
ifeq ($(ramsym),1)
TEXT_BASE = 0x07FD0000
else
TEXT_BASE = 0xFFFC0000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif

97
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/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <config.h>
/* General */
#define TLB_VALID 0x00000200
#define _256M 0x10000000
/* Supported page sizes */
#define SZ_1K 0x00000000
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
#define SZ_8M 0x00000060
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
/* Storage attributes */
#define SA_W 0x00000800 /* Write-through */
#define SA_I 0x00000400 /* Caching inhibited */
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
/* Access control */
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
/* Some handy macros */
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
#define TLB2(a) ( (a)&0x00000fbf )
#define tlbtab_start\
mflr r1 ;\
bl 0f ;
#define tlbtab_end\
.long 0, 0, 0 ; \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X )
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
tlbtab_end

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/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <miiphy.h>
#ifdef CONFIG_TAISHAN
#define LCD_DELAY_NORMAL_US 100
#define LCD_DELAY_NORMAL_MS 2
#define LCD_CMD_ADDR ((volatile char *)(CFG_EBC2_LCM_BASE))
#define LCD_DATA_ADDR ((volatile char *)(CFG_EBC2_LCM_BASE+1))
#define LCD_BLK_CTRL ((volatile char *)(CFG_EBC1_FPGA_BASE+0x2))
#define mdelay(t) ({unsigned long msec=(t); while (msec--) { udelay(1000);}})
static int g_lcd_init_b = 0;
static char *amcc_logo = " AMCC TAISHAN 440GX EvalBoard";
static char addr_flag = 0x80;
static void lcd_bl_ctrl(char val)
{
char cpld_val;
cpld_val = *LCD_BLK_CTRL;
*LCD_BLK_CTRL = val | cpld_val;
}
static void lcd_putc(char val)
{
int i = 100;
char addr;
while (i--) {
if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
udelay(LCD_DELAY_NORMAL_US);
break;
}
udelay(LCD_DELAY_NORMAL_US);
}
if (*LCD_CMD_ADDR & 0x80) {
printf("LCD is busy\n");
return;
}
addr = *LCD_CMD_ADDR;
udelay(LCD_DELAY_NORMAL_US);
if ((addr != 0) && (addr % 0x10 == 0)) {
addr_flag ^= 0x40;
*LCD_CMD_ADDR = addr_flag;
}
udelay(LCD_DELAY_NORMAL_US);
*LCD_DATA_ADDR = val;
udelay(LCD_DELAY_NORMAL_US);
}
static void lcd_puts(char *s)
{
char *p = s;
int i = 100;
while (i--) {
if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
udelay(LCD_DELAY_NORMAL_US);
break;
}
udelay(LCD_DELAY_NORMAL_US);
}
if (*LCD_CMD_ADDR & 0x80) {
printf("LCD is busy\n");
return;
}
while (*p)
lcd_putc(*p++);
}
static void lcd_put_logo(void)
{
int i = 100;
char *p = amcc_logo;
while (i--) {
if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
udelay(LCD_DELAY_NORMAL_US);
break;
}
udelay(LCD_DELAY_NORMAL_US);
}
if (*LCD_CMD_ADDR & 0x80) {
printf("LCD is busy\n");
return;
}
*LCD_CMD_ADDR = 0x80;
while (*p)
lcd_putc(*p++);
}
int lcd_init(void)
{
if (g_lcd_init_b == 0) {
puts("LCD: ");
mdelay(100); /* Waiting for the LCD initialize */
*LCD_CMD_ADDR = 0x38; /*set function:8-bit,2-line,5x7 font type */
udelay(LCD_DELAY_NORMAL_US);
*LCD_CMD_ADDR = 0x0f; /*set display on,cursor on,blink on */
udelay(LCD_DELAY_NORMAL_US);
*LCD_CMD_ADDR = 0x01; /*display clear */
mdelay(LCD_DELAY_NORMAL_MS);
*LCD_CMD_ADDR = 0x06; /*set entry */
udelay(LCD_DELAY_NORMAL_US);
lcd_bl_ctrl(0x02);
lcd_put_logo();
puts(" ready\n");
g_lcd_init_b = 1;
}
return 0;
}
static int do_lcd_test(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
lcd_init();
return 0;
}
static int do_lcd_clear(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
*LCD_CMD_ADDR = 0x01;
mdelay(LCD_DELAY_NORMAL_MS);
return 0;
}
static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
if (argc < 2) {
printf("%s", cmdtp->usage);
return 1;
}
lcd_puts(argv[1]);
return 0;
}
static int do_lcd_putc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
if (argc < 2) {
printf("%s", cmdtp->usage);
return 1;
}
lcd_putc((char)argv[1][0]);
return 0;
}
static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
ulong count;
ulong dir;
char cur_addr;
if (argc < 3) {
printf("%s", cmdtp->usage);
return 1;
}
count = simple_strtoul(argv[1], NULL, 16);
if (count > 31) {
printf("unable to shift > 0x20\n");
count = 0;
}
dir = simple_strtoul(argv[2], NULL, 16);
cur_addr = *LCD_CMD_ADDR;
udelay(LCD_DELAY_NORMAL_US);
if (dir == 0x0) {
if (addr_flag == 0x80) {
if (count >= (cur_addr & 0xf)) {
*LCD_CMD_ADDR = 0x80;
udelay(LCD_DELAY_NORMAL_US);
count = 0;
}
} else {
if (count >= ((cur_addr & 0x0f) + 0x0f)) {
*LCD_CMD_ADDR = 0x80;
addr_flag = 0x80;
udelay(LCD_DELAY_NORMAL_US);
count = 0x0;
} else if (count >= (cur_addr & 0xf)) {
count -= cur_addr & 0xf;
*LCD_CMD_ADDR = 0x80 | 0xf;
addr_flag = 0x80;
udelay(LCD_DELAY_NORMAL_US);
}
}
} else {
if (addr_flag == 0x80) {
if (count >= (0x1f - (cur_addr & 0xf))) {
count = 0x0;
addr_flag = 0xc0;
*LCD_CMD_ADDR = 0xc0 | 0xf;
udelay(LCD_DELAY_NORMAL_US);
} else if ((count + (cur_addr & 0xf)) >= 0x0f) {
count = count + (cur_addr & 0xf) - 0x0f;
addr_flag = 0xc0;
*LCD_CMD_ADDR = 0xc0;
udelay(LCD_DELAY_NORMAL_US);
}
} else if ((count + (cur_addr & 0xf)) >= 0x0f) {
count = 0x0;
*LCD_CMD_ADDR = 0xc0 | 0xf;
udelay(LCD_DELAY_NORMAL_US);
}
}
while (count--) {
if (dir == 0) {
*LCD_CMD_ADDR = 0x10;
} else {
*LCD_CMD_ADDR = 0x14;
}
udelay(LCD_DELAY_NORMAL_US);
}
return 0;
}
U_BOOT_CMD(lcd_test, 1, 1, do_lcd_test, "lcd_test - lcd test display\n", NULL);
U_BOOT_CMD(lcd_cls, 1, 1, do_lcd_clear, "lcd_cls - lcd clear display\n", NULL);
U_BOOT_CMD(lcd_puts, 2, 1, do_lcd_puts,
"lcd_puts - display string on lcd\n",
"<string> - <string> to be displayed\n");
U_BOOT_CMD(lcd_putc, 2, 1, do_lcd_putc,
"lcd_putc - display char on lcd\n",
"<char> - <char> to be displayed\n");
U_BOOT_CMD(lcd_cur, 3, 1, do_lcd_cur,
"lcd_cur - shift cursor on lcd\n",
"<count> <dir>- shift cursor on lcd <count> times, direction is <dir> \n"
" <count> - 0~31\n" " <dir> - 0,backward; 1, forward\n");
#if 0 /* test-only */
void set_phy_loopback_mode(void)
{
char devemac2[32];
char devemac3[32];
sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
#if 0
unsigned short reg_short;
miiphy_read(devemac2, 0x1, 1, &reg_short);
if (reg_short & 0x04) {
/*
* printf("EMAC2 link up,do nothing\n");
*/
} else {
udelay(1000);
miiphy_write(devemac2, 0x1, 0, 0x6000);
udelay(1000);
miiphy_read(devemac2, 0x1, 0, &reg_short);
if (reg_short != 0x6000) {
printf
("\nEMAC2 error set LOOPBACK mode error,reg2[0]=%x\n",
reg_short);
}
}
miiphy_read(devemac3, 0x3, 1, &reg_short);
if (reg_short & 0x04) {
/*
* printf("EMAC3 link up,do nothing\n");
*/
} else {
udelay(1000);
miiphy_write(devemac3, 0x3, 0, 0x6000);
udelay(1000);
miiphy_read(devemac3, 0x3, 0, &reg_short);
if (reg_short != 0x6000) {
printf
("\nEMAC3 error set LOOPBACK mode error,reg2[0]=%x\n",
reg_short);
}
}
#else
/* Set PHY as LOOPBACK MODE, for Linux emac initializing */
miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0, 0x6000);
udelay(1000);
miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0, 0x6000);
udelay(1000);
#endif /* 0 */
}
void set_phy_normal_mode(void)
{
char devemac2[32];
char devemac3[32];
unsigned short reg_short;
sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
/* Set phy of EMAC2 */
miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x16, &reg_short);
reg_short &= ~(0x7);
reg_short |= 0x6; /* RGMII DLL Delay */
miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x16, reg_short);
miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x17, &reg_short);
reg_short &= ~(0x40);
miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x17, reg_short);
miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x1c, 0x74f0);
/* Set phy of EMAC3 */
miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x16, &reg_short);
reg_short &= ~(0x7);
reg_short |= 0x6; /* RGMII DLL Delay */
miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x16, reg_short);
miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x17, &reg_short);
reg_short &= ~(0x40);
miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x17, reg_short);
miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x1c, 0x74f0);
}
#endif /* 0 - test only */
static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
volatile unsigned int *GpioOr =
(volatile unsigned int *)(CFG_PERIPHERAL_BASE + 0x700);
*GpioOr |= 0x00300000;
return 0;
}
static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
volatile unsigned int *GpioOr =
(volatile unsigned int *)(CFG_PERIPHERAL_BASE + 0x700);
*GpioOr &= ~0x00300000;
return 0;
}
U_BOOT_CMD(ledon, 1, 1, do_led_test_on,
"ledon - led test light on\n", NULL);
U_BOOT_CMD(ledoff, 1, 1, do_led_test_off,
"ledoff - led test light off\n", NULL);
#endif

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/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <pci.h>
void show_reset_reg(void)
{
unsigned long reg;
/* read clock regsiter */
printf("===== Display reset and initialize register Start =========\n");
mfclk(clk_pllc,reg);
printf("cpr_pllc = %#010x\n",reg);
mfclk(clk_plld,reg);
printf("cpr_plld = %#010x\n",reg);
mfclk(clk_primad,reg);
printf("cpr_primad = %#010x\n",reg);
mfclk(clk_primbd,reg);
printf("cpr_primbd = %#010x\n",reg);
mfclk(clk_opbd,reg);
printf("cpr_opbd = %#010x\n",reg);
mfclk(clk_perd,reg);
printf("cpr_perd = %#010x\n",reg);
mfclk(clk_mald,reg);
printf("cpr_mald = %#010x\n",reg);
/* read sdr register */
mfsdr(sdr_ebc,reg);
printf("sdr_ebc = %#010x\n",reg);
mfsdr(sdr_cp440,reg);
printf("sdr_cp440 = %#010x\n",reg);
mfsdr(sdr_xcr,reg);
printf("sdr_xcr = %#010x\n",reg);
mfsdr(sdr_xpllc,reg);
printf("sdr_xpllc = %#010x\n",reg);
mfsdr(sdr_xplld,reg);
printf("sdr_xplld = %#010x\n",reg);
mfsdr(sdr_pfc0,reg);
printf("sdr_pfc0 = %#010x\n",reg);
mfsdr(sdr_pfc1,reg);
printf("sdr_pfc1 = %#010x\n",reg);
mfsdr(sdr_cust0,reg);
printf("sdr_cust0 = %#010x\n",reg);
mfsdr(sdr_cust1,reg);
printf("sdr_cust1 = %#010x\n",reg);
mfsdr(sdr_uart0,reg);
printf("sdr_uart0 = %#010x\n",reg);
mfsdr(sdr_uart1,reg);
printf("sdr_uart1 = %#010x\n",reg);
printf("===== Display reset and initialize register End =========\n");
}
void show_xbridge_info(void)
{
unsigned long reg;
printf("PCI-X chip control registers\n");
mfsdr(sdr_xcr, reg);
printf("sdr_xcr = %#010x\n", reg);
mfsdr(sdr_xpllc, reg);
printf("sdr_xpllc = %#010x\n", reg);
mfsdr(sdr_xplld, reg);
printf("sdr_xplld = %#010x\n", reg);
printf("PCI-X Bridge Configure registers\n");
printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID));
printf("PCIX0_DEVID = %#06x\n", in16r(PCIX0_DEVID));
printf("PCIX0_CMD = %#06x\n", in16r(PCIX0_CMD));
printf("PCIX0_STATUS = %#06x\n", in16r(PCIX0_STATUS));
printf("PCIX0_REVID = %#04x\n", in8(PCIX0_REVID));
printf("PCIX0_CACHELS = %#04x\n", in8(PCIX0_CACHELS));
printf("PCIX0_LATTIM = %#04x\n", in8(PCIX0_LATTIM));
printf("PCIX0_HDTYPE = %#04x\n", in8(PCIX0_HDTYPE));
printf("PCIX0_BIST = %#04x\n", in8(PCIX0_BIST));
printf("PCIX0_BAR0 = %#010x\n", in32r(PCIX0_BAR0));
printf("PCIX0_BAR1 = %#010x\n", in32r(PCIX0_BAR1));
printf("PCIX0_BAR2 = %#010x\n", in32r(PCIX0_BAR2));
printf("PCIX0_BAR3 = %#010x\n", in32r(PCIX0_BAR3));
printf("PCIX0_BAR4 = %#010x\n", in32r(PCIX0_BAR4));
printf("PCIX0_BAR5 = %#010x\n", in32r(PCIX0_BAR5));
printf("PCIX0_CISPTR = %#010x\n", in32r(PCIX0_CISPTR));
printf("PCIX0_SBSSYSVID = %#010x\n", in16r(PCIX0_SBSYSVID));
printf("PCIX0_SBSSYSID = %#010x\n", in16r(PCIX0_SBSYSID));
printf("PCIX0_EROMBA = %#010x\n", in32r(PCIX0_EROMBA));
printf("PCIX0_CAP = %#04x\n", in8(PCIX0_CAP));
printf("PCIX0_INTLN = %#04x\n", in8(PCIX0_INTLN));
printf("PCIX0_INTPN = %#04x\n", in8(PCIX0_INTPN));
printf("PCIX0_MINGNT = %#04x\n", in8(PCIX0_MINGNT));
printf("PCIX0_MAXLTNCY = %#04x\n", in8(PCIX0_MAXLTNCY));
printf("PCIX0_BRDGOPT1 = %#010x\n", in32r(PCIX0_BRDGOPT1));
printf("PCIX0_BRDGOPT2 = %#010x\n", in32r(PCIX0_BRDGOPT2));
printf("PCIX0_POM0LAL = %#010x\n", in32r(PCIX0_POM0LAL));
printf("PCIX0_POM0LAH = %#010x\n", in32r(PCIX0_POM0LAH));
printf("PCIX0_POM0SA = %#010x\n", in32r(PCIX0_POM0SA));
printf("PCIX0_POM0PCILAL = %#010x\n", in32r(PCIX0_POM0PCIAL));
printf("PCIX0_POM0PCILAH = %#010x\n", in32r(PCIX0_POM0PCIAH));
printf("PCIX0_POM1LAL = %#010x\n", in32r(PCIX0_POM1LAL));
printf("PCIX0_POM1LAH = %#010x\n", in32r(PCIX0_POM1LAH));
printf("PCIX0_POM1SA = %#010x\n", in32r(PCIX0_POM1SA));
printf("PCIX0_POM1PCILAL = %#010x\n", in32r(PCIX0_POM1PCIAL));
printf("PCIX0_POM1PCILAH = %#010x\n", in32r(PCIX0_POM1PCIAH));
printf("PCIX0_POM2SA = %#010x\n", in32r(PCIX0_POM2SA));
printf("PCIX0_PIM0SA = %#010x\n", in32r(PCIX0_PIM0SA));
printf("PCIX0_PIM0LAL = %#010x\n", in32r(PCIX0_PIM0LAL));
printf("PCIX0_PIM0LAH = %#010x\n", in32r(PCIX0_PIM0LAH));
printf("PCIX0_PIM1SA = %#010x\n", in32r(PCIX0_PIM1SA));
printf("PCIX0_PIM1LAL = %#010x\n", in32r(PCIX0_PIM1LAL));
printf("PCIX0_PIM1LAH = %#010x\n", in32r(PCIX0_PIM1LAH));
printf("PCIX0_PIM2SA = %#010x\n", in32r(PCIX0_PIM1SA));
printf("PCIX0_PIM2LAL = %#010x\n", in32r(PCIX0_PIM1LAL));
printf("PCIX0_PIM2LAH = %#010x\n", in32r(PCIX0_PIM1LAH));
printf("PCIX0_XSTS = %#010x\n", in32r(PCIX0_STS));
}
int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
show_xbridge_info();
return 0;
}
U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info,
"xbriinfo - Show PCIX bridge info\n", NULL);
#define TAISHAN_PCI_DEV_ID0 0x800
#define TAISHAN_PCI_DEV_ID1 0x1000
void show_pcix_device_info(void)
{
int ii;
int dev;
u8 capp;
u8 xcapid;
u16 status;
u16 xcommand;
u32 xstatus;
for (ii = 0; ii < 2; ii++) {
if (ii == 0)
dev = TAISHAN_PCI_DEV_ID0;
else
dev = TAISHAN_PCI_DEV_ID1;
pci_read_config_word(dev, PCI_STATUS, &status);
if (status & PCI_STATUS_CAP_LIST) {
pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &capp);
pci_read_config_byte(dev, (int)(capp), &xcapid);
if (xcapid == 0x07) {
pci_read_config_word(dev, (int)(capp + 2),
&xcommand);
pci_read_config_dword(dev, (int)(capp + 4),
&xstatus);
printf("BUS0 dev%d Xcommand=%#06x,Xstatus=%#010x\n",
(ii + 1), xcommand, xstatus);
} else {
printf("BUS0 dev%d PCI-X CAP ID error,"
"CAP=%#04x,XCAPID=%#04x\n",
(ii + 1), capp, xcapid);
}
} else {
printf("BUS0 dev%d not found PCI_STATUS_CAP_LIST supporting\n",
ii + 1);
}
}
}
int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc,
char *argv[])
{
show_pcix_device_info();
return 0;
}
U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info,
"xdevinfo - Show PCIX Device info\n", NULL);
extern void show_reset_reg(void);
int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
show_reset_reg();
return 0;
}
U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info,
"resetinfo - Show Reset REG info\n", NULL);

331
board/amcc/taishan/taishan.c Normal file
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/*
* Copyright (C) 2004 PaulReynolds@lhsolutions.com
*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <spd_sdram.h>
#include <ppc4xx_enet.h>
#ifdef CFG_INIT_SHOW_RESET_REG
void show_reset_reg(void);
#endif
int lcd_init(void);
int board_early_init_f (void)
{
unsigned long reg;
volatile unsigned int *GpioOdr;
volatile unsigned int *GpioTcr;
volatile unsigned int *GpioOr;
/*-------------------------------------------------------------------------+
| Initialize EBC CONFIG
+-------------------------------------------------------------------------*/
mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
/*-------------------------------------------------------------------------+
| 64MB FLASH. Initialize bank 0 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
EBC_BXAP_BCE_DISABLE |
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
/*-------------------------------------------------------------------------+
| FPGA. Initialize bank 1 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
EBC_BXAP_BCE_DISABLE |
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
/*-------------------------------------------------------------------------+
| LCM. Initialize bank 2 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb2ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
EBC_BXAP_BCE_DISABLE |
EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
/*-------------------------------------------------------------------------+
| TMP. Initialize bank 3 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb3ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
EBC_BXAP_BCE_DISABLE |
EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
/*-------------------------------------------------------------------------+
| Connector 4~7. Initialize bank 3~ 7 with default values.
+-------------------------------------------------------------------------*/
mtebc(pb4ap,0);
mtebc(pb4cr,0);
mtebc(pb5ap,0);
mtebc(pb5cr,0);
mtebc(pb6ap,0);
mtebc(pb6cr,0);
mtebc(pb7ap,0);
mtebc(pb7cr,0);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr (uic0sr, 0xffffffff); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic0sr, 0xffffffff); /* clear all */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000000); /* all non-critical */
mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uic2er, 0x00000000); /* disable all */
mtdcr (uic2cr, 0x00000000); /* all non-critical */
mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic2sr, 0xffffffff); /* clear all */
mtdcr (uicb0sr, 0xfc000000); /* clear all */
mtdcr (uicb0er, 0x00000000); /* disable all */
mtdcr (uicb0cr, 0x00000000); /* all non-critical */
mtdcr (uicb0pr, 0xfc000000); /* */
mtdcr (uicb0tr, 0x00000000); /* */
mtdcr (uicb0vr, 0x00000001); /* */
/* Enable two GPIO 10~11 and TraceA signal */
mfsdr(sdr_pfc0,reg);
reg |= 0x00300000;
mtsdr(sdr_pfc0,reg);
mfsdr(sdr_pfc1,reg);
reg |= 0x00100000;
mtsdr(sdr_pfc1,reg);
/* Set GPIO 10 and 11 as output */
GpioOdr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x718);
GpioTcr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x704);
GpioOr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x700);
*GpioOdr &= ~(0x00300000);
*GpioTcr |= 0x00300000;
*GpioOr |= 0x00300000;
return 0;
}
int misc_init_r(void)
{
lcd_init();
return 0;
}
int checkboard (void)
{
char *s = getenv ("serial#");
printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
if (s != NULL) {
puts (", serial# ");
puts (s);
}
putc ('\n');
#ifdef CFG_INIT_SHOW_RESET_REG
show_reset_reg();
#endif
return (0);
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) 0x04000000;
uint *pend = (uint *) 0x0fc00000;
uint *p;
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The ocotea board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
}
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
DECLARE_GLOBAL_DATA_PTR;
/*--------------------------------------------------------------------------+
* Disable everything
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0SA, 0 ); /* disable */
out32r( PCIX0_PIM1SA, 0 ); /* disable */
out32r( PCIX0_PIM2SA, 0 ); /* disable */
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
/*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
out32r( PCIX0_BAR0, 0 );
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* The ocotea board is always configured as host. */
return(1);
}
#endif /* defined(CONFIG_PCI) */
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return (ctrlc());
}
#endif

157
board/amcc/taishan/u-boot.lds Normal file
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@ -0,0 +1,157 @@
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/taishan/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

78
board/amcc/taishan/update.c Normal file
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/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <i2c.h>
#if defined(CONFIG_TAISHAN)
const uchar bootstrap_buf[16] = {
0x86,
0x78,
0xc1,
0xa6,
0x09,
0x67,
0x04,
0x63,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00
};
static int update_boot_eeprom(void)
{
ulong len = 0x10;
uchar chip = CFG_BOOTSTRAP_IIC_ADDR;
uchar *pbuf = (uchar *)bootstrap_buf;
int ii, jj;
for (ii = 0; ii < len; ii++) {
if (i2c_write(chip, ii, 1, &pbuf[ii], 1) != 0) {
printf("i2c_write failed\n");
return -1;
}
/* wait 10ms */
for (jj = 0; jj < 10; jj++)
udelay(1000);
}
return 0;
}
int do_update_boot_eeprom(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
return update_boot_eeprom();
}
U_BOOT_CMD(update_boot_eeprom, 1, 1, do_update_boot_eeprom,
"update_boot_eeprom - update bootstrap eeprom content\n", NULL);
#endif

25
board/amcc/yellowstone/yellowstone.c
View file

@ -39,24 +39,6 @@ int board_early_init_f(void)
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
mtebc(pb1ap, 0x00000000);
mtebc(pb1cr, 0x00000000);
mtebc(pb2ap, 0x04814500);
/*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
mtebc(pb3ap, 0x00000000);
mtebc(pb3cr, 0x00000000);
mtebc(pb4ap, 0x00000000);
mtebc(pb4cr, 0x00000000);
mtebc(pb5ap, 0x00000000);
mtebc(pb5cr, 0x00000000);
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
@ -190,8 +172,15 @@ int misc_init_r (void)
int checkboard(void)
{
char *s = getenv("serial#");
u8 rev;
u8 val;
printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
rev = *(u8 *)(CFG_CPLD + 0);
val = *(u8 *)(CFG_CPLD + 5) & 0x01;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {
puts(", serial# ");
puts(s);

25
board/amcc/yosemite/yosemite.c
View file

@ -39,24 +39,6 @@ int board_early_init_f(void)
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
mtebc(pb1ap, 0x00000000);
mtebc(pb1cr, 0x00000000);
mtebc(pb2ap, 0x04814500);
/*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
mtebc(pb3ap, 0x00000000);
mtebc(pb3cr, 0x00000000);
mtebc(pb4ap, 0x00000000);
mtebc(pb4cr, 0x00000000);
mtebc(pb5ap, 0x00000000);
mtebc(pb5cr, 0x00000000);
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
@ -186,8 +168,15 @@ int misc_init_r (void)
int checkboard(void)
{
char *s = getenv("serial#");
u8 rev;
u8 val;
printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
rev = *(u8 *)(CFG_CPLD + 0);
val = *(u8 *)(CFG_CPLD + 5) & 0x01;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {
puts(", serial# ");
puts(s);

8
board/mcc200/auto_update.c
View file

@ -121,10 +121,10 @@ struct flash_layout aufl_layout[AU_MAXFILES] = { \
#define I2C_PSOC_KEYPAD_ADDR 0x53
/* keypad mask */
#define KEYPAD_ROW 3
#define KEYPAD_COL 3
#define KEYPAD_MASK_LO ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*4-4)))&0xFF)
#define KEYPAD_MASK_HI ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*4-4)))>>8)
#define KEYPAD_ROW 2
#define KEYPAD_COL 2
#define KEYPAD_MASK_LO ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))&0xFF)
#define KEYPAD_MASK_HI ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))>>8)
/* externals */
extern int fat_register_device(block_dev_desc_t *, int);

11
board/mcc200/mcc200.c
View file

@ -92,8 +92,8 @@ static void sdram_start (int hi_addr)
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
*/
long int initdram (int board_type)
@ -228,10 +228,6 @@ int misc_init_r (void)
{
ulong flash_sup_end, snum;
#ifdef CONFIG_AUTO_UPDATE
/* this has priority over all else */
do_auto_update();
#endif
/*
* Adjust flash start and offset to detected values
*/
@ -294,6 +290,9 @@ int misc_init_r (void)
flash_info[0].sector_count = snum;
}
#ifdef CONFIG_AUTO_UPDATE
do_auto_update();
#endif
return (0);
}

27
board/prodrive/alpr/alpr.c
View file

@ -77,8 +77,12 @@ int board_early_init_f (void)
mtdcr (uicb0tr, 0x00000000); /* */
mtdcr (uicb0vr, 0x00000001); /* */
/* Setup shutdown/SSD empty interrupt as inputs */
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
/* Setup GPIO/IRQ multiplexing */
mtsdr(sdr_pfc0, 0x01a03e00);
mtsdr(sdr_pfc0, 0x01a33e00);
return 0;
}
@ -105,26 +109,11 @@ int last_stage_init(void)
static int board_rev(void)
{
int rev;
u32 pfc0;
/* Setup GPIO14 & 15 as GPIO */
mfsdr(sdr_pfc0, pfc0);
pfc0 |= CFG_GPIO_REV0 | CFG_GPIO_REV1;
mtsdr(sdr_pfc0, pfc0);
/* Setup as input */
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0));
out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0));
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
rev = (in32(GPIO0_IR) >> 16) & 0x3;
/* Setup GPIO14 & 15 as non GPIO again */
mfsdr(sdr_pfc0, pfc0);
pfc0 &= ~(CFG_GPIO_REV0 | CFG_GPIO_REV1);
mtsdr(sdr_pfc0, pfc0);
return rev;
return (in32(GPIO0_IR) >> 16) & 0x3;
}
int checkboard (void)

4
board/prodrive/alpr/nand.c
View file

@ -154,7 +154,7 @@ static int alpr_nand_dev_ready(struct mtd_info *mtd)
return 1;
}
void board_nand_init(struct nand_chip *nand)
int board_nand_init(struct nand_chip *nand)
{
alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE;
@ -169,5 +169,7 @@ void board_nand_init(struct nand_chip *nand)
nand->read_buf = alpr_nand_read_buf;
nand->verify_buf = alpr_nand_verify_buf;
nand->dev_ready = alpr_nand_dev_ready;
return 0;
}
#endif

63
board/prodrive/p3mx/p3mx.c
View file

@ -45,6 +45,7 @@
#include "mpsc.h"
#include "64460.h"
#include "mv_regs.h"
#include "p3mx.h"
DECLARE_GLOBAL_DATA_PTR;
@ -79,6 +80,7 @@ extern flash_info_t flash_info[];
void board_prebootm_init (void);
unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
int display_mem_map (void);
void set_led(int);
/* ------------------------------------------------------------------------- */
@ -246,7 +248,6 @@ int board_early_init_f (void)
* that if it's not at the power-on location, it's where we put
* it last time. (huber)
*/
my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
#ifdef CONFIG_PCI
@ -287,6 +288,8 @@ int board_early_init_f (void)
GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
set_led(LED_RED);
return 0;
}
@ -332,6 +335,7 @@ void after_reloc (ulong dest_addr, gd_t * gd)
/* display_mem_map(); */
/* now, jump to the main U-Boot board init code */
set_led(LED_GREEN);
board_init_r (gd, dest_addr);
/* NOTREACHED */
}
@ -356,15 +360,66 @@ int checkboard (void)
return (0);
}
/* utility functions */
void debug_led (int led, int mode)
void set_led(int col)
{
int tmp;
int on_pin;
int off_pin;
/* Program Mpp[22] as Gpp[22]
* Program Mpp[23] as Gpp[23]
*/
tmp = GTREGREAD(MPP_CONTROL2);
tmp &= 0x00ffffff;
GT_REG_WRITE(MPP_CONTROL2,tmp);
/* Program Gpp[22] and Gpp[23] as output
*/
tmp = GTREGREAD(GPP_IO_CONTROL);
tmp |= 0x00C00000;
GT_REG_WRITE(GPP_IO_CONTROL, tmp);
/* Program Gpp[22] and Gpp[23] as active high
*/
tmp = GTREGREAD(GPP_LEVEL_CONTROL);
tmp &= 0xff3fffff;
GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp);
switch(col) {
default:
case LED_OFF :
on_pin = 0;
off_pin = ((1 << 23) | (1 << 22));
break;
case LED_RED :
on_pin = (1 << 23);
off_pin = (1 << 22);
break;
case LED_GREEN :
on_pin = (1 << 22);
off_pin = (1 << 23);
break;
case LED_ORANGE :
on_pin = ((1 << 23) | (1 << 22));
off_pin = 0;
break;
}
/* Set output Gpp[22] and Gpp[23]
*/
tmp = GTREGREAD(GPP_VALUE);
tmp |= on_pin;
tmp &= ~off_pin;
GT_REG_WRITE(GPP_VALUE, tmp);
}
int display_mem_map (void)
{
int i, j;
int i;
unsigned int base, size, width;
#ifdef CONFIG_PCI
int j;
#endif
/* SDRAM */
printf ("SD (DDR) RAM\n");

4
board/prodrive/p3mx/sdram_init.c
View file

@ -65,7 +65,7 @@ int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
int memory_map_bank (unsigned int bankNo,
unsigned int bankBase, unsigned int bankLength)
{
#ifdef MAP_PCI
#if defined (MAP_PCI) && defined (CONFIG_PCI)
PCI_HOST host;
#endif
@ -80,7 +80,7 @@ int memory_map_bank (unsigned int bankNo,
memoryMapBank (bankNo, bankBase, bankLength);
#ifdef MAP_PCI
#if defined (MAP_PCI) && defined (CONFIG_PCI)
for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
const int features =
PREFETCH_ENABLE |

4
board/prodrive/pdnb3/flash.c
View file

@ -24,6 +24,8 @@
#include <common.h>
#include <asm/arch/ixp425.h>
#if !defined(CFG_FLASH_CFI_DRIVER)
/*
* include common flash code (for esd boards)
*/
@ -83,3 +85,5 @@ unsigned long flash_init(void)
return size;
}
#endif /* CFG_FLASH_CFI_DRIVER */

47
board/sc3/Makefile Normal file
View file

@ -0,0 +1,47 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o sc3nand.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

24
board/sc3/config.mk Normal file
View file

@ -0,0 +1,24 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xFFFC0000

382
board/sc3/init.S Normal file
View file

@ -0,0 +1,382 @@
/*------------------------------------------------------------------------------+
*
* This souce code has been made available to you by EuroDesign
* (www.eurodsn.de). It's based on the original IBM source code, so
* this follows:
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
* copyrights to use it in any way he or she deems fit, including
* copying it, modifying it, compiling it, and redistributing it either
* with or without modifications. No license under IBM patents or
* patent applications is to be implied by the copyright license.
*
* Any user of this software should understand that IBM cannot provide
* technical support for this software and will not be responsible for
* any consequences resulting from the use of this software.
*
* Any person who transfers this source code or any derivative work
* must include the IBM copyright notice, this paragraph, and the
* preceding two paragraphs in the transferred software.
*
* COPYRIGHT I B M CORPORATION 1995
* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
*------------------------------------------------------------------------------- */
#include <config.h>
#include <ppc4xx.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
/**
* ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
*
* IMPORTANT: For pass1 this code must run from cache since you can not
* reliably change a peripheral banks timing register (pbxap) while running
* code from that bank. For ex., since we are running from ROM on bank 0, we
* can NOT execute the code that modifies bank 0 timings from ROM, so
* we run it from cache.
*
* Bank 0 - Boot-Flash
* Bank 1 - NAND-Flash
* Bank 2 - ISA bus
* Bank 3 - Second Flash
* Bank 4 - USB controller
*/
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
/*
* We need the current boot up configuration to set correct
* timings into internal flash and external flash
*/
mfdcr r24,strap /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
0 0 -> 8 bit external ROM
0 1 -> 16 bit internal ROM */
addi r4,0,2
srw r24,r24,r4 /* shift right r24 two positions */
andi. r24,r24,0x06000
/*
* All calculations are based on 33MHz EBC clock.
*
* First, create a "very slow" timing (~250ns) with burst mode enabled
* This is need for the external flash access
*/
lis r25,0x0800
ori r25,r25,0x0280 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280
/*
* Second, create a fast timing:
* 90ns first cycle - 3 clock access
* and 90ns burst cycle, plus 1 clock after the last access
* This is used for the internal access
*/
lis r26,0x8900
ori r26,r26,0x0280 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx
/*
* We can't change settings on CS# if we currently use them.
* -> load a few instructions into cache and run this code from cache
*/
mflr r4 /* save link register */
bl ..getAddr
..getAddr:
mflr r3 /* get address of ..getAddr */
mtlr r4 /* restore link register */
addi r4,0,14 /* set ctr to 10; used to prefetch */
mtctr r4 /* 10 cache lines to fit this function
in cache (gives us 8x10=80 instructions) */
..ebcloop:
icbt r0,r3 /* prefetch cache line for addr in r3 */
addi r3,r3,32 /* move to next cache line */
bdnz ..ebcloop /* continue for 10 cache lines */
/*
* Delay to ensure all accesses to ROM are complete before changing
* bank 0 timings. 200usec should be enough.
* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
*/
lis r3,0x0
ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
mtctr r3
..spinlp:
bdnz ..spinlp /* spin loop */
/*-----------------------------------------------------------------------
* Memory Bank 0 (BOOT-ROM) initialization
* 0xFFEF00000....0xFFFFFFF
* We only have to change the timing. Mapping is ok by boot-strapping
*----------------------------------------------------------------------- */
li r4,pb0ap /* PB0AP=Peripheral Bank 0 Access Parameters */
mtdcr ebccfga,r4
mr r4,r26 /* assume internal fast flash is boot flash */
cmpwi r24,0x2000 /* assumption true? ... */
beq 1f /* ...yes! */
mr r4,r25 /* ...no, use the slow variant */
mr r25,r26 /* use this for the other flash */
1:
mtdcr ebccfgd,r4 /* change timing now */
li r4,pb0cr /* PB0CR=Peripheral Bank 0 Control Register */
mtdcr ebccfga,r4
mfdcr r4,ebccfgd
lis r3,0x0001
ori r3,r3,0x8000 /* allow reads and writes */
or r4,r4,r3
mtdcr ebccfgd,r4
/*-----------------------------------------------------------------------
* Memory Bank 3 (Second-Flash) initialization
* 0xF0000000...0xF01FFFFF -> 2MB
*----------------------------------------------------------------------- */
li r4,pb3ap /* Peripheral Bank 1 Access Parameter */
mtdcr ebccfga,r4
mtdcr ebccfgd,r2 /* change timing */
li r4,pb3cr /* Peripheral Bank 1 Configuration Registers */
mtdcr ebccfga,r4
lis r4,0xF003
ori r4,r4,0x8000
/*
* Consider boot configuration
*/
xori r24,r24,0x2000 /* invert current bus width */
or r4,r4,r24
mtdcr ebccfgd,r4
/*-----------------------------------------------------------------------
* Memory Bank 1 (NAND-Flash) initialization
* 0x77D00000...0x77DFFFFF -> 1MB
* - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
* - the setup time is 0ns
* - the hold time is 15ns
* ->
* - TWT = 0
* - CSN = 0
* - OEN = 0
* - WBN = 0
* - WBF = 0
* - TH = 1
* ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
*----------------------------------------------------------------------- */
li r4,pb1ap /* Peripheral Bank 1 Access Parameter */
mtdcr ebccfga,r4
lis r4,0x0000
ori r4,r4,0x0200
mtdcr ebccfgd,r4
li r4,pb1cr /* Peripheral Bank 1 Configuration Registers */
mtdcr ebccfga,r4
lis r4,0x77D1
ori r4,r4,0x8000
mtdcr ebccfgd,r4
/* USB init (without acceleration) */
#ifndef CONFIG_ISP1161_PRESENT
li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */
mtdcr ebccfga,r4
lis r4,0x0180
ori r4,r4,0x5940
mtdcr ebccfgd,r4
#endif
/*-----------------------------------------------------------------------
* Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
* 0x78000000...0x7BFFFFFF -> 64 MB
* Wir arbeiten bei 33 MHz -> 30ns
*-----------------------------------------------------------------------
A7 (ppc notation) or A24 (standard notation) decides about
the type of access:
A7/A24=0 -> memory cycle
A7/ /A24=1 -> I/O cycle
*/
li r4,pb2ap /* PB2AP=Peripheral Bank 2 Access Parameters */
mtdcr ebccfga,r4
/*
We emulate an ISA access
1. Address active
2. wait 0 EBC clocks -> CSN=0
3. set CS#
4. wait 0 EBC clock -> OEN/WBN=0
5. set OE#/WE#
6. wait 4 clocks (ca. 90ns) and for Ready signal
7. hold for 4 clocks -> TH=4
*/
#if 1
/* faster access to isa-bus */
lis r4,0x0180
ori r4,r4,0x5940
#else
lis r4,0x0100
ori r4,r4,0x0340
#endif
mtdcr ebccfgd,r4
#ifdef IDE_USES_ISA_EMULATION
li r25,pb5ap /* PB5AP=Peripheral Bank 5 Access Parameters */
mtdcr ebccfga,r25
mtdcr ebccfgd,r4
#endif
li r25,pb6ap /* PB6AP=Peripheral Bank 6 Access Parameters */
mtdcr ebccfga,r25
mtdcr ebccfgd,r4
li r25,pb7ap /* PB7AP=Peripheral Bank 7 Access Parameters */
mtdcr ebccfga,r25
mtdcr ebccfgd,r4
li r25,pb2cr /* PB2CR=Peripheral Bank 2 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x780B
ori r4,r4,0xA000
mtdcr ebccfgd,r4
/*
* the other areas are only 1MiB in size
*/
lis r4,0x7401
ori r4,r4,0xA000
li r25,pb6cr /* PB6CR=Peripheral Bank 6 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x7401
ori r4,r4,0xA000
mtdcr ebccfgd,r4
li r25,pb7cr /* PB7CR=Peripheral Bank 7 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x7411
ori r4,r4,0xA000
mtdcr ebccfgd,r4
#ifndef CONFIG_ISP1161_PRESENT
li r25,pb4cr /* PB4CR=Peripheral Bank 4 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x7421
ori r4,r4,0xA000
mtdcr ebccfgd,r4
#endif
#ifdef IDE_USES_ISA_EMULATION
li r25,pb5cr /* PB5CR=Peripheral Bank 5 Configuration Register */
mtdcr ebccfga,r25
lis r4,0x0000
ori r4,r4,0x0000
mtdcr ebccfgd,r4
#endif
/*-----------------------------------------------------------------------
* Memory bank 4: USB controller Philips ISP6111
* 0x77C00000 ... 0x77CFFFFF
*
* The chip is connected to:
* - CPU CS#4
* - CPU IRQ#2
* - CPU DMA 3
*
* Timing:
* - command to first data: 300ns. Software must ensure this timing!
* - Write pulse: 26ns
* - Read pulse: 33ns
* - read cycle time: 150ns
* - write cycle time: 140ns
*
* Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
*
* |- 300ns --|
* |---- 420ns ---|---- 420ns ---| cycle
* CS ############:###____#######:###____#######
* OE ############:####___#######:####___#######
* WE ############:####__########:####__########
*
* ----> 2 clocks RD/WR pulses: 60ns
* ----> CSN: 3 clock, 90ns
* ----> OEN: 1 clocks (read cycle)
* ----> WBN: 1 clocks (write cycle)
* ----> WBE: 2 clocks
* ----> TH: 7 clock, 210ns
* ----> TWT: 7 clocks
*----------------------------------------------------------------------- */
#ifdef CONFIG_ISP1161_PRESENT
li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */
mtdcr ebccfga,r4
lis r4,0x030D
ori r4,r4,0x5E80
mtdcr ebccfgd,r4
li r4,pb4cr /* PB2CR=Peripheral Bank 4 Configuration Register */
mtdcr ebccfga,r4
lis r4,0x77C1
ori r4,r4,0xA000
mtdcr ebccfgd,r4
#endif
#ifndef IDE_USES_ISA_EMULATION
/*-----------------------------------------------------------------------
* Memory Bank 5 used for IDE access
*
* Timings for IDE Interface
*
* SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
* 70 165 30 PIO-Mode 0, [ns]
* 3 6 1 [Cycles] ----> AP=0x040C0200
* 50 125 20 PIO-Mode 1, [ns]
* 2 5 1 [Cycles] ----> AP=0x03080200
* 30 100 15 PIO-Mode 2, [ns]
* 1 4 1 [Cycles] ----> AP=0x02040200
* 30 80 10 PIO-Mode 3, [ns]
* 1 3 1 [Cycles] ----> AP=0x01840200
* 25 70 10 PIO-Mode 4, [ns]
* 1 3 1 [Cycles] ----> AP=0x01840200
*
*----------------------------------------------------------------------- */
li r4,pb5ap
mtdcr ebccfga,r4
lis r4,0x040C
ori r4,r4,0x0200
mtdcr ebccfgd,r4
li r4,pb5cr /* PB2CR=Peripheral Bank 2 Configuration Register */
mtdcr ebccfga,r4
lis r4,0x7A01
ori r4,r4,0xA000
mtdcr ebccfgd,r4
#endif
/*
* External Peripheral Control Register
*/
li r4,epcr
mtdcr ebccfga,r4
lis r4,0xB84E
ori r4,r4,0xF000
mtdcr ebccfgd,r4
/*
* drive POST code
*/
lis r4,0x7900
ori r4,r4,0x0080
li r3,0x0001
stb r3,0(r4) /* 01 -> external bus controller is initialized */
nop /* pass2 DCR errata #8 */
blr

781
board/sc3/sc3.c Normal file
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/*
* (C) Copyright 2007
* Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
*
* (C) Copyright 2003
* Juergen Beisert, EuroDesign embedded technologies, info@eurodsn.de
* Derived from walnut.c
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* $Log:$
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include "sc3.h"
#include <pci.h>
#include <i2c.h>
#include <malloc.h>
#undef writel
#undef writeb
#define writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
/* write only register to configure things in our CPLD */
#define CPLD_CONTROL_1 0x79000102
#define CPLD_VERSION 0x79000103
#define IS_CAMERON ((*(unsigned char *)(CPLD_VERSION)== 0x32) ? 1 : 0)
static struct pci_controller hose={0,};
/************************************************************
* Standard definition
************************************************************/
/* CPC0_CR0 Function ISA bus
- GPIO0
- GPIO1 -> Output: NAND-Command Latch Enable
- GPIO2 -> Output: NAND Address Latch Enable
- GPIO3 -> IRQ input ISA-IRQ #5 (through CPLD)
- GPIO4 -> Output: NAND-Chip Enable
- GPIO5 -> IRQ input ISA-IRQ#7 (through CPLD)
- GPIO6 -> IRQ input ISA-IRQ#9 (through CPLD)
- GPIO7 -> IRQ input ISA-IRQ#10 (through CPLD)
- GPIO8 -> IRQ input ISA-IRQ#11 (through CPLD)
- GPIO9 -> IRQ input ISA-IRQ#12 (through CPLD)
- GPIO10/CS1# -> CS1# NAND ISA-CS#0
- GPIO11/CS2# -> CS2# ISA emulation ISA-CS#1
- GPIO12/CS3# -> CS3# 2nd Flash-Bank ISA-CS#2 or ISA-CS#7
- GPIO13/CS4# -> CS4# USB HC or ISA emulation ISA-CS#3
- GPIO14/CS5# -> CS5# Boosted IDE access ISA-CS#4
- GPIO15/CS6# -> CS6# ISA emulation ISA-CS#5
- GPIO16/CS7# -> CS7# ISA emulation ISA-CS#6
- GPIO17/IRQ0 -> GPIO, in, NAND-Ready/Busy# line ISA-IRQ#3
- GPIO18/IRQ1 -> IRQ input ISA-IRQ#14
- GPIO19/IRQ2 -> IRQ input or USB ISA-IRQ#4
- GPIO20/IRQ3 -> IRQ input PCI-IRQ#D
- GPIO21/IRQ4 -> IRQ input PCI-IRQ#C
- GPIO22/IRQ5 -> IRQ input PCI-IRQ#B
- GPIO23/IRQ6 -> IRQ input PCI-IRQ#A
- GPIO24 -> if GPIO output: 0=JTAG CPLD activ, 1=JTAG CPLD inactiv
*/
/*
| CPLD register: io-space at offset 0x102 (write only)
| 0
| 1
| 2 0=CS#4 USB CS#, 1=ISA or GP bus
| 3
| 4
| 5
| 6 1=enable faster IDE access
| 7
*/
#define USB_CHIP_ENABLE 0x04
#define IDE_BOOSTING 0x40
/* --------------- USB stuff ------------------------------------- */
#ifdef CONFIG_ISP1161_PRESENT
/**
* initUsbHost- Initialize the Philips isp1161 HC part if present
* @cpldConfig: Pointer to value in write only CPLD register
*
* Initialize the USB host controller if present and fills the
* scratch register to inform the driver about used resources
*/
static void initUsbHost (unsigned char *cpldConfig)
{
int i;
unsigned long usbBase;
/*
* Read back where init.S has located the USB chip
*/
mtdcr (0x012, 0x04);
usbBase = mfdcr (0x013);
if (!(usbBase & 0x18000)) /* enabled? */
return;
usbBase &= 0xFFF00000;
/*
* to test for the USB controller enable using of CS#4 and DMA 3 for USB access
*/
writeb (*cpldConfig | USB_CHIP_ENABLE,CPLD_CONTROL_1);
/*
* first check: is the controller assembled?
*/
hcWriteWord (usbBase, 0x5555, HcScratch);
if (hcReadWord (usbBase, HcScratch) == 0x5555) {
hcWriteWord (usbBase, 0xAAAA, HcScratch);
if (hcReadWord (usbBase, HcScratch) == 0xAAAA) {
if ((hcReadWord (usbBase, HcChipID) & 0xFF00) != 0x6100)
return; /* this is not our controller */
/*
* try a software reset. This needs up to 10 seconds (see datasheet)
*/
hcWriteDWord (usbBase, 0x00000001, HcCommandStatus);
for (i = 1000; i > 0; i--) { /* loop up to 10 seconds */
udelay (10);
if (!(hcReadDWord (usbBase, HcCommandStatus) & 0x01))
break;
}
if (!i)
return; /* the controller doesn't responding. Broken? */
/*
* OK. USB controller is ready. Initialize it in such way the later driver
* can us it (without any knowing about specific implementation)
*/
hcWriteDWord (usbBase, 0x00000000, HcControl);
/*
* disable all interrupt sources. Because we
* don't know where we come from (hard reset, cold start, soft reset...)
*/
hcWriteDWord (usbBase, 0x8000007D, HcInterruptDisable);
/*
* our current setup hardware configuration
* - every port power supply can switched indepently
* - every port can signal overcurrent
* - every port is "outside" and the devices are removeable
*/
hcWriteDWord (usbBase, 0x32000902, HcRhDescriptorA);
hcWriteDWord (usbBase, 0x00060000, HcRhDescriptorB);
/*
* don't forget to switch off power supply of each port
* The later running driver can reenable them to find and use
* the (maybe) connected devices.
*
*/
hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus1);
hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus2);
hcWriteWord (usbBase, 0x0428, HcHardwareConfiguration);
hcWriteWord (usbBase, 0x0040, HcDMAConfiguration);
hcWriteWord (usbBase, 0x0000, HcuPInterruptEnable);
hcWriteWord (usbBase, 0xA000 | (0x03 << 8) | 27, HcScratch);
/*
* controller is present and usable
*/
*cpldConfig |= USB_CHIP_ENABLE;
}
}
}
#endif
#if defined(CONFIG_START_IDE)
int board_start_ide(void)
{
if (IS_CAMERON) {
puts ("no IDE on cameron board.\n");
return 0;
}
return 1;
}
#endif
static int sc3_cameron_init (void)
{
/* Set up the Memory Controller for the CAMERON version */
mtebc (pb4ap, 0x01805940);
mtebc (pb4cr, 0x7401a000);
mtebc (pb5ap, 0x01805940);
mtebc (pb5cr, 0x7401a000);
mtebc (pb6ap, 0x0);
mtebc (pb6cr, 0x0);
mtebc (pb7ap, 0x0);
mtebc (pb7cr, 0x0);
return 0;
}
void sc3_read_eeprom (void)
{
uchar i2c_buffer[18];
i2c_read (0x50, 0x03, 1, i2c_buffer, 9);
i2c_buffer[9] = 0;
setenv ("serial#", (char *)i2c_buffer);
/* read mac-address from eeprom */
i2c_read (0x50, 0x11, 1, i2c_buffer, 15);
i2c_buffer[17] = 0;
i2c_buffer[16] = i2c_buffer[14];
i2c_buffer[15] = i2c_buffer[13];
i2c_buffer[14] = ':';
i2c_buffer[13] = i2c_buffer[12];
i2c_buffer[12] = i2c_buffer[11];
i2c_buffer[11] = ':';
i2c_buffer[8] = ':';
i2c_buffer[5] = ':';
i2c_buffer[2] = ':';
setenv ("ethaddr", (char *)i2c_buffer);
}
int board_early_init_f (void)
{
/* write only register to configure things in our CPLD */
unsigned char cpldConfig_1=0x00;
/*-------------------------------------------------------------------------+
| Interrupt controller setup for the SolidCard III CPU card (plus Evaluation board).
|
| Note: IRQ 0 UART 0, active high; level sensitive
| IRQ 1 UART 1, active high; level sensitive
| IRQ 2 IIC, active high; level sensitive
| IRQ 3 Ext. master, rising edge, edge sensitive
| IRQ 4 PCI, active high; level sensitive
| IRQ 5 DMA Channel 0, active high; level sensitive
| IRQ 6 DMA Channel 1, active high; level sensitive
| IRQ 7 DMA Channel 2, active high; level sensitive
| IRQ 8 DMA Channel 3, active high; level sensitive
| IRQ 9 Ethernet Wakeup, active high; level sensitive
| IRQ 10 MAL System Error (SERR), active high; level sensitive
| IRQ 11 MAL Tx End of Buffer, active high; level sensitive
| IRQ 12 MAL Rx End of Buffer, active high; level sensitive
| IRQ 13 MAL Tx Descriptor Error, active high; level sensitive
| IRQ 14 MAL Rx Descriptor Error, active high; level sensitive
| IRQ 15 Ethernet, active high; level sensitive
| IRQ 16 External PCI SERR, active high; level sensitive
| IRQ 17 ECC Correctable Error, active high; level sensitive
| IRQ 18 PCI Power Management, active high; level sensitive
|
| IRQ 19 (EXT IRQ7 405GPr only)
| IRQ 20 (EXT IRQ8 405GPr only)
| IRQ 21 (EXT IRQ9 405GPr only)
| IRQ 22 (EXT IRQ10 405GPr only)
| IRQ 23 (EXT IRQ11 405GPr only)
| IRQ 24 (EXT IRQ12 405GPr only)
|
| IRQ 25 (EXT IRQ 0) NAND-Flash R/B# (raising edge means flash is ready)
| IRQ 26 (EXT IRQ 1) IDE0 interrupt (x86 = IRQ14). Active high (edge sensitive)
| IRQ 27 (EXT IRQ 2) USB controller
| IRQ 28 (EXT IRQ 3) INT D, VGA; active low; level sensitive
| IRQ 29 (EXT IRQ 4) INT C, Ethernet; active low; level sensitive
| IRQ 30 (EXT IRQ 5) INT B, PC104+ SLOT; active low; level sensitive
| IRQ 31 (EXT IRQ 6) INT A, PC104+ SLOT; active low; level sensitive
|
| Direct Memory Access Controller Signal Polarities
| DRQ0 active high (like ISA)
| ACK0 active low (like ISA)
| EOT0 active high (like ISA)
| DRQ1 active high (like ISA)
| ACK1 active low (like ISA)
| EOT1 active high (like ISA)
| DRQ2 active high (like ISA)
| ACK2 active low (like ISA)
| EOT2 active high (like ISA)
| DRQ3 active high (like ISA)
| ACK3 active low (like ISA)
| EOT3 active high (like ISA)
|
+-------------------------------------------------------------------------*/
writeb (cpldConfig_1, CPLD_CONTROL_1); /* disable everything in CPLD */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
if (IS_CAMERON) {
sc3_cameron_init();
mtdcr (0x0B6, 0x18000000);
mtdcr (uicpr, 0xFFFFFFF0);
mtdcr (uictr, 0x10001030);
} else {
mtdcr (0x0B6, 0x0000000);
mtdcr (uicpr, 0xFFFFFFE0);
mtdcr (uictr, 0x10000020);
}
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
/* setup other implementation specific details */
mtdcr (ecr, 0x60606000);
mtdcr (cntrl1, 0x000042C0);
if (IS_CAMERON) {
mtdcr (cntrl0, 0x01380000);
/* Setup the GPIOs */
writel (0x08008000, 0xEF600700); /* Output states */
writel (0x00000000, 0xEF600718); /* Open Drain control */
writel (0x68098000, 0xEF600704); /* Output control */
} else {
mtdcr (cntrl0,0x00080000);
/* Setup the GPIOs */
writel (0x08000000, 0xEF600700); /* Output states */
writel (0x14000000, 0xEF600718); /* Open Drain control */
writel (0x7C000000, 0xEF600704); /* Output control */
}
/* Code decompression disabled */
mtdcr (kiar, kconf);
mtdcr (kidr, 0x2B);
/* CPC0_ER: enable sleep mode of (currently) unused components */
/* CPC0_FR: force unused components into sleep mode */
mtdcr (cpmer, 0x3F800000);
mtdcr (cpmfr, 0x14000000);
/* set PLB priority */
mtdcr (0x87, 0x08000000);
/* --------------- DMA stuff ------------------------------------- */
mtdcr (0x126, 0x49200000);
#ifndef IDE_USES_ISA_EMULATION
cpldConfig_1 |= IDE_BOOSTING; /* enable faster IDE */
/* cpldConfig |= 0x01; */ /* enable 8.33MHz output, if *not* present on your baseboard */
writeb (cpldConfig_1, CPLD_CONTROL_1);
#endif
#ifdef CONFIG_ISP1161_PRESENT
initUsbHost (&cpldConfig_1);
writeb (cpldConfig_1, CPLD_CONTROL_1);
#endif
/* FIXME: for what must we do this */
*(unsigned long *)0x79000080 = 0x0001;
return(0);
}
int misc_init_r (void)
{
char *s1;
int i, xilinx_val;
volatile char *xilinx_adr;
xilinx_adr = (char *)0x79000102;
*xilinx_adr = 0x00;
/* customer settings ***************************************** */
/*
s1 = getenv ("function");
if (s1) {
if (!strcmp (s1, "Rosho")) {
printf ("function 'Rosho' activated\n");
*xilinx_adr = 0x40;
}
else {
printf (">>>>>>>>>> function %s not recognized\n",s1);
}
}
*/
/* individual settings ***************************************** */
if ((s1 = getenv ("xilinx"))) {
i=0;
xilinx_val = 0;
while (i < 3 && s1[i]) {
if (s1[i] >= '0' && s1[i] <= '9')
xilinx_val = (xilinx_val << 4) + s1[i] - '0';
else
if (s1[i] >= 'A' && s1[i] <= 'F')
xilinx_val = (xilinx_val << 4) + s1[i] - 'A' + 10;
else
if (s1[i] >= 'a' && s1[i] <= 'f')
xilinx_val = (xilinx_val << 4) + s1[i] - 'a' + 10;
else {
xilinx_val = -1;
break;
}
i++;
}
if (xilinx_val >= 0 && xilinx_val <=255 && i < 3) {
printf ("Xilinx: set to %s\n", s1);
*xilinx_adr = (unsigned char) xilinx_val;
} else
printf ("Xilinx: rejected value %s\n", s1);
}
return 0;
}
/* -------------------------------------------------------------------------
* printCSConfig
*
* Print some informations about chips select configurations
* Only used while debugging.
*
* Params:
* - No. of CS pin
* - AP of this CS
* - CR of this CS
*
* Returns
* nothing
------------------------------------------------------------------------- */
#ifdef SC3_DEBUGOUT
static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
{
const char *bsize[4] = {"8","16","32","?"};
const unsigned char banks[8] = {1, 2, 4, 8, 16, 32, 64, 128};
const char *bankaccess[4] = {"disabled", "RO", "WO", "RW"};
#define CYCLE 30 /* time of one clock (based on 33MHz) */
printf("\nCS#%d",reg);
if (!(cr & 0x00018000))
puts(" unused");
else {
if (((cr&0xFFF00000U) & ((banks[(cr & 0x000E0000) >> 17]-1) << 20)))
puts(" Address is not multiple of bank size!");
printf("\n -%s bit device",
bsize[(cr & 0x00006000) >> 13]);
printf(" at 0x%08lX", cr & 0xFFF00000U);
printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]);
printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]);
if (ap & 0x80000000) {
printf("\n -Burst device (%luns/%luns)",
(((ap & 0x7C000000) >> 26) + 1) * CYCLE,
(((ap & 0x03800000) >> 23) + 1) * CYCLE);
} else {
printf("\n -Non burst device, active cycle %luns",
(((ap & 0x7F800000) >> 23) + 1) * CYCLE);
printf("\n -Address setup %luns",
((ap & 0xC0000) >> 18) * CYCLE);
printf("\n -CS active to RD %luns/WR %luns",
((ap & 0x30000) >> 16) * CYCLE,
((ap & 0xC000) >> 14) * CYCLE);
printf("\n -WR to CS inactive %luns",
((ap & 0x3000) >> 12) * CYCLE);
printf("\n -Hold after access %luns",
((ap & 0xE00) >> 9) * CYCLE);
printf("\n -Ready is %sabled",
ap & 0x100 ? "en" : "dis");
}
}
}
#endif
#ifdef SC3_DEBUGOUT
static unsigned int ap[] = {pb0ap, pb1ap, pb2ap, pb3ap, pb4ap,
pb5ap, pb6ap, pb7ap};
static unsigned int cr[] = {pb0cr, pb1cr, pb2cr, pb3cr, pb4cr,
pb5cr, pb6cr, pb7cr};
static int show_reg (int nr)
{
unsigned long ul1, ul2;
mtdcr (ebccfga, ap[nr]);
ul1 = mfdcr (ebccfgd);
mtdcr (ebccfga, cr[nr]);
ul2 = mfdcr(ebccfgd);
printCSConfig(nr, ul1, ul2);
return 0;
}
#endif
int checkboard (void)
{
#ifdef SC3_DEBUGOUT
unsigned long ul1;
int i;
for (i = 0; i < 8; i++) {
show_reg (i);
}
mtdcr (ebccfga, epcr);
ul1 = mfdcr (ebccfgd);
puts ("\nGeneral configuration:\n");
if (ul1 & 0x80000000)
printf(" -External Bus is always driven\n");
if (ul1 & 0x400000)
printf(" -CS signals are always driven\n");
if (ul1 & 0x20000)
printf(" -PowerDown after %lu clocks\n",
(ul1 & 0x1F000) >> 7);
switch (ul1 & 0xC0000)
{
case 0xC0000:
printf(" -No external master present\n");
break;
case 0x00000:
printf(" -8 bit external master present\n");
break;
case 0x40000:
printf(" -16 bit external master present\n");
break;
case 0x80000:
printf(" -32 bit external master present\n");
break;
}
switch (ul1 & 0x300000)
{
case 0x300000:
printf(" -Prefetch: Illegal setting!\n");
break;
case 0x000000:
printf(" -1 doubleword prefetch\n");
break;
case 0x100000:
printf(" -2 doublewords prefetch\n");
break;
case 0x200000:
printf(" -4 doublewords prefetch\n");
break;
}
putc ('\n');
#endif
printf("Board: SolidCard III %s %s version.\n",
(IS_CAMERON ? "Cameron" : "Eurodesign"), CONFIG_SC3_VERSION);
return 0;
}
static int printSDRAMConfig(char reg, unsigned long cr)
{
const int bisize[8]={4, 8, 16, 32, 64, 128, 256, 0};
#ifdef SC3_DEBUGOUT
const char *basize[8]=
{"4", "8", "16", "32", "64", "128", "256", "Reserved"};
printf("SDRAM bank %d",reg);
if (!(cr & 0x01))
puts(" disabled\n");
else {
printf(" at 0x%08lX, size %s MB",cr & 0xFFC00000,basize[(cr&0xE0000)>>17]);
printf(" mode %lu\n",((cr & 0xE000)>>13)+1);
}
#endif
if (cr & 0x01)
return(bisize[(cr & 0xE0000) >> 17]);
return 0;
}
#ifdef SC3_DEBUGOUT
static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf};
#endif
long int initdram (int board_type)
{
unsigned int mems=0;
unsigned long ul1;
#ifdef SC3_DEBUGOUT
unsigned long ul2;
int i;
puts("\nSDRAM configuration:\n");
mtdcr (memcfga, mem_mcopt1);
ul1 = mfdcr(memcfgd);
if (!(ul1 & 0x80000000)) {
puts(" Controller disabled\n");
return 0;
}
for (i = 0; i < 4; i++) {
mtdcr (memcfga, mbcf[i]);
ul1 = mfdcr (memcfgd);
mems += printSDRAMConfig (i, ul1);
}
mtdcr (memcfga, mem_sdtr1);
ul1 = mfdcr(memcfgd);
printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
printf (" -R/W to Precharge %lu (CTP)\n", ((ul1 & 0x30000) >> 16) + 1);
printf (" -Leadoff %lu\n", ((ul1 & 0xC000) >> 14) + 1);
printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
puts ("Misc:\n");
mtdcr (memcfga, mem_rtr);
ul1 = mfdcr(memcfgd);
printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
mtdcr(memcfga,mem_pmit);
ul2=mfdcr(memcfgd);
mtdcr(memcfga,mem_mcopt1);
ul1=mfdcr(memcfgd);
if (ul1 & 0x20000000)
printf(" -Power Down after: %luns\n",
((ul2 & 0xFFC00000) >> 22) * 7);
else
puts(" -Power Down disabled\n");
if (ul1 & 0x40000000)
printf(" -Self refresh feature active\n");
else
puts(" -Self refresh disabled\n");
if (ul1 & 0x10000000)
puts(" -ECC enabled\n");
else
puts(" -ECC disabled\n");
if (ul1 & 0x8000000)
puts(" -Using registered SDRAM\n");
if (!(ul1 & 0x6000000))
puts(" -Using 32 bit data width\n");
else
puts(" -Illegal data width!\n");
if (ul1 & 0x400000)
puts(" -ECC drivers inactive\n");
else
puts(" -ECC drivers active\n");
if (ul1 & 0x200000)
puts(" -Memory lines always active outputs\n");
else
puts(" -Memory lines only at write cycles active outputs\n");
mtdcr (memcfga, mem_status);
ul1 = mfdcr (memcfgd);
if (ul1 & 0x80000000)
puts(" -SDRAM Controller ready\n");
else
puts(" -SDRAM Controller not ready\n");
if (ul1 & 0x4000000)
puts(" -SDRAM in self refresh mode!\n");
return (mems * 1024 * 1024);
#else
mtdcr (memcfga, mem_mb0cf);
ul1 = mfdcr (memcfgd);
mems = printSDRAMConfig (0, ul1);
mtdcr (memcfga, mem_mb1cf);
ul1 = mfdcr (memcfgd);
mems += printSDRAMConfig (1, ul1);
mtdcr (memcfga, mem_mb2cf);
ul1 = mfdcr(memcfgd);
mems += printSDRAMConfig (2, ul1);
mtdcr (memcfga, mem_mb3cf);
ul1 = mfdcr(memcfgd);
mems += printSDRAMConfig (3, ul1);
return (mems * 1024 * 1024);
#endif
}
static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
{
/*-------------------------------------------------------------------------+
| ,-. ,-. ,-. ,-. ,-.
| INTD# ----|B|-----|P|-. ,-|P|-. ,-| |-. ,-|G|
| |R| |C| \ / |C| \ / |E| \ / |r|
| INTC# ----|I|-----|1|-. `/---|1|-. `/---|t|-. `/---|a|
| |D| |0| \/ |0| \/ |h| \/ |f|
| INTB# ----|G|-----|4|-./`----|4|-./`----|e|-./`----|i|
| |E| |+| /\ |+| /\ |r| /\ |k|
| INTA# ----| |-----| |- `----| |- `----| |- `----| |
| `-' `-' `-' `-' `-'
| Slot 0 10 11 12 13
| REQ# 0 1 2 *
| GNT# 0 1 2 *
+-------------------------------------------------------------------------*/
unsigned char int_line = 0xff;
switch (PCI_DEV(dev)) {
case 10:
int_line = 31; /* INT A */
POST_OUT(0x42);
break;
case 11:
int_line = 30; /* INT B */
POST_OUT(0x43);
break;
case 12:
int_line = 29; /* INT C */
POST_OUT(0x44);
break;
case 13:
int_line = 28; /* INT D */
POST_OUT(0x45);
break;
}
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
}
extern void pci_405gp_init(struct pci_controller *hose);
extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
extern void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,struct pci_config_table *entry);
/*
* The following table is used when there is a special need to setup a PCI device.
* For every PCI device found in this table is called the given init function with given
* parameters. So never let all IDs at PCI_ANY_ID. In this case any found device gets the same
* parameters!
*
*/
static struct pci_config_table pci_solidcard3_config_table[] =
{
/* Host to PCI Bridge device (405GP) */
{
vendor: 0x1014,
device: 0x0156,
class: PCI_CLASS_BRIDGE_HOST,
bus: 0,
dev: 0,
func: 0,
config_device: pci_405gp_setup_bridge
},
{ }
};
/*-------------------------------------------------------------------------+
| pci_init_board (Called from pci_init() in drivers/pci.c)
|
| Init the PCI part of the SolidCard III
|
| Params:
* - Pointer to current PCI hose
* - Current Device
*
* Returns
* nothing
+-------------------------------------------------------------------------*/
void pci_init_board(void)
{
POST_OUT(0x41);
/*
* we want the ptrs to RAM not flash (ie don't use init list)
*/
hose.fixup_irq = pci_solidcard3_fixup_irq;
hose.config_table = pci_solidcard3_config_table;
pci_405gp_init(&hose);
}

117
board/sc3/sc3.h Normal file
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@ -0,0 +1,117 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/**
* hcWriteWord - write a 16 bit value into the USB controller
* @base: base address to access the chip registers
* @value: 16 bit value to write into register @offset
* @offset: register to write the @value into
*
*/
static void inline hcWriteWord (unsigned long base, unsigned int value,
unsigned int offset)
{
out_le16 ((volatile u16*)(base + 2), offset | 0x80);
out_le16 ((volatile u16*)base, value);
}
/**
* hcWriteDWord - write a 32 bit value into the USB controller
* @base: base address to access the chip registers
* @value: 32 bit value to write into register @offset
* @offset: register to write the @value into
*
*/
static void inline hcWriteDWord (unsigned long base, unsigned long value,
unsigned int offset)
{
out_le16 ((volatile u16*)(base + 2), offset | 0x80);
out_le16 ((volatile u16*)base, value);
out_le16 ((volatile u16*)base, value >> 16);
}
/**
* hcReadWord - read a 16 bit value from the USB controller
* @base: base address to access the chip registers
* @offset: register to read from
*
* Returns the readed register value
*/
static unsigned int inline hcReadWord (unsigned long base, unsigned int offset)
{
out_le16 ((volatile u16*)(base + 2), offset);
return (in_le16 ((volatile u16*)base));
}
/**
* hcReadDWord - read a 32 bit value from the USB controller
* @base: base address to access the chip registers
* @offset: register to read from
*
* Returns the readed register value
*/
static unsigned long inline hcReadDWord (unsigned long base, unsigned int offset)
{
unsigned long val, val16;
out_le16 ((volatile u16*)(base + 2), offset);
val = in_le16((volatile u16*)base);
val16 = in_le16((volatile u16*)base);
return (val | (val16 << 16));
}
/* control and status registers isp1161 */
#define HcRevision 0x00
#define HcControl 0x01
#define HcCommandStatus 0x02
#define HcInterruptStatus 0x03
#define HcInterruptEnable 0x04
#define HcInterruptDisable 0x05
#define HcFmInterval 0x0D
#define HcFmRemaining 0x0E
#define HcFmNumber 0x0F
#define HcLSThreshold 0x11
#define HcRhDescriptorA 0x12
#define HcRhDescriptorB 0x13
#define HcRhStatus 0x14
#define HcRhPortStatus1 0x15
#define HcRhPortStatus2 0x16
#define HcHardwareConfiguration 0x20
#define HcDMAConfiguration 0x21
#define HcTransferCounter 0x22
#define HcuPInterrupt 0x24
#define HcuPInterruptEnable 0x25
#define HcChipID 0x27
#define HcScratch 0x28
#define HcSoftwareReset 0x29
#define HcITLBufferLength 0x2A
#define HcATLBufferLength 0x2B
#define HcBufferStatus 0x2C
#define HcReadBackITL0Length 0x2D
#define HcReadBackITL1Length 0x2E
#define HcITLBufferPort 0x40
#define HcATLBufferPort 0x41

94
board/sc3/sc3nand.c Normal file
View file

@ -0,0 +1,94 @@
/*
* (C) Copyright 2007
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <nand.h>
#include <asm/processor.h>
#define readb(addr) *(volatile u_char *)(addr)
#define readl(addr) *(volatile u_long *)(addr)
#define writeb(d,addr) *(volatile u_char *)(addr) = (d)
#define SC3_NAND_ALE 29 /* GPIO PIN 3 */
#define SC3_NAND_CLE 30 /* GPIO PIN 2 */
#define SC3_NAND_CE 27 /* GPIO PIN 5 */
static void *sc3_io_base;
static void *sc3_control_base = (void *)0xEF600700;
static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd)
{
switch (cmd) {
case NAND_CTL_SETCLE:
set_bit (SC3_NAND_CLE, sc3_control_base);
break;
case NAND_CTL_CLRCLE:
clear_bit (SC3_NAND_CLE, sc3_control_base);
break;
case NAND_CTL_SETALE:
set_bit (SC3_NAND_ALE, sc3_control_base);
break;
case NAND_CTL_CLRALE:
clear_bit (SC3_NAND_ALE, sc3_control_base);
break;
case NAND_CTL_SETNCE:
set_bit (SC3_NAND_CE, sc3_control_base);
break;
case NAND_CTL_CLRNCE:
clear_bit (SC3_NAND_CE, sc3_control_base);
break;
}
}
static int sc3_nand_dev_ready(struct mtd_info *mtd)
{
if (!(readl(sc3_control_base + 0x1C) & 0x4000))
return 0;
return 1;
}
static void sc3_select_chip(struct mtd_info *mtd, int chip)
{
clear_bit (SC3_NAND_CE, sc3_control_base);
}
int board_nand_init(struct nand_chip *nand)
{
nand->eccmode = NAND_ECC_SOFT;
sc3_io_base = (void *) CFG_NAND_BASE;
/* Set address of NAND IO lines (Using Linear Data Access Region) */
nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
nand->IO_ADDR_W = (void __iomem *) sc3_io_base;
/* Reference hardware control function */
nand->hwcontrol = sc3_nand_hwcontrol;
nand->dev_ready = sc3_nand_dev_ready;
nand->select_chip = sc3_select_chip;
return 0;
}
#endif

150
board/sc3/u-boot.lds Normal file
View file

@ -0,0 +1,150 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/sc3/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

2
board/spc1920/Makefile
View file

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o
COBJS = $(BOARD).o hpi.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

603
board/spc1920/hpi.c Normal file
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@ -0,0 +1,603 @@
/*
* (C) Copyright 2006
* Markus Klotzbuecher, DENX Software Engineering, mk@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Host Port Interface (HPI)
*/
/* debug levels:
* 0 : errors
* 1 : usefull info
* 2 : lots of info
* 3 : noisy
*/
#define DEBUG 0
#include <config.h>
#include <common.h>
#include <mpc8xx.h>
#include "pld.h"
#include "hpi.h"
#define _NOT_USED_ 0xFFFFFFFF
/* original table:
* - inserted loops to achieve long CS low and high Periods (~217ns)
* - move cs high 2/4 to the right
*/
const uint dsp_table_slow[] =
{
/* single read (offset 0x00 in upm ram) */
0x8fffdc04, 0x0fffdc84, 0x0fffdc84, 0x0fffdc00,
0x3fffdc04, 0xffffdc84, 0xffffdc84, 0xffffdc05,
/* burst read (offset 0x08 in upm ram) */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* single write (offset 0x18 in upm ram) */
0x8fffd004, 0x0fffd084, 0x0fffd084, 0x3fffd000,
0xffffd084, 0xffffd084, 0xffffd005, _NOT_USED_,
/* burst write (offset 0x20 in upm ram) */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* refresh (offset 0x30 in upm ram) */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* exception (offset 0x3C in upm ram) */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* dsp hpi upm ram table
* works fine for noninc access, failes on incremental.
* - removed first word
*/
const uint dsp_table_fast[] =
{
/* single read (offset 0x00 in upm ram) */
0x8fffdc04, 0x0fffdc04, 0x0fffdc00, 0x3fffdc04,
0xffffdc05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* burst read (offset 0x08 in upm ram) */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* single write (offset 0x18 in upm ram) */
0x8fffd004, 0x0fffd004, 0x3fffd000, 0xffffd005,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* burst write (offset 0x20 in upm ram) */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* refresh (offset 0x30 in upm ram) */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* exception (offset 0x3C in upm ram) */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
};
#ifdef CONFIG_SPC1920_HPI_TEST
#undef HPI_TEST_OSZI
#define HPI_TEST_CHUNKSIZE 0x1000
#define HPI_TEST_PATTERN 0x00000000
#define HPI_TEST_START 0x0
#define HPI_TEST_END 0x30000
#define TINY_AUTOINC_DATA_SIZE 16 /* 32bit words */
#define TINY_AUTOINC_BASE_ADDR 0x0
static int hpi_activate(void);
static void hpi_inactivate(void);
static void dsp_reset(void);
static int hpi_write_inc(u32 addr, u32 *data, u32 count);
static int hpi_read_inc(u32 addr, u32 *buf, u32 count);
static int hpi_write_noinc(u32 addr, u32 data);
static u32 hpi_read_noinc(u32 addr);
int hpi_test(void);
static int hpi_write_addr_test(u32 addr);
static int hpi_read_write_test(u32 addr, u32 data);
static int hpi_tiny_autoinc_test(void);
#endif /* CONFIG_SPC1920_HPI_TEST */
/* init the host port interface on UPMA */
int hpi_init(void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE;
upmconfig(UPMA, (uint *)dsp_table_slow, sizeof(dsp_table_slow)/sizeof(uint));
udelay(100);
memctl->memc_mamr = CFG_MAMR;
memctl->memc_or3 = CFG_OR3;
memctl->memc_br3 = CFG_BR3;
/* reset dsp */
dsp_reset();
/* activate hpi switch*/
pld->dsp_hpi_on = 0x1;
udelay(100);
return 0;
}
#ifdef CONFIG_SPC1920_HPI_TEST
/* activate the Host Port interface */
static int hpi_activate(void)
{
volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE;
/* turn on hpi */
pld->dsp_hpi_on = 0x1;
udelay(5);
/* turn on the power EN_DSP_POWER high*/
/* currently always on TBD */
/* setup hpi control register */
HPI_HPIC_1 = (u16) 0x0008;
HPI_HPIC_2 = (u16) 0x0008;
udelay(100);
return 0;
}
/* turn off the host port interface */
static void hpi_inactivate(void)
{
volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE;
/* deactivate hpi */
pld->dsp_hpi_on = 0x0;
/* reset the dsp */
/* pld->dsp_reset = 0x0; */
/* turn off the power EN_DSP_POWER# high*/
/* currently always on TBD */
}
/* reset the DSP */
static void dsp_reset(void)
{
volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE;
pld->dsp_reset = 0x1;
pld->dsp_hpi_on = 0x0;
udelay(300000);
pld->dsp_reset = 0x0;
pld->dsp_hpi_on = 0x1;
}
/* write using autoinc (count is number of 32bit words) */
static int hpi_write_inc(u32 addr, u32 *data, u32 count)
{
int i;
u16 addr1, addr2;
addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
addr2 = (u16) (addr & 0xffff);
/* write address */
HPI_HPIA_1 = addr1;
HPI_HPIA_2 = addr2;
debugX(4, "writing from data=0x%x to 0x%x\n", data, (data+count));
for(i=0; i<count; i++) {
HPI_HPID_INC_1 = (u16) ((data[i] >> 16) & 0xffff);
HPI_HPID_INC_2 = (u16) (data[i] & 0xffff);
debugX(4, "hpi_write_inc: data1=0x%x, data2=0x%x\n",
(u16) ((data[i] >> 16) & 0xffff),
(u16) (data[i] & 0xffff));
}
#if 0
while(data_ptr < (u16*) (data + count)) {
HPI_HPID_INC_1 = *(data_ptr++);
HPI_HPID_INC_2 = *(data_ptr++);
}
#endif
/* return number of bytes written */
return count;
}
/*
* read using autoinc (count is number of 32bit words)
*/
static int hpi_read_inc(u32 addr, u32 *buf, u32 count)
{
int i;
u16 addr1, addr2, data1, data2;
addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
addr2 = (u16) (addr & 0xffff);
/* write address */
HPI_HPIA_1 = addr1;
HPI_HPIA_2 = addr2;
for(i=0; i<count; i++) {
data1 = HPI_HPID_INC_1;
data2 = HPI_HPID_INC_2;
debugX(4, "hpi_read_inc: data1=0x%x, data2=0x%x\n", data1, data2);
buf[i] = (((u32) data1) << 16) | (data2 & 0xffff);
}
#if 0
while(buf_ptr < (u16*) (buf + count)) {
*(buf_ptr++) = HPI_HPID_INC_1;
*(buf_ptr++) = HPI_HPID_INC_2;
}
#endif
/* return number of bytes read */
return count;
}
/* write to non- auto inc regs */
static int hpi_write_noinc(u32 addr, u32 data)
{
u16 addr1, addr2, data1, data2;
addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
addr2 = (u16) (addr & 0xffff);
/* printf("hpi_write_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */
HPI_HPIA_1 = addr1;
HPI_HPIA_2 = addr2;
data1 = (u16) ((data >> 16) & 0xffff);
data2 = (u16) (data & 0xffff);
/* printf("hpi_write_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */
HPI_HPID_NOINC_1 = data1;
HPI_HPID_NOINC_2 = data2;
return 0;
}
/* read from non- auto inc regs */
static u32 hpi_read_noinc(u32 addr)
{
u16 addr1, addr2, data1, data2;
u32 ret;
addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
addr2 = (u16) (addr & 0xffff);
HPI_HPIA_1 = addr1;
HPI_HPIA_2 = addr2;
/* printf("hpi_read_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */
data1 = HPI_HPID_NOINC_1;
data2 = HPI_HPID_NOINC_2;
/* printf("hpi_read_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */
ret = (((u32) data1) << 16) | (data2 & 0xffff);
return ret;
}
/*
* Host Port Interface Tests
*/
#ifndef HPI_TEST_OSZI
/* main test function */
int hpi_test(void)
{
int err = 0;
u32 i, ii, pattern, tmp;
pattern = HPI_TEST_PATTERN;
u32 test_data[HPI_TEST_CHUNKSIZE];
u32 read_data[HPI_TEST_CHUNKSIZE];
debugX(2, "hpi_test: activating hpi...");
hpi_activate();
debugX(2, "OK.\n");
#if 0
/* Dump the first 1024 bytes
*
*/
for(i=0; i<1024; i+=4) {
if(i%16==0)
printf("\n0x%08x: ", i);
printf("0x%08x ", hpi_read_noinc(i));
}
#endif
/* HPIA read-write test
*
*/
debugX(1, "hpi_test: starting HPIA read-write tests...\n");
err |= hpi_write_addr_test(0xdeadc0de);
err |= hpi_write_addr_test(0xbeefd00d);
err |= hpi_write_addr_test(0xabcd1234);
err |= hpi_write_addr_test(0xaaaaaaaa);
if(err) {
debugX(1, "hpi_test: HPIA read-write tests: *** FAILED ***\n");
return -1;
}
debugX(1, "hpi_test: HPIA read-write tests: OK\n");
/* read write test using nonincremental data regs
*
*/
debugX(1, "hpi_test: starting nonincremental tests...\n");
for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) {
err |= hpi_read_write_test(i, pattern);
/* stolen from cmd_mem.c */
if(pattern & 0x80000000) {
pattern = -pattern; /* complement & increment */
} else {
pattern = ~pattern;
}
err |= hpi_read_write_test(i, pattern);
if(err) {
debugX(1, "hpi_test: nonincremental tests *** FAILED ***\n");
return -1;
}
}
debugX(1, "hpi_test: nonincremental test OK\n");
/* read write a chunk of data using nonincremental data regs
*
*/
debugX(1, "hpi_test: starting nonincremental chunk tests...\n");
pattern = HPI_TEST_PATTERN;
for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) {
hpi_write_noinc(i, pattern);
/* stolen from cmd_mem.c */
if(pattern & 0x80000000) {
pattern = -pattern; /* complement & increment */
} else {
pattern = ~pattern;
}
}
pattern = HPI_TEST_PATTERN;
for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) {
tmp = hpi_read_noinc(i);
if(tmp != pattern) {
debugX(1, "hpi_test: noninc chunk test *** FAILED *** @ 0x%x, written=0x%x, read=0x%x\n", i, pattern, tmp);
err = -1;
}
/* stolen from cmd_mem.c */
if(pattern & 0x80000000) {
pattern = -pattern; /* complement & increment */
} else {
pattern = ~pattern;
}
}
if(err)
return -1;
debugX(1, "hpi_test: nonincremental chunk test OK\n");
#ifdef DO_TINY_TEST
/* small verbose test using autoinc and nonautoinc to compare
*
*/
debugX(1, "hpi_test: tiny_autoinc_test...\n");
hpi_tiny_autoinc_test();
debugX(1, "hpi_test: tiny_autoinc_test done\n");
#endif /* DO_TINY_TEST */
/* $%& write a chunk of data using the autoincremental regs
*
*/
debugX(1, "hpi_test: starting autoinc test %d chunks with 0x%x bytes...\n",
((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE),
HPI_TEST_CHUNKSIZE);
for(i=HPI_TEST_START;
i < ((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE);
i++) {
/* generate the pattern data */
debugX(3, "generating pattern data: ");
for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) {
debugX(3, "0x%x ", pattern);
test_data[ii] = pattern;
read_data[ii] = 0x0; /* zero to be sure */
/* stolen from cmd_mem.c */
if(pattern & 0x80000000) {
pattern = -pattern; /* complement & increment */
} else {
pattern = ~pattern;
}
}
debugX(3, "done\n");
debugX(2, "Writing autoinc data @ 0x%x\n", i);
hpi_write_inc(i, test_data, HPI_TEST_CHUNKSIZE);
debugX(2, "Reading autoinc data @ 0x%x\n", i);
hpi_read_inc(i, read_data, HPI_TEST_CHUNKSIZE);
/* compare */
for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) {
debugX(3, "hpi_test_autoinc: @ 0x%x, written=0x%x, read=0x%x", i+ii, test_data[ii], read_data[ii]);
if(read_data[ii] != test_data[ii]) {
debugX(0, "hpi_test: autoinc test @ 0x%x, written=0x%x, read=0x%x *** FAILED ***\n", i+ii, test_data[ii], read_data[ii]);
return -1;
}
}
}
debugX(1, "hpi_test: autoinc test OK\n");
return 0;
}
#else /* HPI_TEST_OSZI */
int hpi_test(void)
{
int i;
u32 read_data[TINY_AUTOINC_DATA_SIZE];
unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = {
0x11112222, 0x33334444, 0x55556666, 0x77778888,
0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111,
0x00010002, 0x00030004, 0x00050006, 0x00070008,
0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001
};
debugX(0, "hpi_test: activating hpi...");
hpi_activate();
debugX(0, "OK.\n");
while(1) {
led9(1);
debugX(0, " writing to autoinc...\n");
hpi_write_inc(TINY_AUTOINC_BASE_ADDR,
dummy_data, TINY_AUTOINC_DATA_SIZE);
debugX(0, " reading from autoinc...\n");
hpi_read_inc(TINY_AUTOINC_BASE_ADDR,
read_data, TINY_AUTOINC_DATA_SIZE);
for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) {
debugX(0, " written=0x%x, read(inc)=0x%x\n",
dummy_data[i], read_data[i]);
}
led9(0);
udelay(2000000);
}
return 0;
}
#endif
/* test if Host Port Address Register can be written correctly */
static int hpi_write_addr_test(u32 addr)
{
u32 read_back;
/* write address */
HPI_HPIA_1 = ((u16) (addr >> 16)); /* First HW is most significant */
HPI_HPIA_2 = ((u16) addr);
read_back = (((u32) HPI_HPIA_1)<<16) | ((u32) HPI_HPIA_2);
if(read_back == addr) {
debugX(2, " hpi_write_addr_test OK: written=0x%x, read=0x%x\n",
addr, read_back);
return 0;
} else {
debugX(0, " hpi_write_addr_test *** FAILED ***: written=0x%x, read=0x%x\n",
addr, read_back);
return -1;
}
return 0;
}
/* test if a simple read/write sequence succeeds */
static int hpi_read_write_test(u32 addr, u32 data)
{
u32 read_back;
hpi_write_noinc(addr, data);
read_back = hpi_read_noinc(addr);
if(read_back == data) {
debugX(2, " hpi_read_write_test: OK, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back);
return 0;
} else {
debugX(0, " hpi_read_write_test: *** FAILED ***, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back);
return -1;
}
return 0;
}
static int hpi_tiny_autoinc_test(void)
{
int i;
u32 read_data[TINY_AUTOINC_DATA_SIZE];
u32 read_data_noinc[TINY_AUTOINC_DATA_SIZE];
unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = {
0x11112222, 0x33334444, 0x55556666, 0x77778888,
0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111,
0x00010002, 0x00030004, 0x00050006, 0x00070008,
0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001
};
printf(" writing to autoinc...\n");
hpi_write_inc(TINY_AUTOINC_BASE_ADDR, dummy_data, TINY_AUTOINC_DATA_SIZE);
printf(" reading from autoinc...\n");
hpi_read_inc(TINY_AUTOINC_BASE_ADDR, read_data, TINY_AUTOINC_DATA_SIZE);
printf(" reading from noinc for comparison...\n");
for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++)
read_data_noinc[i] = hpi_read_noinc(TINY_AUTOINC_BASE_ADDR+i*4);
for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) {
printf(" written=0x%x, read(inc)=0x%x, read(noinc)=0x%x\n",
dummy_data[i], read_data[i], read_data_noinc[i]);
}
return 0;
}
#endif /* CONFIG_SPC1920_HPI_TEST */

28
board/spc1920/hpi.h Normal file
View file

@ -0,0 +1,28 @@
/*
* (C) Copyright 2006
* Markus Klotzbuecher, DENX Software Engineering, mk@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
int hpi_init(void);
#ifdef CONFIG_SPC1920_HPI_TEST
int hpi_test(void);
#endif

2
board/spc1920/pld.h
View file

@ -5,8 +5,8 @@ typedef struct spc1920_pld {
uchar com1_en;
uchar dsp_reset;
uchar dsp_hpi_on;
uchar superv_mode;
uchar codec_dsp_power_en;
uchar clk2_en;
uchar clk3_select;
uchar clk4_select;
} spc1920_pld_t;

38
board/spc1920/spc1920.c
View file

@ -27,9 +27,9 @@
#include <common.h>
#include <mpc8xx.h>
#include "pld.h"
#include "hpi.h"
#define _NOT_USED_ 0xFFFFFFFF
/* #define debug(fmt,args...) printf (fmt ,##args) */
static long int dram_size (long int, long int *, long int);
@ -172,10 +172,12 @@ long int initdram (int board_type)
memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
udelay (1000);
/* initalize the DSP Host Port Interface */
hpi_init();
/* PLD Setup */
memctl->memc_or5 = CFG_OR5_PRELIM;
memctl->memc_br5 = CFG_BR5_PRELIM;
/* FRAM Setup */
memctl->memc_or4 = CFG_OR4;
memctl->memc_br4 = CFG_BR4;
udelay(1000);
return (size_b0);
@ -207,13 +209,31 @@ int board_early_init_f(void)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
/* Set Go/NoGo led (PA15) to color red */
immap->im_ioport.iop_papar &= ~0x1;
immap->im_ioport.iop_paodr &= ~0x1;
immap->im_ioport.iop_padir |= 0x1;
immap->im_ioport.iop_padat |= 0x1;
#if 0
/* Turn on LED PD9 */
immap->im_ioport.iop_pdpar &= ~(0x0040);
immap->im_ioport.iop_pddir |= 0x0040;
immap->im_ioport.iop_pddat |= 0x0040;
#endif
/* Enable PD10 (COM2_EN) */
/*
* Enable console on SMC1. This requires turning on
* the com2_en signal and SMC1_DISABLE
*/
/* SMC1_DISABLE: PB17 */
immap->im_cpm.cp_pbodr &= ~0x4000;
immap->im_cpm.cp_pbpar &= ~0x4000;
immap->im_cpm.cp_pbdir |= 0x4000;
immap->im_cpm.cp_pbdat &= ~0x4000;
/* COM2_EN: PD10 */
immap->im_ioport.iop_pdpar &= ~0x0020;
immap->im_ioport.iop_pddir &= ~0x4000;
immap->im_ioport.iop_pddir |= 0x0020;
@ -228,6 +248,14 @@ int board_early_init_f(void)
return 0;
}
int last_stage_init(void)
{
#ifdef CONFIG_SPC1920_HPI_TEST
printf("CMB1920 Host Port Interface Test: %s\n",
hpi_test() ? "Failed!" : "OK");
#endif
return 0;
}
int checkboard (void)
{

4
board/tqm5200/cam5200_flash.c
View file

@ -25,7 +25,7 @@
#include <mpc5xxx.h>
#include <asm/processor.h>
#ifdef CONFIG_CAM5200
#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
#if 0
#define DEBUGF(x...) printf(x)
@ -783,4 +783,4 @@ unsigned long flash_init(void)
return total_b;
}
#endif /* ifdef CONFIG_CAM5200 */
#endif /* if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) */

50
board/uc101/Makefile Normal file
View file

@ -0,0 +1,50 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

41
board/uc101/config.mk Normal file
View file

@ -0,0 +1,41 @@
#
# (C) Copyright 2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# INKA 4X0 board:
#
# Valid values for TEXT_BASE are:
#
# 0xFFE00000 boot high
#
# 0x00100000 boot from RAM (for testing only)
#
ifndef TEXT_BASE
## Standard: boot high
TEXT_BASE = 0xFFF00000
## For testing: boot from RAM
#TEXT_BASE = 0x00100000
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

136
board/uc101/u-boot.lds Normal file
View file

@ -0,0 +1,136 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc5xxx/start.o (.text)
cpu/mpc5xxx/traps.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/cache.o (.text)
lib_ppc/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.ppcenv)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

371
board/uc101/uc101.c Normal file
View file

@ -0,0 +1,371 @@
/*
* (C) Copyright 2006
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* (C) Copyright 2004
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <malloc.h>
/* some SIMPLE GPIO Pins */
#define GPIO_USB_8 (31-12)
#define GPIO_USB_7 (31-13)
#define GPIO_USB_6 (31-14)
#define GPIO_USB_0 (31-15)
#define GPIO_PSC3_7 (31-18)
#define GPIO_PSC3_6 (31-19)
#define GPIO_PSC3_1 (31-22)
#define GPIO_PSC3_0 (31-23)
/* some simple Interrupt GPIO Pins */
#define GPIO_PSC3_8 2
#define GPIO_USB1_9 3
#define GPT_OUT_0 0x00000027
#define GPT_OUT_1 0x00000037
#define GPT_DISABLE 0x00000000 /* GPT pin disabled */
#define GP_SIMP_ENABLE_O(n, v) {pgpio->simple_dvo |= (v << n); \
pgpio->simple_ddr |= (1 << n); \
pgpio->simple_gpioe |= (1 << n); \
}
#define GP_SIMP_ENABLE_I(n) { pgpio->simple_ddr |= ~(1 << n); \
pgpio->simple_gpioe |= (1 << n); \
}
#define GP_SIMP_SET_O(n, v) (pgpio->simple_dvo = v ? \
(pgpio->simple_dvo | (1 << n)) : \
(pgpio->simple_dvo & ~(1 << n)) )
#define GP_SIMP_GET_O(n) ((pgpio->simple_dvo >> n) & 1)
#define GP_SIMP_GET_I(n) ((pgpio->simple_ival >> n) & 1)
#define GP_SINT_SET_O(n, v) (pgpio->sint_dvo = v ? \
(pgpio->sint_dvo | (1 << n)) : \
(pgpio->sint_dvo & ~(1 << n)) )
#define GP_SINT_ENABLE_O(n, v) {pgpio->sint_ode &= ~(1 << n); \
pgpio->sint_ddr |= (1 << n); \
GP_SINT_SET_O(n, v); \
pgpio->sint_gpioe |= (1 << n); \
}
#define GP_SINT_ENABLE_I(n) { pgpio->sint_ddr |= ~(1 << n); \
pgpio->sint_gpioe |= (1 << n); \
}
#define GP_SINT_GET_O(n) ((pgpio->sint_ival >> n) & 1)
#define GP_SINT_GET_I(n) ((pgpio-ntt_ival >> n) & 1)
#define GP_TIMER_ENABLE_O(n, v) ( \
((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr = v ? \
GPT_OUT_1 : \
GPT_OUT_0 )
#define GP_TIMER_SET_O(n, v) GP_TIMER_ENABLE_O(n, v)
#define GP_TIMER_GET_O(n, v) ( \
(((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr & 0x10) >> 4)
#define GP_TIMER_GET_I(n, v) ( \
(((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->sr & 0x100) >> 8)
#ifndef CFG_RAMBOOT
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
__asm__ volatile ("sync");
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set mode register: extended mode */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
__asm__ volatile ("sync");
/* set mode register: reset DLL */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
__asm__ volatile ("sync");
#endif
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register */
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
__asm__ volatile ("sync");
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
}
#endif
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
*/
long int initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
__asm__ volatile ("sync");
/* setup config registers */
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
__asm__ volatile ("sync");
#if SDRAM_DDR
/* set tap delay */
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
__asm__ volatile ("sync");
#endif
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
sdram_start(1);
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20)) {
dramsize = 0;
}
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
__builtin_ffs(dramsize >> 20) - 1;
} else {
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
}
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
#else /* CFG_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
if (dramsize >= 0x13) {
dramsize = (1 << (dramsize - 0x13)) << 20;
} else {
dramsize = 0;
}
/* retrieve size of memory connected to SDRAM CS1 */
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
if (dramsize2 >= 0x13) {
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
} else {
dramsize2 = 0;
}
#endif /* CFG_RAMBOOT */
/* return dramsize + dramsize2; */
return dramsize;
}
int checkboard (void)
{
puts ("Board: MAN UC101\n");
return 0;
}
static void init_ports (void)
{
volatile struct mpc5xxx_gpio *pgpio =
(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
GP_SIMP_ENABLE_I(GPIO_USB_8); /* HEX Bit 3 */
GP_SIMP_ENABLE_I(GPIO_USB_7); /* HEX Bit 2 */
GP_SIMP_ENABLE_I(GPIO_USB_6); /* HEX Bit 1 */
GP_SIMP_ENABLE_I(GPIO_USB_0); /* HEX Bit 0 */
GP_SIMP_ENABLE_I(GPIO_PSC3_0); /* Switch Menue A */
GP_SIMP_ENABLE_I(GPIO_PSC3_1); /* Switch Menue B */
GP_SIMP_ENABLE_I(GPIO_PSC3_6); /* Switch Cold_Warm */
GP_SIMP_ENABLE_I(GPIO_PSC3_7); /* Switch Restart */
GP_SINT_ENABLE_O(GPIO_PSC3_8, 0); /* LED H2 */
GP_SINT_ENABLE_O(GPIO_USB1_9, 0); /* LED H3 */
GP_TIMER_ENABLE_O(4, 0); /* LED H4 */
GP_TIMER_ENABLE_O(5, 0); /* LED H5 */
GP_TIMER_ENABLE_O(3, 0); /* LED HB */
GP_TIMER_ENABLE_O(1, 0); /* RES_COLDSTART */
}
#ifdef CONFIG_PREBOOT
static uchar kbd_magic_prefix[] = "key_magic";
static uchar kbd_command_prefix[] = "key_cmd";
struct kbd_data_t {
char s1;
};
struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
{
volatile struct mpc5xxx_gpio *pgpio =
(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
kbd_data->s1 = GP_SIMP_GET_I(GPIO_USB_8) << 3 | \
GP_SIMP_GET_I(GPIO_USB_7) << 2 | \
GP_SIMP_GET_I(GPIO_USB_6) << 1 | \
GP_SIMP_GET_I(GPIO_USB_0) << 0;
return kbd_data;
}
static int compare_magic (const struct kbd_data_t *kbd_data, uchar *str)
{
char s1 = str[0];
if (s1 >= '0' && s1 <= '9')
s1 -= '0';
else if (s1 >= 'a' && s1 <= 'f')
s1 = s1 - 'a' + 10;
else if (s1 >= 'A' && s1 <= 'F')
s1 = s1 - 'A' + 10;
else
return -1;
if (s1 != kbd_data->s1) return -1;
return 0;
}
static uchar *key_match (const struct kbd_data_t *kbd_data)
{
uchar magic[sizeof (kbd_magic_prefix) + 1];
uchar *suffix;
uchar *kbd_magic_keys;
/*
* The following string defines the characters that can be appended
* to "key_magic" to form the names of environment variables that
* hold "magic" key codes, i. e. such key codes that can cause
* pre-boot actions. If the string is empty (""), then only
* "key_magic" is checked (old behaviour); the string "125" causes
* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
*/
if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
kbd_magic_keys = "";
/* loop over all magic keys;
* use '\0' suffix in case of empty string
*/
for (suffix = kbd_magic_keys; *suffix ||
suffix == kbd_magic_keys; ++suffix) {
sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
if (compare_magic(kbd_data, getenv(magic)) == 0) {
uchar cmd_name[sizeof (kbd_command_prefix) + 1];
char *cmd;
sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
cmd = getenv (cmd_name);
return (cmd);
}
}
return (NULL);
}
#endif /* CONFIG_PREBOOT */
int misc_init_r (void)
{
/* Init the I/O ports */
init_ports ();
#ifdef CONFIG_PREBOOT
struct kbd_data_t kbd_data;
/* Decode keys */
uchar *str = strdup (key_match (get_keys (&kbd_data)));
/* Set or delete definition */
setenv ("preboot", str);
free (str);
#endif /* CONFIG_PREBOOT */
return 0;
}
int board_early_init_r (void)
{
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
*(vu_long *)MPC5XXX_BOOTCS_START =
*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
*(vu_long *)MPC5XXX_BOOTCS_STOP =
*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
/* Interbus enable it here ?? */
*(vu_long *)MPC5XXX_GPT6_ENABLE = GPT_OUT_1;
return 0;
}
#ifdef CONFIG_PCI
static struct pci_controller hose;
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void)
{
pci_mpc5xxx_init(&hose);
}
#endif
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{
/* Trigger HW Watchdog with TIMER_0 */
*(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_1;
*(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_0;
}
#endif

21
board/v38b/v38b.c
View file

@ -191,16 +191,8 @@ int checkboard (void)
return 0;
}
int board_early_init_r(void)
int board_early_init_f(void)
{
/*
* Now, when we are in RAM, enable flash write access for the
* detection process. Note that CS_BOOT cannot be cleared when
* executing in flash.
*/
*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
#ifdef CONFIG_HW_WATCHDOG
/*
* Enable and configure the direction (output) of PSC3_9 - watchdog
@ -210,6 +202,17 @@ int board_early_init_r(void)
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
#endif /* CONFIG_HW_WATCHDOG */
return 0;
}
int board_early_init_r(void)
{
/*
* Now, when we are in RAM, enable flash write access for the
* detection process. Note that CS_BOOT cannot be cleared when
* executing in flash.
*/
*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
/*
* Enable GPIO_WKUP_7 to "read the status of the actual power

2
common/cmd_boot.c
View file

@ -83,7 +83,7 @@ U_BOOT_CMD(
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
U_BOOT_CMD(
reset, CFG_MAXARGS, 1, do_reset,
reset, 1, 0, do_reset,
"reset - Perform RESET of the CPU\n",
NULL
);

2
cpu/mpc5xxx/cpu_init.c
View file

@ -123,7 +123,7 @@ void cpu_init_f (void)
#endif
#if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE)
*(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS5_START);
*(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS7_START);
*(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE);
addecr |= (1 << 27);
#endif

7
cpu/mpc5xxx/fec.c
View file

@ -376,7 +376,7 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
mpc5xxx_fec_phydump ();
mpc5xxx_fec_phydump (dev->name);
#endif
/*
@ -575,7 +575,7 @@ static void mpc5xxx_fec_halt(struct eth_device *dev)
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
mpc5xxx_fec_phydump ();
mpc5xxx_fec_phydump (dev->name);
#endif
/*
@ -882,7 +882,8 @@ int mpc5xxx_fec_initialize(bd_t * bis)
defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
defined(CONFIG_MCC200) || defined(CONFIG_O2DNT) || \
defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
defined(CONFIG_TQM5200) || defined(CONFIG_V38B)
defined(CONFIG_TQM5200) || defined(CONFIG_V38B) || \
defined(CONFIG_UC101)
# ifndef CONFIG_FEC_10MBIT
fec->xcv_type = MII100;
# else

13
cpu/mpc8xx/serial.c
View file

@ -227,8 +227,17 @@ static int smc_init (void)
sp->smc_smcm = 0;
sp->smc_smce = 0xff;
#ifdef CFG_SPC1920_SMC1_CLK4 /* clock source is PLD */
*((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0xff;
#ifdef CFG_SPC1920_SMC1_CLK4
/* clock source is PLD */
/* set freq to 19200 Baud */
*((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0x3;
/* configure clk4 as input */
im->im_ioport.iop_pdpar |= 0x800;
im->im_ioport.iop_pddir &= ~0x800;
cp->cp_simode = 0x0000;
cp->cp_simode |= 0x7000;
#else
/* Set up the baud rate generator */
smc_setbrg ();

2
cpu/ppc4xx/405gp_pci.c
View file

@ -380,7 +380,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
}
#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))
#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SOLIDCARD3))
/*
*As is these functs get called out of flash Not a horrible

8
cpu/ppc4xx/440spe_pcie.c
View file

@ -26,10 +26,9 @@
#include <common.h>
#include <pci.h>
#include "440spe_pcie.h"
#if defined(CONFIG_440SPE) && defined(CONFIG_PCI)
#if defined(CONFIG_440SPE)
#if defined(CONFIG_PCI)
#include "440spe_pcie.h"
enum {
PTYPE_ENDPOINT = 0x0,
@ -958,5 +957,4 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
return 0;
}
#endif /* CONFIG_PCI */
#endif /* CONFIG_440SPE */
#endif /* CONFIG_440SPE && CONFIG_PCI */

141
cpu/ppc4xx/4xx_enet.c
View file

@ -166,6 +166,11 @@ struct eth_device *emac0_dev = NULL;
#define LAST_EMAC_NUM 1
#endif
/* normal boards start with EMAC0 */
#if !defined(CONFIG_EMAC_NR_START)
#define CONFIG_EMAC_NR_START 0
#endif
/*-----------------------------------------------------------------------------+
* Prototypes and externals.
*-----------------------------------------------------------------------------*/
@ -601,6 +606,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
/* end Vitesse/Cicada errata */
}
#endif
#if defined(CONFIG_ET1011C_PHY)
/*
* Agere ET1011c PHY needs to have an extended register whacked
* for RGMII mode.
*/
if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
miiphy_read (dev->name, reg, 0x16, &reg_short);
reg_short &= ~(0x7);
reg_short |= 0x6; /* RGMII DLL Delay*/
miiphy_write (dev->name, reg, 0x16, reg_short);
miiphy_read (dev->name, reg, 0x17, &reg_short);
reg_short &= ~(0x40);
miiphy_write (dev->name, reg, 0x17, reg_short);
miiphy_write(dev->name, reg, 0x1c, 0x74f0);
}
#endif
#endif
/* Start/Restart autonegotiation */
phy_setup_aneg (dev->name, reg);
@ -643,8 +668,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
if (hw_p->print_speed) {
hw_p->print_speed = 0;
printf ("ENET Speed is %d Mbps - %s duplex connection\n",
(int) speed, (duplex == HALF) ? "HALF" : "FULL");
printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
(int) speed, (duplex == HALF) ? "HALF" : "FULL",
hw_p->devnum);
}
#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
@ -1493,6 +1519,8 @@ int ppc_4xx_eth_initialize (bd_t * bis)
struct eth_device *dev;
int eth_num = 0;
EMAC_4XX_HW_PST hw = NULL;
u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
u32 hw_addr[4];
#if defined(CONFIG_440GX)
unsigned long pfc1;
@ -1502,6 +1530,43 @@ int ppc_4xx_eth_initialize (bd_t * bis)
pfc1 |= 0x01200000;
mtsdr (sdr_pfc1, pfc1);
#endif
/* first clear all mac-addresses */
for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
switch (eth_num) {
default: /* fall through */
case 0:
memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
bis->bi_enetaddr, 6);
hw_addr[eth_num] = 0x0;
break;
#ifdef CONFIG_HAS_ETH1
case 1:
memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
bis->bi_enet1addr, 6);
hw_addr[eth_num] = 0x100;
break;
#endif
#ifdef CONFIG_HAS_ETH2
case 2:
memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
bis->bi_enet2addr, 6);
hw_addr[eth_num] = 0x400;
break;
#endif
#ifdef CONFIG_HAS_ETH3
case 3:
memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
bis->bi_enet3addr, 6);
hw_addr[eth_num] = 0x600;
break;
#endif
}
}
/* set phy num and mode */
bis->bi_phynum[0] = CONFIG_PHY_ADDR;
bis->bi_phymode[0] = 0;
@ -1520,40 +1585,13 @@ int ppc_4xx_eth_initialize (bd_t * bis)
#endif
for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
/* See if we can actually bring up the interface, otherwise, skip it */
switch (eth_num) {
default: /* fall through */
case 0:
if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
continue;
}
break;
#ifdef CONFIG_HAS_ETH1
case 1:
if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
continue;
}
break;
#endif
#ifdef CONFIG_HAS_ETH2
case 2:
if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
continue;
}
break;
#endif
#ifdef CONFIG_HAS_ETH3
case 3:
if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
continue;
}
break;
#endif
/*
* See if we can actually bring up the interface,
* otherwise, skip it
*/
if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
continue;
}
/* Allocate device structure */
@ -1576,36 +1614,12 @@ int ppc_4xx_eth_initialize (bd_t * bis)
}
memset(hw, 0, sizeof(*hw));
switch (eth_num) {
default: /* fall through */
case 0:
hw->hw_addr = 0;
memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
break;
#ifdef CONFIG_HAS_ETH1
case 1:
hw->hw_addr = 0x100;
memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
break;
#endif
#ifdef CONFIG_HAS_ETH2
case 2:
hw->hw_addr = 0x400;
memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
break;
#endif
#ifdef CONFIG_HAS_ETH3
case 3:
hw->hw_addr = 0x600;
memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
break;
#endif
}
hw->hw_addr = hw_addr[eth_num];
memcpy (dev->enetaddr, ethaddr[eth_num], 6);
hw->devnum = eth_num;
hw->print_speed = 1;
sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
dev->priv = (void *) hw;
dev->init = ppc_4xx_eth_init;
dev->halt = ppc_4xx_eth_halt;
@ -1663,7 +1677,6 @@ int ppc_4xx_eth_initialize (bd_t * bis)
return (1);
}
#if !defined(CONFIG_NET_MULTI)
void eth_halt (void) {
if (emac0_dev) {

30
cpu/ppc4xx/cpu.c
View file

@ -332,24 +332,44 @@ int checkcpu (void)
strcpy(addstr, "No Security/Kasumi support");
break;
case PVR_440SP_RA:
puts("SP Rev. A");
case PVR_440SP_6_RAB:
puts("SP Rev. A/B");
strcpy(addstr, "RAID 6 support");
break;
case PVR_440SP_RB:
puts("SP Rev. B");
case PVR_440SP_RAB:
puts("SP Rev. A/B");
strcpy(addstr, "No RAID 6 support");
break;
case PVR_440SP_6_RC:
puts("SP Rev. C");
strcpy(addstr, "RAID 6 support");
break;
case PVR_440SP_RC:
puts("SP Rev. C");
strcpy(addstr, "No RAID 6 support");
break;
case PVR_440SPe_6_RA:
puts("SPe Rev. A");
strcpy(addstr, "RAID 6 support");
break;
case PVR_440SPe_RA:
puts("SPe Rev. A");
strcpy(addstr, "No RAID 6 support");
break;
case PVR_440SPe_6_RB:
puts("SPe Rev. B");
strcpy(addstr, "RAID 6 support");
break;
case PVR_440SPe_RB:
puts("SPe Rev. B");
strcpy(addstr, "No RAID 6 support");
break;
default:
@ -419,7 +439,7 @@ int ppc440spe_revB() {
unsigned int pvr;
pvr = get_pvr();
if (pvr == PVR_440SPe_RB)
if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
return 1;
else
return 0;

13
cpu/ppc4xx/cpu_init.c
View file

@ -31,9 +31,6 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
#ifdef CFG_INIT_DCACHE_CS
# if (CFG_INIT_DCACHE_CS == 0)
# define PBxAP pb0ap
@ -222,6 +219,10 @@ void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_M
void
cpu_init_f (void)
{
#if defined(CONFIG_WATCHDOG)
unsigned long val;
#endif
#if defined(CONFIG_405EP)
/*
* GPIO0 setup (select GPIO or alternate function)
@ -312,9 +313,11 @@ cpu_init_f (void)
mtebc(pb7cr, CFG_EBC_PB7CR);
#endif
#if defined(CONFIG_WATCHDOG)
unsigned long val;
#if defined (CFG_EBC_CFG)
mtebc(epcr, CFG_EBC_CFG);
#endif
#if defined(CONFIG_WATCHDOG)
val = mfspr(tcr);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */

35
cpu/ppc4xx/sdram.c
View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2005-2006
* (C) Copyright 2005-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
@ -32,9 +32,9 @@
#include <asm/processor.h>
#include "sdram.h"
#ifdef CONFIG_SDRAM_BANK0
#ifndef CONFIG_440
#ifndef CFG_SDRAM_TABLE
sdram_conf_t mb0cf[] = {
@ -50,9 +50,6 @@ sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
#ifndef CONFIG_440
#ifdef CFG_SDRAM_CASL
static ulong ns2clks(ulong ns)
{
@ -221,6 +218,26 @@ void sdram_init(void)
#else /* CONFIG_440 */
/*
* Define some default values. Those can be overwritten in the
* board config file.
*/
#ifndef CFG_SDRAM_TABLE
sdram_conf_t mb0cf[] = {
{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */
{(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */
};
#else
sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
#endif
#ifndef CFG_SDRAM0_TR0
#define CFG_SDRAM0_TR0 0x41094012
#endif
#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
#define NUM_TRIES 64
#define NUM_READS 10
@ -295,7 +312,6 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
*tr1_value = (first_good + last_bad) / 2;
}
#ifdef CONFIG_SDRAM_ECC
static void ecc_init(ulong start, ulong size)
{
@ -351,7 +367,8 @@ long int initdram(int board_type)
int i;
int tr1_bank1;
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
defined(CONFIG_440GR) || defined(CONFIG_440SP)
/*
* Soft-reset SDRAM controller.
*/
@ -378,9 +395,9 @@ long int initdram(int board_type)
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(mem_b0cr, mb0cf[i].reg);
mtsdram(mem_tr0, 0x41094012);
mtsdram(mem_tr0, CFG_SDRAM0_TR0);
mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
mtsdram(mem_rtr, 0x7e000000); /* Interval 15.20µs @ 133MHz PLB*/
mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
udelay(400); /* Delay 200 usecs (min) */

41
drivers/cfi_flash.c
View file

@ -2,7 +2,7 @@
* (C) Copyright 2002-2004
* Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
*
* Copyright (C) 2003, 2006 Arabella Software Ltd.
* Copyright (C) 2003 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*
* Copyright (C) 2004
@ -35,13 +35,10 @@
/* #define DEBUG */
#include <common.h>
#ifdef CFG_FLASH_CFI_DRIVER
#include <watchdog.h>
#include <asm/processor.h>
#include <asm/byteorder.h>
#include <environment.h>
#ifdef CFG_FLASH_CFI_DRIVER
/*
* This file implements a Common Flash Interface (CFI) driver for U-Boot.
@ -57,12 +54,10 @@
* AMD/Spansion Application Note: Migration from Single-byte to Three-byte
* Device IDs, Publication Number 25538 Revision A, November 8, 2001
*
* define CFG_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
* reading and writing ... (yes there is such a Hardware).
*/
#if defined(__LITTLE_ENDIAN) && !defined(CFG_FLASH_CFI_SWAP)
#define CFG_FLASH_CFI_SWAP
#endif
#ifndef CFG_FLASH_BANKS_LIST
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#endif
@ -263,7 +258,7 @@ inline uchar flash_read_uchar (flash_info_t * info, uint offset)
uchar *cp;
cp = flash_make_addr (info, 0, offset);
#if defined(CFG_FLASH_CFI_SWAP)
#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
return (cp[0]);
#else
return (cp[info->portwidth - 1]);
@ -290,7 +285,7 @@ ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
debug ("addr[%x] = 0x%x\n", x, addr[x]);
}
#endif
#if defined(CFG_FLASH_CFI_SWAP)
#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
retval = ((addr[(info->portwidth)] << 8) | addr[0]);
#else
retval = ((addr[(2 * info->portwidth) - 1] << 8) |
@ -322,7 +317,7 @@ ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
debug ("addr[%x] = 0x%x\n", x, addr[x]);
}
#endif
#if defined(CFG_FLASH_CFI_SWAP)
#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
(addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8);
#else
@ -863,7 +858,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
*/
static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
{
#if defined(__LITTLE_ENDIAN)
#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
unsigned short w;
unsigned int l;
unsigned long long ll;
@ -874,7 +869,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
cword->c = c;
break;
case FLASH_CFI_16BIT:
#if defined(__LITTLE_ENDIAN)
#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
w = c;
w <<= 8;
cword->w = (cword->w >> 8) | w;
@ -883,7 +878,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
#endif
break;
case FLASH_CFI_32BIT:
#if defined(__LITTLE_ENDIAN)
#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
l = c;
l <<= 24;
cword->l = (cword->l >> 8) | l;
@ -892,7 +887,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
#endif
break;
case FLASH_CFI_64BIT:
#if defined(__LITTLE_ENDIAN)
#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
ll = c;
ll <<= 56;
cword->ll = (cword->ll >> 8) | ll;
@ -912,22 +907,12 @@ static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
int i;
uchar *cp = (uchar *) cmdbuf;
#if defined(CFG_FLASH_CFI_SWAP)
#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
for (i = info->portwidth; i > 0; i--)
#else
for (i = 1; i <= info->portwidth; i++)
#endif
*cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd;
#ifdef CFG_FLASH_CFI_2x16
if ((info->portwidth == FLASH_CFI_32BIT) && (info->chipwidth == FLASH_CFI_BY16))
{
uchar tmp;
cp = (uchar *) cmdbuf;
tmp = cp[1];
cp[1] = cp[2];
cp[2] = tmp;
}
#endif /* CFG_FLASH_CFI_2x16 */
}
/*
@ -1376,7 +1361,6 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest,
ctladdr.cp = flash_make_addr (info, 0, 0);
cptr.cp = (uchar *) dest;
/* Check if Flash is (sufficiently) erased */
switch (info->portwidth) {
case FLASH_CFI_8BIT:
@ -1548,4 +1532,5 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
}
}
#endif /* CFG_FLASH_USE_BUFFER_WRITE */
#endif /* CFG_FLASH_CFI */

2
drivers/nand/nand_base.c
View file

@ -2338,7 +2338,7 @@ int nand_scan (struct mtd_info *mtd, int maxchips)
mtd->oobblock = 1024 << (extid & 0x3);
extid >>= 2;
/* Calc oobsize */
mtd->oobsize = (8 << (extid & 0x03)) * (mtd->oobblock / 512);
mtd->oobsize = (8 << (extid & 0x01)) * (mtd->oobblock / 512);
extid >>= 2;
/* Calc blocksize. Blocksize is multiples of 64KiB */
mtd->erasesize = (64 * 1024) << (extid & 0x03);

2
dtt/Makefile
View file

@ -30,7 +30,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libdtt.a
COBJS = lm75.o ds1621.o adm1021.o
COBJS = lm75.o ds1621.o adm1021.o lm81.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

148
dtt/lm81.c Normal file
View file

@ -0,0 +1,148 @@
/*
* (C) Copyright 2006
* Heiko Schocher, DENX Software Enginnering <hs@denx.de>
*
* based on dtt/lm75.c which is ...
*
* (C) Copyright 2001
* Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* On Semiconductor's LM81 Temperature Sensor
*/
#include <common.h>
#ifdef CONFIG_DTT_LM81
#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
(CFG_EEPROM_PAGE_WRITE_BITS < 1)
# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM81"
#endif
#include <i2c.h>
#include <dtt.h>
/*
* Device code
*/
#define DTT_I2C_DEV_CODE 0x2c /* ON Semi's LM81 device */
int dtt_read(int sensor, int reg)
{
int dlen = 1;
uchar data[2];
/*
* Calculate sensor address and register.
*/
sensor = DTT_I2C_DEV_CODE + (sensor & 0x03); /* calculate address of lm81 */
/*
* Now try to read the register.
*/
if (i2c_read(sensor, reg, 1, data, dlen) != 0)
return -1;
return (int)data[0];
} /* dtt_read() */
int dtt_write(int sensor, int reg, int val)
{
uchar data;
/*
* Calculate sensor address and register.
*/
sensor = DTT_I2C_DEV_CODE + (sensor & 0x03); /* calculate address of lm81 */
data = (char)(val & 0xff);
/*
* Write value to register.
*/
if (i2c_write(sensor, reg, 1, &data, 1) != 0)
return 1;
return 0;
} /* dtt_write() */
#define DTT_MANU 0x3e
#define DTT_REV 0x3f
#define DTT_CONFIG 0x40
#define DTT_ADR 0x48
static int _dtt_init(int sensor)
{
int man;
int adr;
int rev;
if (dtt_write (sensor, DTT_CONFIG, 0x01) < 0)
return 1;
/* The LM81 needs 400ms to get the correct values ... */
udelay (400000);
man = dtt_read (sensor, DTT_MANU);
if (man != 0x01)
return 1;
adr = dtt_read (sensor, DTT_ADR);
if (adr < 0)
return 1;
rev = dtt_read (sensor, DTT_REV);
if (adr < 0)
return 1;
printf ("DTT: Found LM81@%x Rev: %d\n", adr, rev);
return 0;
} /* _dtt_init() */
int dtt_init (void)
{
int i;
unsigned char sensors[] = CONFIG_DTT_SENSORS;
const char *const header = "DTT: ";
for (i = 0; i < sizeof(sensors); i++) {
if (_dtt_init(sensors[i]) != 0)
printf("%s%d FAILED INIT\n", header, i+1);
else
printf("%s%d is %i C\n", header, i+1,
dtt_get_temp(sensors[i]));
}
return (0);
} /* dtt_init() */
#define TEMP_FROM_REG(temp) \
((temp)<256?((((temp)&0x1fe) >> 1) * 10) + ((temp) & 1) * 5: \
((((temp)&0x1fe) >> 1) -255) * 10 - ((temp) & 1) * 5) \
int dtt_get_temp(int sensor)
{
int val = dtt_read (sensor, DTT_READ_TEMP);
int tmpcnf = dtt_read (sensor, DTT_CONFIG_TEMP);
return (TEMP_FROM_REG((val << 1) + ((tmpcnf & 0x80) >> 7))) / 10;
} /* dtt_get_temp() */
#endif /* CONFIG_DTT_LM81 */

13
include/asm-ppc/processor.h
View file

@ -747,11 +747,14 @@
#define PVR_440GX_RC 0x51B21892
#define PVR_440GX_RF 0x51B21894
#define PVR_405EP_RB 0x51210950
#define PVR_440SP_RA 0x53221850
#define PVR_440SP_RB 0x53221891
#define PVR_440SP_RC 0x53221892
#define PVR_440SPe_RA 0x53421890
#define PVR_440SPe_RB 0x53421891
#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */
#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */
#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */
#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */
#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */
#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */
#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */
#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000

34
include/configs/TQM5200.h
View file

@ -231,6 +231,17 @@
"protect on FC000000 +${filesize}\0"
#endif
#ifndef CONFIG_CAM5200
#define CUSTOM_ENV_SETTINGS \
"bootfile=/tftpboot/tqm5200/uImage\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
#else
#define CUSTOM_ENV_SETTINGS \
"bootfile=cam5200/uImage\0" \
"u-boot=cam5200/u-boot.bin\0" \
"setup=tftp 200000 cam5200/setup.img; autoscr 200000\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
@ -248,8 +259,7 @@
"bootm ${kernel_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
"bootm\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
CUSTOM_ENV_SETTINGS \
"load=tftp 200000 ${u-boot}\0" \
ENV_UPDT \
""
@ -325,15 +335,7 @@
*/
#define CFG_FLASH_BASE 0xFC000000
#ifndef CONFIG_CAM5200
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#else /* CONFIG_CAM5200 */
#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks
(= chip selects) */
#define CFG_FLASH_WORD_SIZE unsigned int /* main flash device with */
@ -344,7 +346,15 @@
#define CFG_FLASH_ADDR1 0x2AA
#define CFG_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */
#define CFG_MAX_FLASH_SECT 128
#endif /* ifndef CONFIG_CAM5200 */
#else
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#endif
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */

19
include/configs/alpr.h
View file

@ -166,8 +166,23 @@
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
"ethprime=ppc_4xx_eth3\0" \
"ethact=ppc_4xx_eth3\0" \
"autoload=no\0" \
"ipconfig=dhcp;setenv serverip 11.0.0.152\0" \
"actkernel=kernel2\0" \
"load_fpga=fpga load 0 ffe00000 10dd9a\0" \
"mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \
"rootfstype=jffs2 init=/sbin/init\0" \
"kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
";bootm 200000\0" \
"kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
"addtty;bootm 200000\0" \
"kernel1=run ipconfig load_fpga kernel1_mtd\0" \
"kernel2=run ipconfig load_fpga kernel2_mtd\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_BOOTCOMMAND "run kernel2"
#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
@ -291,6 +306,8 @@
/*-----------------------------------------------------------------------
* Definitions for GPIO setup
*-----------------------------------------------------------------------*/
#define CFG_GPIO_SHUTDOWN (0x80000000 >> 6)
#define CFG_GPIO_SSD_EMPTY (0x80000000 >> 9)
#define CFG_GPIO_EREADY (0x80000000 >> 26)
#define CFG_GPIO_REV0 (0x80000000 >> 14)
#define CFG_GPIO_REV1 (0x80000000 >> 15)

5
include/configs/p3mx.h
View file

@ -168,10 +168,12 @@
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI /* include pci support */
#ifdef CONFIG_PCI
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
#endif /* CONFIG_PCI */
/* PCI MEMORY MAP section */
#define CFG_PCI0_MEM_BASE 0x80000000
@ -194,7 +196,6 @@
#define CFG_PCI1_IO_SPACE_PCI 0x00000000
#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
#define CFG_PCI_IDSEL 0x30
#undef CONFIG_BOOTARGS

37
include/configs/pdnb3.h
View file

@ -71,12 +71,18 @@
#define CONFIG_BAUDRATE 115200
#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
#if defined(CONFIG_SCPU)
#define CMD_NAND_ADD 0
#else
#define CMD_NAND_ADD CFG_CMD_NAND
#endif
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_DATE | \
CFG_CMD_NET | \
CFG_CMD_MII | \
CFG_CMD_NAND | \
CMD_NAND_ADD | \
CFG_CMD_I2C | \
CFG_CMD_ELF | \
CFG_CMD_PING)
@ -176,12 +182,20 @@
#define CFG_FLASH_BASE 0x50000000
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#if defined(CONFIG_SCPU)
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */
#else
#define CFG_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */
#endif
/*
* Expansion bus settings
*/
#if defined(CONFIG_SCPU)
#define CFG_EXP_CS0 0x94d23C42 /* 8bit, max size */
#else
#define CFG_EXP_CS0 0x94913C43 /* 8bit, max size */
#endif
#define CFG_EXP_CS1 0x85000043 /* 8bit, 512bytes */
/*
@ -194,6 +208,12 @@
/*
* FLASH and environment organization
*/
#if defined(CONFIG_SCPU)
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
#endif
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
@ -217,20 +237,27 @@
#define CFG_ENV_IS_IN_FLASH 1
#if defined(CONFIG_SCPU)
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#else
#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
#endif
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#if !defined(CONFIG_SCPU)
/*
* NAND-FLASH stuff
*/
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
#endif
/*
* GPIO settings
@ -284,9 +311,15 @@
/*
* I2C RTC
*/
#if 0 /* test-only */
#define CONFIG_RTC_DS1340 1
#define CFG_I2C_RTC_ADDR 0x68
#else
/* M41T11 Serial Access Timekeeper(R) SRAM */
#define CONFIG_RTC_M41T11 1
#define CFG_I2C_RTC_ADDR 0x68
#define CFG_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
#endif
/*
* Spartan3 FPGA configuration support

585
include/configs/sc3.h Normal file
View file

@ -0,0 +1,585 @@
/*
* (C) Copyright 2007
* Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
*
* From:
* (C) Copyright 2003
* Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#undef USE_VGA_GRAPHICS
/* Memory Map
* 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB)
* 0x74000000 .... 0x740FFFFF -> CS#6
* 0x74100000 .... 0x741FFFFF -> CS#7
* 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB
* 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE
* 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB)
* 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB)
* 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB)
* 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB)
* 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored)
* 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB)
*
* 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1)
* 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF)
* 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF)
* 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF)
* 0xEED00000 .... 0xEED00003 -> PCI-Bus
* 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers
* 0xEF40003F .... 0xEF5FFFFF -> reserved
* 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB)
* 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB)
* 0xF0200000 .... 0xF7FFFFFF -> free for flash devices
* 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB)
* 0xF8001000 .... 0xFFDFFFFF -> free for flash devices
* 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
*/
#define CONFIG_SOLIDCARD3 1
#define CONFIG_4xx 1
#define CONFIG_405GP 1
#define CONFIG_BOARD_EARLY_INIT_F 1
/*
* Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range
* If undefined, IDE access uses a seperat emulation with higher access speed.
* Consider to inform your Linux IDE driver about the different addresses!
* IDE_USES_ISA_EMULATION is only used if your CONFIG_COMMANDS macro includes
* the CFG_CMD_IDE macro!
*/
#define IDE_USES_ISA_EMULATION
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_SERIAL_MULTI
#undef CONFIG_SERIAL_SOFTWARE_FIFO
/*
* define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input
* Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature
*/
#if CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_POWER_DOWN
#endif
/*
* define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz
*/
#define CONFIG_SYS_CLK_FREQ 33333333
/*
* define CONFIG_BAUDRATE to the baudrate value you want to use as default
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nand_args=setenv bootargs root=/dev/mtdblock5 rw" \
"rootfstype=jffs2\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
"flash_nand=nand_args addip addcon;bootm ${kernel_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/sc3/uImage\0" \
"u-boot=/tftpboot/sc3/u-boot.bin\0" \
"setup=tftp 200000 /tftpboot/sc3/setup.img;autoscr 200000\0" \
"kernel_addr=FFE08000\0" \
""
#undef CONFIG_BOOTCOMMAND
#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
#if 1 /* feel free to disable for development */
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with S\n"
#define CONFIG_AUTOBOOT_DELAY_STR "S" /* 1st "password" */
#endif
/*
* define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after
* the CONFIG_BOOTDELAY delay to boot your machine
*/
#define CONFIG_BOOTCOMMAND "bootp;dcache on;bootm"
/*
* define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't
* set different values at the u-boot prompt
*/
#ifdef USE_VGA_GRAPHICS
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re"
#else
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs rw ip=bootp"
#endif
/*
* Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT
* This reserves memory bank #4 for this purpose
*/
#undef CONFIG_ISP1161_PRESENT
#undef CONFIG_LOADS_ECHO /* no echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_NET_MULTI
/* #define CONFIG_EEPRO100_SROM_WRITE */
/* #define CONFIG_SHOW_MAC */
#define CONFIG_EEPRO100
#define CONFIG_MII 1 /* add 405GP MII PHY management */
#define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */
#define CONFIG_COMMANDS \
(CONFIG_CMD_DFL | \
CFG_CMD_AUTOSCRIPT | \
CFG_CMD_PCI | \
CFG_CMD_IRQ | \
CFG_CMD_NET | \
CFG_CMD_MII | \
CFG_CMD_PING | \
CFG_CMD_NAND | \
CFG_CMD_JFFS2 | \
CFG_CMD_I2C | \
CFG_CMD_IDE | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_CACHE | \
CFG_CMD_ELF )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP 1 /* undef to save memory */
#define CFG_PROMPT "SC3> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
/*
* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
* The Linux BASE_BAUD define should match this configuration.
* baseBaud = cpuClock/(uartDivisor*16)
* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*
* Consider the OPB clock! If it get lower the BASE_BAUD must be lower to
* (see 405GP datasheet for descritpion)
*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD 921600 /* internal clock */
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
#define CFG_LOAD_ADDR 0x1000000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* IIC stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define I2C_INIT
#define I2C_ACTIVE 0
#define I2C_TRISTATE 0
#define CFG_I2C_SPEED 100000 /* use the standard 100kHz speed */
#define CFG_I2C_SLAVE 0x7F /* mask valid bits */
#define CONFIG_RTC_DS1337
#define CFG_I2C_RTC_ADDR 0x68
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
/* If you want to see, whats connected to your PCI bus */
/* #define CONFIG_PCI_SCAN_SHOW */
#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* External peripheral base address
*-----------------------------------------------------------------------
*/
#if !(CONFIG_COMMANDS & CFG_CMD_IDE)
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
/*-----------------------------------------------------------------------
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
#else /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
#define CONFIG_START_IDE 1 /* check, if use IDE */
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
#define CONFIG_ATAPI
#define CONFIG_DOS_PARTITION
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
#ifndef IDE_USES_ISA_EMULATION
/* New and faster access */
#define CFG_ATA_BASE_ADDR 0x7A000000 /* start of ISA IO emulation */
/* How many IDE busses are available */
#define CFG_IDE_MAXBUS 1
/* What IDE ports are available */
#define CFG_ATA_IDE0_OFFSET 0x000 /* first is available */
#undef CFG_ATA_IDE1_OFFSET /* second not available */
/* access to the data port is calculated:
CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
/* access to the registers is calculated:
CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
/* access to the alternate register is calculated:
CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
#define CFG_ATA_ALT_OFFSET 0x008 /* Offset for alternate registers */
#else /* IDE_USES_ISA_EMULATION */
#define CFG_ATA_BASE_ADDR 0x79000000 /* start of ISA IO emulation */
/* How many IDE busses are available */
#define CFG_IDE_MAXBUS 1
/* What IDE ports are available */
#define CFG_ATA_IDE0_OFFSET 0x01F0 /* first is available */
#undef CFG_ATA_IDE1_OFFSET /* second not available */
/* access to the data port is calculated:
CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
/* access to the registers is calculated:
CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
/* access to the alternate register is calculated:
CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
#define CFG_ATA_ALT_OFFSET 0x03F0 /* Offset for alternate registers */
#endif /* IDE_USES_ISA_EMULATION */
#endif /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
/*
#define CFG_KEY_REG_BASE_ADDR 0xF0100000
#define CFG_IR_REG_BASE_ADDR 0xF0200000
#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
*/
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*
* CFG_FLASH_BASE -> start address of internal flash
* CFG_MONITOR_BASE -> start of u-boot
*/
#ifndef __ASSEMBLER__
extern unsigned long offsetOfBigFlash;
extern unsigned long offsetOfEnvironment;
#endif
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFFE00000
#define CFG_MONITOR_BASE 0xFFFC0000 /* placed last 256k */
#define CFG_MONITOR_LEN (224 * 1024) /* Reserve 224 KiB for Monitor */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MiB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization ## FIXME: lookup in datasheet
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_CFI /* flash is CFI compat. */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_WRITE_SWAPPED_DATA /* swap Databytes between reading/writing */
#define CFG_ENV_IS_IN_FLASH 1
#if CFG_ENV_IS_IN_FLASH
#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
/* let us changing anything in our environment */
#define CONFIG_ENV_OVERWRITE
/*
* NAND-FLASH stuff
*/
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE 0x77D00000
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
/* No command line, one static partition Partition 3 contains jffs2 rootfs */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV "nand0"
#define CONFIG_JFFS2_PART_SIZE 0x00400000
#define CONFIG_JFFS2_PART_OFFSET 0x00c00000
/*-----------------------------------------------------------------------
* Cache Configuration
*
* CFG_DCACHE_SIZE -> size of data cache:
* - 405GP 8k
* - 405GPr 16k
* How to handle the difference in chache size?
* CFG_CACHELINE_SIZE -> size of one cache line: 32 bytes
* (used in cpu/ppc4xx/start.S)
*/
#define CFG_DCACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*
*/
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE
#define FLASH_BASE1_PRELIM 0
/*-----------------------------------------------------------------------
* Some informations about the internal SRAM (OCM=On Chip Memory)
*
* CFG_OCM_DATA_ADDR -> location
* CFG_OCM_DATA_SIZE -> size
*/
#define CFG_TEMP_STACK_OCM 1
#define CFG_OCM_DATA_ADDR 0xF8000000
#define CFG_OCM_DATA_SIZE 0x1000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM):
* - we are using the internal 4k SRAM, so we don't need data cache mapping
* - internal SRAM (OCM=On Chip Memory) is placed to CFG_OCM_DATA_ADDR
* - Stackpointer will be located to
* (CFG_INIT_RAM_ADDR&0xFFFF0000) | (CFG_INIT_SP_OFFSET&0x0000FFFF)
* in cpu/ppc4xx/start.S
*/
#undef CFG_INIT_DCACHE_CS
/* Where the internal SRAM starts */
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR
/* Where the internal SRAM ends (only offset) */
#define CFG_INIT_RAM_END 0x0F00
/*
CFG_INIT_RAM_ADDR ------> ------------ lower address
| |
| ^ |
| | |
| | Stack |
CFG_GBL_DATA_OFFSET ----> ------------
| |
| 64 Bytes |
| |
CFG_INIT_RAM_END ------> ------------ higher address
(offset only)
*/
/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_SIZE 64
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/* Initial value of the stack pointern in internal SRAM */
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/* ################################################################################### */
/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */
/* They are currently undefined cause they are initiaized in board/solidcard3/init.S */
/* This chip select accesses the boot device */
/* It depends on boot select switch if this device is 16 or 8 bit */
#undef CFG_EBC_PB0AP
#undef CFG_EBC_PB0CR
#undef CFG_EBC_PB1AP
#undef CFG_EBC_PB1CR
#undef CFG_EBC_PB2AP
#undef CFG_EBC_PB2CR
#undef CFG_EBC_PB3AP
#undef CFG_EBC_PB3CR
#undef CFG_EBC_PB4AP
#undef CFG_EBC_PB4CR
#undef CFG_EBC_PB5AP
#undef CFG_EBC_PB5CR
#undef CFG_EBC_PB6AP
#undef CFG_EBC_PB6CR
#undef CFG_EBC_PB7AP
#undef CFG_EBC_PB7CR
#define CFG_EBC_CFG 0xb84ef000
#define CONFIG_SDRAM_BANK0 /* use the standard SDRAM initialization */
#undef CONFIG_SPD_EEPROM
/*
* Define this to get more information about system configuration
*/
/* #define SC3_DEBUGOUT */
#undef SC3_DEBUGOUT
/***********************************************************************
* External peripheral base address
***********************************************************************/
#define CFG_ISA_MEM_BASE_ADDRESS 0x78000000
/*
Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu.
Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen
auf ISA- und PCI-Zyklen)
*/
#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
/*#define CFG_ISA_IO_BASE_ADDRESS 0x79000000 */
/************************************************************
* Video support
************************************************************/
#ifdef USE_VGA_GRAPHICS
#define CONFIG_VIDEO /* To enable video controller support */
#define CONFIG_VIDEO_CT69000
#define CONFIG_CFB_CONSOLE
/* #define CONFIG_VIDEO_LOGO */
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
/* #define CONFIG_VIDEO_HW_CURSOR */
#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
#define VIDEO_HW_RECTFILL
#define VIDEO_HW_BITBLT
#endif
/************************************************************
* Ident
************************************************************/
#define CONFIG_SC3_VERSION "r1.4"
#define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x)
#endif /* __CONFIG_H */

5
include/configs/sequoia.h
View file

@ -188,7 +188,10 @@
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CFG_MBYTES_SDRAM (256) /* 256MB */
#define CFG_MBYTES_SDRAM (256) /* 256MB */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
/*-----------------------------------------------------------------------
* I2C

102
include/configs/spc1920.h
View file

@ -44,19 +44,19 @@
#define CONFIG_BAUDRATE 19200
/* use PLD CLK4 instead of brg */
#undef CFG_SPC1920_SMC1_CLK4
#define CFG_SPC1920_SMC1_CLK4
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
#define CFG_8xx_CPUCLK_MIN 40000000
#define CFG_8xx_CPUCLK_MAX 133000000
#define CFG_RESET_ADDRESS 0xf8000000
#define CFG_RESET_ADDRESS 0xC0000000
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_LAST_STAGE_INIT
#if 1
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
@ -83,12 +83,13 @@
#ifndef CONFIG_COMMANDS
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_ASKENV \
| CFG_CMD_DATE \
| CFG_CMD_ECHO \
| CFG_CMD_IMMAP \
| CFG_CMD_JFFS2 \
| CFG_CMD_PING \
| CFG_CMD_DHCP \
| CFG_CMD_IMMAP \
| CFG_CMD_I2C \
| CFG_CMD_MII)
/* & ~( CFG_CMD_NET)) */
@ -193,13 +194,39 @@
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#ifdef CFG_CMD_DATE
# define CONFIG_RTC_DS3231
# define CFG_I2C_RTC_ADDR 0x68
#endif
/*-----------------------------------------------------------------------
* I2C configuration
*/
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
#define CFG_I2C_SLAVE 0x7F
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
#define CFG_I2C_SLAVE 0xFE
#ifdef CONFIG_SOFT_I2C
/*
* Software (bit-bang) I2C driver configuration
*/
#define PB_SCL 0x00000020 /* PB 26 */
#define PB_SDA 0x00000010 /* PB 27 */
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
else immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
#endif /* CONFIG_SOFT_I2C */
#endif
/*-----------------------------------------------------------------------
@ -220,7 +247,7 @@
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#define CFG_SIUMCR (SIUMCR_FRC)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
@ -283,7 +310,7 @@
* FLASH timing:
*/
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
OR_SCY_3_CLK | OR_EHTR | OR_BI)
OR_SCY_6_CLK | OR_EHTR | OR_BI)
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@ -330,7 +357,56 @@
MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
/* PLD CS5 */
/*
* DSP Host Port Interface CS3
*/
#define CFG_SPC1920_HPI_BASE 0x90000000
#define CFG_PRELIM_OR3_AM 0xF8000000
#define CFG_OR3 (CFG_PRELIM_OR3_AM | \
OR_G5LS | \
OR_SCY_0_CLK | \
OR_BI)
#define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
BR_MS_UPMA | \
BR_PS_16 | \
BR_V);
#define CFG_MAMR (MAMR_GPL_A4DIS | \
MAMR_RLFA_5X | \
MAMR_WLFA_5X)
#define CONFIG_SPC1920_HPI_TEST
#ifdef CONFIG_SPC1920_HPI_TEST
#define HPI_REG(x) (*((volatile u16 *) (CFG_SPC1920_HPI_BASE + x)))
#define HPI_HPIC_1 HPI_REG(0)
#define HPI_HPIC_2 HPI_REG(2)
#define HPI_HPIA_1 HPI_REG(0x2000008)
#define HPI_HPIA_2 HPI_REG(0x2000008 + 2)
#define HPI_HPID_INC_1 HPI_REG(0x1000004)
#define HPI_HPID_INC_2 HPI_REG(0x1000004 + 2)
#define HPI_HPID_NOINC_1 HPI_REG(0x300000c)
#define HPI_HPID_NOINC_2 HPI_REG(0x300000c + 2)
#endif /* CONFIG_SPC1920_HPI_TEST */
/*
* Ramtron FM18L08 FRAM 32KB on CS4
*/
#define CFG_SPC1920_FRAM_BASE 0x80100000
#define CFG_PRELIM_OR4_AM 0xffff8000
#define CFG_OR4 (CFG_PRELIM_OR4_AM | \
OR_ACS_DIV2 | \
OR_BI | \
OR_SCY_4_CLK | \
OR_TRLX)
#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
/*
* PLD CS5
*/
#define CFG_SPC1920_PLD_BASE 0x80000000
#define CFG_PRELIM_OR5_AM 0xffff8000
@ -343,10 +419,6 @@
#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
/* #define CFG_PLD_BASE 0x30000000 */
/* #define CFG_OR5_PRELIM 0xffff1110 */
/* #define CFG_BR5_PRELIM 0x30000401 */
/*
* Internal Definitions
*

333
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@ -0,0 +1,333 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* TAISHAN.h - configuration for AMCC 440GX Ref
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_TAISHAN 1 /* Board is taishan */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CFG_EBC0_FLASH_BASE CFG_FLASH_BASE
#define CFG_EBC1_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x01000000)
#define CFG_EBC2_LCM_BASE (CFG_PERIPHERAL_BASE + 0x02000000)
#define CFG_EBC3_CONN_BASE (CFG_PERIPHERAL_BASE + 0x08000000)
#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700)
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in internal SRAM)
*----------------------------------------------------------------------*/
#define CFG_TEMP_STACK_OCM 1
#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM*/
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc*/
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_UART1_CONSOLE 1 /* use of UART1 as console */
#define CONFIG_SERIAL_MULTI 1 /* enable serial multi support */
#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*-----------------------------------------------------------------------
* E2PROM bootstrap configure value
*----------------------------------------------------------------------*/
/*
* 800/133/66
* IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00
*/
/*
* 800/160/80
* IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00
*/
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
#define CFG_SDRAM0_TR0 0xC10A401A
#undef CONFIG_SDRAM_ECC /* enable ECC support */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#undef CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR 0x50
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CFG_BOOTSTRAP_IIC_ADDR 0x50
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CFG_DTT_MAX_TEMP 70
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=taishan\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/taishan/uImage\0" \
"kernel_addr=fc000000\0" \
"ramdisk_addr=fc180000\0" \
"load=tftp 100000 /tftpboot/taishan/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
"fixedip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
"$(gatewayip):$(netmask):$(hostname):$(netdev):off panic=1\0" \
"dhcp=setenv bootargs $(bootargs) ip=dhcp\0" \
"kozio=bootm 0xffe00000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*-----------------------------------------------------------------------
* Networking
*----------------------------------------------------------------------*/
#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY2_ADDR 0x1
#define CONFIG_PHY3_ADDR 0x3
#define CONFIG_ET1011C_PHY 1
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_RESET_DELAY 1000
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_NETCONSOLE /* include NetConsole support */
/*-----------------------------------------------------------------------
* Console/Commands/Parser
*----------------------------------------------------------------------*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_DTT | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_EEPRO100 1 /* include PCI EEPRO100 */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* Cache Configuration
*----------------------------------------------------------------------*/
#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#endif /* __CONFIG_H */

353
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@ -0,0 +1,353 @@
/*
* (C) Copyright 2003-2006
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_UC101 1 /* UC101 board */
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
#define CONFIG_BOARD_EARLY_INIT_R
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/* Partitions */
#define CONFIG_DOS_PARTITION
/*
* Supported commands
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_DISPLAY | \
CFG_CMD_DHCP | \
CFG_CMD_PING | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_DTT | \
CFG_CMD_IDE | \
CFG_CMD_FAT | \
CFG_CMD_NFS | \
CFG_CMD_MII | \
CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
#if (TEXT_BASE == 0xFFF00000) /* Boot low */
# define CFG_LOWBOOT 1
#endif
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addwdt=setenv bootargs ${bootargs} wdt=off" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
"net_nfs=tftp 300000 ${bootfile};run nfsargs addip addwdt;bootm\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CONFIG_MISC_INIT_R 1
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
#define CFG_I2C_SPEED 100000 /* 100 kHz */
#define CFG_I2C_SLAVE 0x7F
/*
* EEPROM configuration
*/
#define CFG_I2C_EEPROM_ADDR 0x58
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
/* for LM81 */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*
* RTC configuration
*/
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR 0x51
/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CFG_DTT_MAX_TEMP 70
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
/*
* Flash configuration
*/
#define CFG_FLASH_BASE 0xFF800000
#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
#define CFG_MAX_FLASH_SECT 140 /* max num of sects on one chip */
#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_CFI_AMD_RESET
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x4000
#define CFG_ENV_SECT_SIZE 0x10000
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*
* Memory map
*/
#define CFG_MBAR 0xF0000000
#define CFG_DEFAULT_MBAR 0x80000000
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SRAM_BASE 0x80100000 /* CS 1 */
#define CFG_DISPLAY_BASE 0x80600000 /* CS 3 */
#define CFG_IB_MASTER 0xc0510000 /* CS 6 */
#define CFG_IB_EPLD 0xc0500000 /* CS 7 */
/* Settings for XLB = 132 MHz */
#define SDRAM_DDR 1
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x714f0f00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
/* SRAM */
#define SRAM_BASE CFG_SRAM_BASE /* SRAM base address */
#define SRAM_LEN 0x1fffff
#define SRAM_END (SRAM_BASE + SRAM_LEN)
/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
#else
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
#endif
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT 1
#endif
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_MII 1
/*
* GPIO configuration
*/
#define CFG_GPS_PORT_CONFIG 0x4d558044
/*use Hardware WDT */
#define CONFIG_HW_WATCHDOG
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST
#define CFG_MEMTEST_START 0x00300000 /* memtest works on */
#define CFG_MEMTEST_END 0x00f00000 /* 3 ... 15 MB in DRAM */
#define CFG_LOAD_ADDR 0x300000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
* which is normally part of the default commands (CFV_CMD_DFL)
*/
#define CONFIG_LOOPW
/*
* Various low-level settings
*/
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL HID0_ICE
#else
#define CFG_HID0_INIT 0
#define CFG_HID0_FINAL 0
#endif
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG 0x00045D00
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
/* 8Mbit SRAM @0x80100000 */
#define CFG_CS1_START CFG_SRAM_BASE
#define CFG_CS1_SIZE 0x00100000
#define CFG_CS1_CFG 0x21D00
/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
#define CFG_CS3_START CFG_DISPLAY_BASE
#define CFG_CS3_SIZE 0x00000100
#define CFG_CS3_CFG 0x00081802
/* Interbus Master 16 Bit */
#define CFG_CS6_START CFG_IB_MASTER
#define CFG_CS6_SIZE 0x00010000
#define CFG_CS6_CFG 0x00FF3500
/* Interbus EPLD 8 Bit */
#define CFG_CS7_START CFG_IB_EPLD
#define CFG_CS7_SIZE 0x00010000
#define CFG_CS7_CFG 0x00081800
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333333
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
#define CONFIG_IDE_PREINIT 1
/* #define CONFIG_IDE_RESET 1 beispile siehe tqm5200.c */
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CFG_ATA_STRIDE 4
#define CONFIG_ATAPI 1
/*---------------------------------------------------------------------*/
/* Display addresses */
/*---------------------------------------------------------------------*/
#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38)
#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30)
#endif /* __CONFIG_H */

7
include/configs/v38b.h
View file

@ -39,6 +39,7 @@
#define CONFIG_NETCONSOLE 1
#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* do board-specific init */
#define CFG_XLB_PIPELINING 1 /* gives better performance */
@ -101,7 +102,7 @@
CFG_CMD_IRQ | \
CFG_CMD_JFFS2 | \
CFG_CMD_MII | \
CFG_CMD_SDRAMi | \
CFG_CMD_SDRAM | \
CFG_CMD_DATE | \
CFG_CMD_USB | \
CFG_CMD_FAT)
@ -135,7 +136,7 @@
"preboot=echo;echo Type \"run flash_nfs\" to mount root " \
"filesystem over NFS; echo\0" \
"netdev=eth0\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):" \
"$(netmask):$(hostname):$(netdev):off panic=1\0" \
@ -144,7 +145,7 @@
"$(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"nfsroot=$(serverip):$(rootpath) wdt=off\0" \
"hostname=v38b\0" \
"ethact=FEC ETHERNET\0" \
"rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \

14
include/configs/yellowstone.h
View file

@ -301,6 +301,20 @@
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define CFG_FLASH CFG_FLASH_BASE
#define CFG_CPLD 0x80000000
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x03017300
#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000)
/* Memory Bank 2 (CPLD) initialization */
#define CFG_EBC_PB2AP 0x04814500
#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000)
/*-----------------------------------------------------------------------
* Cache Configuration
*/

14
include/configs/yosemite.h
View file

@ -306,6 +306,20 @@
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define CFG_FLASH CFG_FLASH_BASE
#define CFG_CPLD 0x80000000
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x03017300
#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000)
/* Memory Bank 2 (CPLD) initialization */
#define CFG_EBC_PB2AP 0x04814500
#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000)
/*-----------------------------------------------------------------------
* Cache Configuration
*/

9
include/dtt.h
View file

@ -29,6 +29,7 @@
#if defined(CONFIG_DTT_LM75) || \
defined(CONFIG_DTT_DS1621) || \
defined(CONFIG_DTT_LM81) || \
defined(CONFIG_DTT_ADM1021)
#define CONFIG_DTT /* We have a DTT */
@ -58,6 +59,14 @@ extern int dtt_get_temp(int sensor);
#define DTT_TEMP_SET 0x3
#endif
#if defined(CONFIG_DTT_LM81)
#define DTT_READ_TEMP 0x27
#define DTT_CONFIG_TEMP 0x4b
#define DTT_TEMP_MAX 0x39
#define DTT_TEMP_HYST 0x3a
#define DTT_CONFIG 0x40
#endif
#if defined(CONFIG_DTT_DS1621)
#define DTT_READ_TEMP 0xAA
#define DTT_READ_COUNTER 0xA8

1
include/ppc405.h
View file

@ -160,6 +160,7 @@
#define mem_bear 0x10 /* bus error address reg */
#endif
#define mem_mcopt1 0x20 /* memory controller options 1 */
#define mem_status 0x24 /* memory status */
#define mem_rtr 0x30 /* refresh timer reg */
#define mem_pmit 0x34 /* power management idle timer */
#define mem_mb0cf 0x40 /* memory bank 0 configuration */

20
include/ppc440.h
View file

@ -887,12 +887,14 @@
/* PLB4 Arbiter - PowerPC440EP Pass1 */
#define PLB4_DCR_BASE 0x080
#define plb4_acr (PLB4_DCR_BASE+0x1)
#define plb4_revid (PLB4_DCR_BASE+0x2)
#define plb4_acr (PLB4_DCR_BASE+0x3)
#define plb4_besr (PLB4_DCR_BASE+0x4)
#define plb4_bearl (PLB4_DCR_BASE+0x6)
#define plb4_bearh (PLB4_DCR_BASE+0x7)
#define PLB4_ACR_WRP (0x80000000 >> 7)
/* Nebula PLB4 Arbiter - PowerPC440EP */
#define PLB_ARBITER_BASE 0x80
@ -3284,26 +3286,26 @@ typedef struct { unsigned long add; /* gpio core base address */
/*
* Macros for accessing the indirect EBC registers
*/
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
#define mtebc(reg, data) { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); }
#define mfebc(reg, data) { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); }
/*
* Macros for accessing the indirect SDRAM controller registers
*/
#define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
#define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd)
#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); }
#define mfsdram(reg, data) { mtdcr(memcfga,reg);data = mfdcr(memcfgd); }
/*
* Macros for accessing the indirect clocking controller registers
*/
#define mtclk(reg, data) mtdcr(clkcfga,reg);mtdcr(clkcfgd,data)
#define mfclk(reg, data) mtdcr(clkcfga,reg);data = mfdcr(clkcfgd)
#define mtclk(reg, data) { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); }
#define mfclk(reg, data) { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); }
/*
* Macros for accessing the sdr controller registers
*/
#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
#define mtsdr(reg, data) { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); }
#define mfsdr(reg, data) { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); }
#ifndef __ASSEMBLY__

16
lib_ppc/board.c
View file

@ -76,6 +76,10 @@
extern int update_flash_size (int flash_size);
#endif
#if defined(CONFIG_SOLIDCARD3)
extern void sc3_read_eeprom(void);
#endif
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
void doc_init (void);
#endif
@ -93,6 +97,9 @@ static char *failed = "*** failed ***\n";
extern flash_info_t flash_info[];
#endif
#if defined(CONFIG_START_IDE)
extern int board_start_ide(void);
#endif
#include <environment.h>
DECLARE_GLOBAL_DATA_PTR;
@ -815,6 +822,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
#endif /* CONFIG_405GP, CONFIG_405EP */
#endif /* CFG_EXTBDINFO */
#if defined(CONFIG_SOLIDCARD3)
sc3_read_eeprom();
#endif
s = getenv ("ethaddr");
#if defined (CONFIG_MBX) || \
defined (CONFIG_RPXCLASSIC) || \
@ -921,6 +931,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
defined(CONFIG_KUP4X) || \
defined(CONFIG_LWMON) || \
defined(CONFIG_PCU_E) || \
defined(CONFIG_SOLIDCARD3) || \
defined(CONFIG_W7O) || \
defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
@ -1030,7 +1041,12 @@ void board_init_r (gd_t *id, ulong dest_addr)
# else
puts ("IDE: ");
#endif
#if defined(CONFIG_START_IDE)
if (board_start_ide())
ide_init ();
#else
ide_init ();
#endif
#endif /* CFG_CMD_IDE */
#ifdef CONFIG_LAST_STAGE_INIT

2
nand_spl/board/amcc/sequoia/Makefile
View file

@ -76,7 +76,9 @@ $(obj)init.S:
$(obj)sdram.c:
@rm -f $(obj)sdram.c
@rm -f $(obj)sdram.h
ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $(obj)sdram.c
ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)sdram.h
# from nand_spl directory
$(obj)nand_boot.c:

2
rtc/Makefile
View file

@ -29,7 +29,7 @@ LIB = $(obj)librtc.a
COBJS = date.o \
bf533_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \
ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o \
ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o ds3231.o \
m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \
mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o

193
rtc/ds3231.c Normal file
View file

@ -0,0 +1,193 @@
/*
* (C) Copyright 2006
* Markus Klotzbuecher, mk@denx.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
* Extremly Accurate DS3231 Real Time Clock (RTC).
*
* copied from ds1337.c
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
#if defined(CONFIG_RTC_DS3231) && (CONFIG_COMMANDS & CFG_CMD_DATE)
/*---------------------------------------------------------------------*/
#undef DEBUG_RTC
#ifdef DEBUG_RTC
#define DEBUGR(fmt,args...) printf(fmt ,##args)
#else
#define DEBUGR(fmt,args...)
#endif
/*---------------------------------------------------------------------*/
/*
* RTC register addresses
*/
#define RTC_SEC_REG_ADDR 0x0
#define RTC_MIN_REG_ADDR 0x1
#define RTC_HR_REG_ADDR 0x2
#define RTC_DAY_REG_ADDR 0x3
#define RTC_DATE_REG_ADDR 0x4
#define RTC_MON_REG_ADDR 0x5
#define RTC_YR_REG_ADDR 0x6
#define RTC_CTL_REG_ADDR 0x0e
#define RTC_STAT_REG_ADDR 0x0f
/*
* RTC control register bits
*/
#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
/*
* RTC status register bits
*/
#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
static uchar bin2bcd (unsigned int n);
static unsigned bcd2bin (uchar c);
/*
* Get the current time from the RTC
*/
void rtc_get (struct rtc_time *tmp)
{
uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
control = rtc_read (RTC_CTL_REG_ADDR);
status = rtc_read (RTC_STAT_REG_ADDR);
sec = rtc_read (RTC_SEC_REG_ADDR);
min = rtc_read (RTC_MIN_REG_ADDR);
hour = rtc_read (RTC_HR_REG_ADDR);
wday = rtc_read (RTC_DAY_REG_ADDR);
mday = rtc_read (RTC_DATE_REG_ADDR);
mon_cent = rtc_read (RTC_MON_REG_ADDR);
year = rtc_read (RTC_YR_REG_ADDR);
DEBUGR ("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
year, mon_cent, mday, wday, hour, min, sec, control, status);
if (status & RTC_STAT_BIT_OSF) {
printf ("### Warning: RTC oscillator has stopped\n");
/* clear the OSF flag */
rtc_write (RTC_STAT_REG_ADDR,
rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
}
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
tmp->tm_hour = bcd2bin (hour & 0x3F);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
}
/*
* Set the RTC
*/
void rtc_set (struct rtc_time *tmp)
{
uchar century;
DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
century = (tmp->tm_year >= 2000) ? 0x80 : 0;
rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
}
/*
* Reset the RTC. We also enable the oscillator output on the
* SQW/INTB* pin and program it for 32,768 Hz output. Note that
* according to the datasheet, turning on the square wave output
* increases the current drain on the backup battery from about
* 600 nA to 2uA.
*/
void rtc_reset (void)
{
rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2);
}
/*
* Helper functions
*/
static
uchar rtc_read (uchar reg)
{
return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val);
}
static unsigned bcd2bin (uchar n)
{
return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
}
static unsigned char bin2bcd (unsigned int n)
{
return (((n / 10) << 4) | (n % 10));
}
#endif /* (CONFIG_RTC_DS3231) && (CONFIG_COMMANDS & CFG_CMD_DATE) */