thermal: imx_tmu: Move architecture code into driver
Stop polluting the architecture directory with driver specific code, move it into driver where it should be. Split the code slightly so the MX8MM/MX8MN fuse readout and programming and MX8MP fuse readout and programming are in their separate functions, and called in case of matching SoC. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
This commit is contained in:
Marek Vasut
Stefano Babic
parent
114eb2505f
commit
eb1e370a9b
2 changed files with 93 additions and 75 deletions
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@ -1430,79 +1430,6 @@ int arch_misc_init(void)
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}
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#endif
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void imx_tmu_arch_init(void *reg_base)
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{
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if (is_imx8mm() || is_imx8mn()) {
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/* Load TCALIV and TASR from fuses */
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struct ocotp_regs *ocotp =
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(struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[3];
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struct fuse_bank3_regs *fuse =
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(struct fuse_bank3_regs *)bank->fuse_regs;
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u32 tca_rt, tca_hr, tca_en;
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u32 buf_vref, buf_slope;
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tca_rt = fuse->ana0 & 0xFF;
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tca_hr = (fuse->ana0 & 0xFF00) >> 8;
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tca_en = (fuse->ana0 & 0x2000000) >> 25;
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buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
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buf_slope = (fuse->ana0 & 0xF0000) >> 16;
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writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
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writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
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(ulong)reg_base + 0x30);
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}
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#ifdef CONFIG_IMX8MP
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/* Load TCALIV0/1/m40 and TRIM from fuses */
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[38];
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struct fuse_bank38_regs *fuse =
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(struct fuse_bank38_regs *)bank->fuse_regs;
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struct fuse_bank *bank2 = &ocotp->bank[39];
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struct fuse_bank39_regs *fuse2 =
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(struct fuse_bank39_regs *)bank2->fuse_regs;
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u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
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u32 reg;
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u32 tca40[2], tca25[2], tca105[2];
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/* For blank sample */
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if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
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!fuse->ana_trim4 && !fuse2->ana_trim5) {
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/* Use a default 25C binary codes */
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tca25[0] = 1596;
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tca25[1] = 1596;
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writel(tca25[0], (ulong)reg_base + 0x30);
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writel(tca25[1], (ulong)reg_base + 0x34);
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return;
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}
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buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
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buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
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bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
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bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
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vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
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writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
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reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
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writel(reg, (ulong)reg_base + 0x3c);
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tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
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tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
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tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
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tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
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tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
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tca25[1] = fuse2->ana_trim5 & 0xFFF;
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tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
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/* use 25c for 1p calibration */
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writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
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writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
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writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
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#endif
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}
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#if defined(CONFIG_SPL_BUILD)
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#if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
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bool serror_need_skip = true;
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@ -244,8 +244,99 @@ static int imx_tmu_calibration(struct udevice *dev)
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return 0;
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}
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void __weak imx_tmu_arch_init(void *reg_base)
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#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
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static void imx_tmu_mx8mm_mx8mn_init(struct udevice *dev)
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{
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/* Load TCALIV and TASR from fuses */
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struct ocotp_regs *ocotp =
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(struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[3];
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struct fuse_bank3_regs *fuse =
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(struct fuse_bank3_regs *)bank->fuse_regs;
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struct imx_tmu_plat *pdata = dev_get_plat(dev);
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void *reg_base = (void *)pdata->regs;
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u32 tca_rt, tca_hr, tca_en;
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u32 buf_vref, buf_slope;
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tca_rt = fuse->ana0 & 0xFF;
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tca_hr = (fuse->ana0 & 0xFF00) >> 8;
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tca_en = (fuse->ana0 & 0x2000000) >> 25;
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buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
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buf_slope = (fuse->ana0 & 0xF0000) >> 16;
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writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
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writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
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(ulong)reg_base + 0x30);
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}
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#else
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static inline void imx_tmu_mx8mm_mx8mn_init(struct udevice *dev) { }
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#endif
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#if defined(CONFIG_IMX8MP)
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static void imx_tmu_mx8mp_init(struct udevice *dev)
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{
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/* Load TCALIV0/1/m40 and TRIM from fuses */
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[38];
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struct fuse_bank38_regs *fuse =
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(struct fuse_bank38_regs *)bank->fuse_regs;
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struct fuse_bank *bank2 = &ocotp->bank[39];
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struct fuse_bank39_regs *fuse2 =
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(struct fuse_bank39_regs *)bank2->fuse_regs;
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struct imx_tmu_plat *pdata = dev_get_plat(dev);
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void *reg_base = (void *)pdata->regs;
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u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
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u32 reg;
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u32 tca40[2], tca25[2], tca105[2];
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/* For blank sample */
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if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
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!fuse->ana_trim4 && !fuse2->ana_trim5) {
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/* Use a default 25C binary codes */
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tca25[0] = 1596;
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tca25[1] = 1596;
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writel(tca25[0], (ulong)reg_base + 0x30);
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writel(tca25[1], (ulong)reg_base + 0x34);
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return;
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}
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buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
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buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
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bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
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bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
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vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
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writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
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reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
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writel(reg, (ulong)reg_base + 0x3c);
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tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
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tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
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tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
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tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
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tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
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tca25[1] = fuse2->ana_trim5 & 0xFFF;
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tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
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/* use 25c for 1p calibration */
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writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
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writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
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writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
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}
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#else
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static inline void imx_tmu_mx8mp_init(struct udevice *dev) { }
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#endif
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static void imx_tmu_arch_init(struct udevice *dev)
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{
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if (is_imx8mm() || is_imx8mn())
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imx_tmu_mx8mm_mx8mn_init(dev);
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else if (is_imx8mp())
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imx_tmu_mx8mp_init(dev);
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else
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dev_err(dev, "Unsupported SoC, TMU calibration not loaded!\n");
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}
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static void imx_tmu_init(struct udevice *dev)
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@ -279,7 +370,7 @@ static void imx_tmu_init(struct udevice *dev)
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writel(TMTMIR_DEFAULT, &pdata->regs->regs_v1.tmtmir);
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}
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imx_tmu_arch_init((void *)pdata->regs);
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imx_tmu_arch_init(dev);
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}
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static int imx_tmu_enable_msite(struct udevice *dev)
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