From 30c4383da3fa2652e551b0610e71360394aa51e1 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Mon, 10 Dec 2018 20:07:51 +1300 Subject: [PATCH 01/15] ARM: mvebu: sync Armada-38x dts with Linux 4.20 Sync the Armada-38x device tree files with Linux 4.20-rc5. The changes not taken are new compatible strings for the uart and nand flash controller. The nand binding is best updated if/when the mtd/nand infrastructure is updated. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/dts/armada-380.dtsi | 44 +-- arch/arm/dts/armada-385.dtsi | 63 +---- arch/arm/dts/armada-388-clearfog.dts | 25 +- arch/arm/dts/armada-388.dtsi | 43 +-- arch/arm/dts/armada-38x-controlcenterdc.dts | 68 ++--- arch/arm/dts/armada-38x.dtsi | 283 ++++++++++++-------- 6 files changed, 237 insertions(+), 289 deletions(-) diff --git a/arch/arm/dts/armada-380.dtsi b/arch/arm/dts/armada-380.dtsi index 5102d19cc8..cff1269f3f 100644 --- a/arch/arm/dts/armada-380.dtsi +++ b/arch/arm/dts/armada-380.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 380 SoC. * @@ -6,44 +7,6 @@ * Lior Amsalem * Gregory CLEMENT * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "armada-38x.dtsi" @@ -71,7 +34,7 @@ }; }; - pcie-controller { + pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci"; @@ -104,6 +67,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>; @@ -122,6 +86,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>; @@ -140,6 +105,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>; diff --git a/arch/arm/dts/armada-385.dtsi b/arch/arm/dts/armada-385.dtsi index 8e67d2c083..f0022d10c7 100644 --- a/arch/arm/dts/armada-385.dtsi +++ b/arch/arm/dts/armada-385.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 385 SoC. * @@ -6,44 +7,6 @@ * Lior Amsalem * Gregory CLEMENT * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "armada-38x.dtsi" @@ -70,13 +33,7 @@ }; soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6820-pinctrl"; - }; - }; - - pcie-controller { + pciec: pcie { compatible = "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci"; @@ -106,7 +63,7 @@ * configured in x4 by the bootloader, then * pcie@4,0 is not available. */ - pcie@1,0 { + pcie1: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -115,6 +72,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <0>; @@ -124,7 +82,7 @@ }; /* x1 port */ - pcie@2,0 { + pcie2: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x1000 0 0 0 0>; @@ -133,6 +91,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <1>; @@ -142,7 +101,7 @@ }; /* x1 port */ - pcie@3,0 { + pcie3: pcie@3,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; reg = <0x1800 0 0 0 0>; @@ -151,6 +110,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <2>; @@ -163,7 +123,7 @@ * x1 port only available when pcie@1,0 is * configured as a x1 port */ - pcie@4,0 { + pcie4: pcie@4,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; reg = <0x2000 0 0 0 0>; @@ -172,6 +132,7 @@ #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; + bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; marvell,pcie-port = <3>; @@ -182,3 +143,7 @@ }; }; }; + +&pinctrl { + compatible = "marvell,mv88f6820-pinctrl"; +}; diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts index 16a47d59e6..a3493ddd4d 100644 --- a/arch/arm/dts/armada-388-clearfog.dts +++ b/arch/arm/dts/armada-388-clearfog.dts @@ -118,18 +118,7 @@ status = "okay"; }; - spi1: spi@10680 { - /* - * CS0: W25Q32 - * CS1: - * CS2: mikrobus - */ - pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>; - pinctrl-names = "default"; - status = "okay"; - }; - - usb0: usb3@f8000 { + usb3@f8000 { /* CON7, USB-A port on back of device */ status = "okay"; }; @@ -322,6 +311,18 @@ }; }; +&spi1 { + /* + * Add SPI CS pins for clearfog: + * CS0: W25Q32 + * CS1: + * CS2: mikrobus + */ + pinctrl-0 = <&spi1_pins &mikro_spi_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + /* +#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011 MPP18: gpio ? (pca9655 int?) diff --git a/arch/arm/dts/armada-388.dtsi b/arch/arm/dts/armada-388.dtsi index 564fa5937e..f3a020ff57 100644 --- a/arch/arm/dts/armada-388.dtsi +++ b/arch/arm/dts/armada-388.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 388 SoC. * @@ -5,39 +6,6 @@ * * Gregory CLEMENT * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * * The main difference with the Armada 385 is that the 388 can handle two more * SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl * property and the name of the SoC, and add the second SATA host which control @@ -50,13 +18,8 @@ model = "Marvell Armada 388 family SoC"; compatible = "marvell,armada388", "marvell,armada385", "marvell,armada380"; - soc { internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6828-pinctrl"; - }; - sata@e0000 { compatible = "marvell,armada-380-ahci"; reg = <0xe0000 0x2000>; @@ -68,3 +31,7 @@ }; }; }; + +&pinctrl { + compatible = "marvell,mv88f6828-pinctrl"; +}; diff --git a/arch/arm/dts/armada-38x-controlcenterdc.dts b/arch/arm/dts/armada-38x-controlcenterdc.dts index 2cc996876a..ffbd0dcaae 100644 --- a/arch/arm/dts/armada-38x-controlcenterdc.dts +++ b/arch/arm/dts/armada-38x-controlcenterdc.dts @@ -72,40 +72,6 @@ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; internal-regs { - spi0: spi@10600 { - status = "okay"; - sc16is741: sc16is741@0 { - compatible = "nxp,sc16is741"; - reg = <0>; - clocks = <&sc16isclk>; - spi-max-frequency = <4000000>; - interrupt-parent = <&gpio0>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - gpio-controller; - #gpio-cells = <2>; - }; - }; - - spi1: spi@10680 { - status = "okay"; - u-boot,dm-pre-reloc; - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q016a", "spi-flash"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - spi-flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a11", "spi-flash"; - reg = <1>; /* Chip select 1 */ - spi-max-frequency = <108000000>; - u-boot,dm-pre-reloc; - }; - }; - I2C0: i2c@11000 { status = "okay"; clock-frequency = <1000000>; @@ -586,3 +552,37 @@ }; }; }; + +&spi0 { + status = "okay"; + sc16is741: sc16is741@0 { + compatible = "nxp,sc16is741"; + reg = <0>; + clocks = <&sc16isclk>; + spi-max-frequency = <4000000>; + interrupt-parent = <&gpio0>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&spi1 { + status = "okay"; + u-boot,dm-pre-reloc; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q016a", "spi-flash"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; + spi-flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a11", "spi-flash"; + reg = <1>; /* Chip select 1 */ + spi-max-frequency = <108000000>; + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi index 5e5a158551..72c49beb71 100644 --- a/arch/arm/dts/armada-38x.dtsi +++ b/arch/arm/dts/armada-38x.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Device Tree Include file for Marvell Armada 38x family of SoCs. * @@ -6,44 +7,6 @@ * Lior Amsalem * Gregory CLEMENT * Thomas Petazzoni - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include "skeleton.dtsi" @@ -83,7 +46,7 @@ reg = ; }; - devbus-bootcs { + devbus_bootcs: devbus-bootcs { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; @@ -93,7 +56,7 @@ status = "disabled"; }; - devbus-cs0 { + devbus_cs0: devbus-cs0 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; @@ -103,7 +66,7 @@ status = "disabled"; }; - devbus-cs1 { + devbus_cs1: devbus-cs1 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; @@ -113,7 +76,7 @@ status = "disabled"; }; - devbus-cs2 { + devbus_cs2: devbus-cs2 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; @@ -123,7 +86,7 @@ status = "disabled"; }; - devbus-cs3 { + devbus_cs3: devbus-cs3 { compatible = "marvell,mvebu-devbus"; reg = ; ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; @@ -145,6 +108,10 @@ reg = <0x8000 0x1000>; cache-unified; cache-level = <2>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <0>; + arm,double-linefill = <0>; + prefetch-data = <1>; }; scu@c000 { @@ -152,6 +119,13 @@ reg = <0xc000 0x58>; }; + timer@c200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xc200 0x20>; + interrupts = ; + clocks = <&coreclk 2>; + }; + timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; @@ -168,32 +142,8 @@ <0xc100 0x100>; }; - spi0: spi@10600 { - compatible = "marvell,armada-380-spi", - "marvell,orion-spi"; - reg = <0x10600 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-380-spi", - "marvell,orion-spi"; - reg = <0x10680 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; + compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; #address-cells = <1>; #size-cells = <0>; @@ -204,7 +154,7 @@ }; i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; + compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; reg = <0x11100 0x20>; #address-cells = <1>; #size-cells = <0>; @@ -258,19 +208,6 @@ marvell,function = "i2c0"; }; - nand_pins: nand-pins { - marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", - "mpp38", "mpp28", "mpp40", "mpp42", - "mpp35", "mpp36", "mpp25", "mpp30", - "mpp32"; - marvell,function = "dev"; - }; - - nand_rb: nand-rb { - marvell,pins = "mpp41"; - marvell,function = "nand"; - }; - mdio_pins: mdio-pins { marvell,pins = "mpp4", "mpp5"; marvell,function = "ge"; @@ -298,6 +235,20 @@ marvell,function = "spi1"; }; + nand_pins: nand-pins { + marvell,pins = "mpp22", "mpp34", "mpp23", + "mpp33", "mpp38", "mpp28", + "mpp40", "mpp42", "mpp35", + "mpp36", "mpp25", "mpp30", + "mpp32"; + marvell,function = "dev"; + }; + + nand_rb: nand-rb { + marvell,pins = "mpp41"; + marvell,function = "nand"; + }; + uart0_pins: uart-pins-0 { marvell,pins = "mpp0", "mpp1"; marvell,function = "ua0"; @@ -338,34 +289,42 @@ }; gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; - reg = <0x18100 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18100 0x40>, <0x181c0 0x08>; + reg-names = "gpio", "pwm"; ngpios = <32>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = , , , ; + clocks = <&coreclk 0>; }; gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; - reg = <0x18140 0x40>; + compatible = "marvell,armada-370-gpio", + "marvell,orion-gpio"; + reg = <0x18140 0x40>, <0x181c8 0x08>; + reg-names = "gpio", "pwm"; ngpios = <28>; gpio-controller; #gpio-cells = <2>; + #pwm-cells = <2>; interrupt-controller; #interrupt-cells = <2>; interrupts = , , , ; + clocks = <&coreclk 0>; }; - system-controller@18200 { + systemc: system-controller@18200 { compatible = "marvell,armada-380-system-controller", "marvell,armada-370-xp-system-controller"; reg = <0x18200 0x100>; @@ -386,7 +345,8 @@ mbusc: mbus-controller@20000 { compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>; + reg = <0x20000 0x100>, <0x20180 0x20>, + <0x20250 0x8>; }; mpic: interrupt-controller@20a00 { @@ -399,7 +359,7 @@ interrupts = ; }; - timer@20300 { + timer: timer@20300 { compatible = "marvell,armada-380-timer", "marvell,armada-xp-timer"; reg = <0x20300 0x30>, <0x21040 0x30>; @@ -413,14 +373,14 @@ clock-names = "nbclk", "fixed"; }; - watchdog@20300 { + watchdog: watchdog@20300 { compatible = "marvell,armada-380-wdt"; reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; clocks = <&coreclk 2>, <&refclk>; clock-names = "nbclk", "fixed"; }; - cpurst@20800 { + cpurst: cpurst@20800 { compatible = "marvell,armada-370-cpu-reset"; reg = <0x20800 0x10>; }; @@ -430,16 +390,37 @@ reg = <0x20d20 0x6c>; }; - coherency-fabric@21010 { + coherencyfab: coherency-fabric@21010 { compatible = "marvell,armada-380-coherency-fabric"; reg = <0x21010 0x1c>; }; - pmsu@22000 { + pmsu: pmsu@22000 { compatible = "marvell,armada-380-pmsu"; reg = <0x22000 0x1000>; }; + /* + * As a special exception to the "order by + * register address" rule, the eth0 node is + * placed here to ensure that it gets + * registered as the first interface, since + * the network subsystem doesn't allow naming + * interfaces using DT aliases. Without this, + * the ordering of interfaces is different + * from the one used in U-Boot and the + * labeling of interfaces on the boards, which + * is very confusing for users. + */ + eth0: ethernet@70000 { + compatible = "marvell,armada-370-neta"; + reg = <0x70000 0x4000>; + interrupts-extended = <&mpic 8>; + clocks = <&gateclk 4>; + tx-csum-limit = <9800>; + status = "disabled"; + }; + eth1: ethernet@30000 { compatible = "marvell,armada-370-neta"; reg = <0x30000 0x4000>; @@ -456,7 +437,7 @@ status = "disabled"; }; - usb@58000 { + usb0: usb@58000 { compatible = "marvell,orion-ehci"; reg = <0x58000 0x500>; interrupts = ; @@ -464,8 +445,8 @@ status = "disabled"; }; - xor@60800 { - compatible = "marvell,orion-xor"; + xor0: xor@60800 { + compatible = "marvell,armada-380-xor", "marvell,orion-xor"; reg = <0x60800 0x100 0x60a00 0x100>; clocks = <&gateclk 22>; @@ -484,8 +465,8 @@ }; }; - xor@60900 { - compatible = "marvell,orion-xor"; + xor1: xor@60900 { + compatible = "marvell,armada-380-xor", "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; clocks = <&gateclk 28>; @@ -504,14 +485,6 @@ }; }; - eth0: ethernet@70000 { - compatible = "marvell,armada-370-neta"; - reg = <0x70000 0x4000>; - interrupts-extended = <&mpic 8>; - clocks = <&gateclk 4>; - status = "disabled"; - }; - mdio: mdio@72004 { #address-cells = <1>; #size-cells = <0>; @@ -520,14 +493,29 @@ clocks = <&gateclk 4>; }; - rtc@a3800 { + cesa: crypto@90000 { + compatible = "marvell,armada-38x-crypto"; + reg = <0x90000 0x10000>; + reg-names = "regs"; + interrupts = , + ; + clocks = <&gateclk 23>, <&gateclk 21>, + <&gateclk 14>, <&gateclk 16>; + clock-names = "cesa0", "cesa1", + "cesaz0", "cesaz1"; + marvell,crypto-srams = <&crypto_sram0>, + <&crypto_sram1>; + marvell,crypto-sram-size = <0x800>; + }; + + rtc: rtc@a3800 { compatible = "marvell,armada-380-rtc"; reg = <0xa3800 0x20>, <0x184a0 0x0c>; reg-names = "rtc", "rtc-soc"; interrupts = ; }; - sata@a8000 { + ahci0: sata@a8000 { compatible = "marvell,armada-380-ahci"; reg = <0xa8000 0x2000>; interrupts = ; @@ -535,7 +523,15 @@ status = "disabled"; }; - sata@e0000 { + bm: bm@c8000 { + compatible = "marvell,armada-380-neta-bm"; + reg = <0xc8000 0xac>; + clocks = <&gateclk 13>; + internal-mem = <&bm_bppi>; + status = "disabled"; + }; + + ahci1: sata@e0000 { compatible = "marvell,armada-380-ahci"; reg = <0xe0000 0x2000>; interrupts = ; @@ -551,23 +547,23 @@ clock-output-names = "nand"; }; - thermal@e8078 { + thermal: thermal@e8078 { compatible = "marvell,armada380-thermal"; - reg = <0xe4078 0x4>, <0xe4074 0x4>; + reg = <0xe4078 0x4>, <0xe4070 0x8>; status = "okay"; }; - flash@d0000 { + nand_controller: nand-controller@d0000 { compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand"; reg = <0xd0000 0x54>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; interrupts = ; clocks = <&coredivclk 0>; status = "disabled"; }; - sdhci@d8000 { + sdhci: sdhci@d8000 { compatible = "marvell,armada-380-sdhci"; reg-names = "sdhci", "mbus", "conf-sdio3"; reg = <0xd8000 0x1000>, @@ -579,7 +575,7 @@ status = "disabled"; }; - usb3@f0000 { + usb3_0: usb3@f0000 { compatible = "marvell,armada-380-xhci"; reg = <0xf0000 0x4000>,<0xf4000 0x4000>; interrupts = ; @@ -587,7 +583,7 @@ status = "disabled"; }; - usb3@f8000 { + usb3_1: usb3@f8000 { compatible = "marvell,armada-380-xhci"; reg = <0xf8000 0x4000>,<0xfc000 0x4000>; interrupts = ; @@ -595,10 +591,63 @@ status = "disabled"; }; }; + + crypto_sram0: sa-sram0 { + compatible = "mmio-sram"; + reg = ; + clocks = <&gateclk 23>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>; + }; + + crypto_sram1: sa-sram1 { + compatible = "mmio-sram"; + reg = ; + clocks = <&gateclk 21>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>; + }; + + bm_bppi: bm-bppi { + compatible = "mmio-sram"; + reg = ; + ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gateclk 13>; + no-memory-wc; + status = "disabled"; + }; + + spi0: spi@10600 { + compatible = "marvell,armada-380-spi", + "marvell,orion-spi"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,armada-380-spi", + "marvell,orion-spi"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; }; clocks { - /* 2 GHz fixed main PLL */ + /* 1 GHz fixed main PLL */ mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; From 296c64ea4147aa621e3ab4f42b2c43cc8a91991a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 17 Dec 2018 16:10:01 +0100 Subject: [PATCH 02/15] arm: mvebu: turris_mox: Cosmetic restructurization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Restructure the board initialization source. Remove the module_topology environment variable since it won't be needed. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- board/CZ.NIC/turris_mox/turris_mox.c | 150 +++++++++++++++++---------- 1 file changed, 96 insertions(+), 54 deletions(-) diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index c4622a49c2..415c462493 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -135,17 +135,15 @@ int board_init(void) return 0; } -int last_stage_init(void) +static int mox_do_spi(u8 *in, u8 *out, size_t size) { struct spi_slave *slave; struct udevice *dev; - u8 din[10], dout[10]; - int ret, i; - size_t len = 0; - char module_topology[128]; + int ret; - ret = spi_get_bus_and_cs(0, 1, 20000000, SPI_CPHA, "spi_generic_drv", - "mox-modules@1", &dev, &slave); + ret = spi_get_bus_and_cs(0, 1, 1000000, SPI_CPHA | SPI_CPOL, + "spi_generic_drv", "moxtet@1", &dev, + &slave); if (ret) goto fail; @@ -153,57 +151,101 @@ int last_stage_init(void) if (ret) goto fail_free; - memset(din, 0, 10); - memset(dout, 0, 10); + ret = spi_xfer(slave, size * 8, out, in, SPI_XFER_ONCE); - ret = spi_xfer(slave, 80, dout, din, SPI_XFER_ONCE); - if (ret) - goto fail_release; - - if (din[0] != 0x00 && din[0] != 0xff) - goto fail_release; - - printf("Module Topology:\n"); - for (i = 1; i < 10 && din[i] != 0xff; ++i) { - u8 mid = din[i] & 0xf; - size_t mlen; - const char *mname = ""; - - switch (mid) { - case 0x1: - mname = "sfp-"; - printf("% 4i: SFP Module\n", i); - break; - case 0x2: - mname = "pci-"; - printf("% 4i: Mini-PCIe Module\n", i); - break; - case 0x3: - mname = "topaz-"; - printf("% 4i: Topaz Switch Module\n", i); - break; - default: - printf("% 4i: unknown (ID %i)\n", i, mid); - } - - mlen = strlen(mname); - if (len + mlen < sizeof(module_topology)) { - strcpy(module_topology + len, mname); - len += mlen; - } - } - printf("\n"); - - module_topology[len > 0 ? len - 1 : 0] = '\0'; - - env_set("module_topology", module_topology); - -fail_release: spi_release_bus(slave); fail_free: spi_free_slave(slave); fail: - if (ret) - printf("Cannot read module topology!\n"); return ret; } + +static int mox_get_topology(const u8 **ptopology, int *psize, int *pis_sd) +{ + static int is_sd; + static u8 topology[MAX_MOX_MODULES - 1]; + static int size; + u8 din[MAX_MOX_MODULES], dout[MAX_MOX_MODULES]; + int ret, i; + + if (size) { + if (ptopology) + *ptopology = topology; + if (psize) + *psize = size; + if (pis_sd) + *pis_sd = is_sd; + return 0; + } + + memset(din, 0, MAX_MOX_MODULES); + memset(dout, 0, MAX_MOX_MODULES); + + ret = mox_do_spi(din, dout, MAX_MOX_MODULES); + if (ret) + return ret; + + if (din[0] == 0x10) + is_sd = 1; + else if (din[0] == 0x00) + is_sd = 0; + else + return -ENODEV; + + for (i = 1; i < MAX_MOX_MODULES && din[i] != 0xff; ++i) + topology[i - 1] = din[i] & 0xf; + size = i - 1; + + if (ptopology) + *ptopology = topology; + if (psize) + *psize = size; + if (pis_sd) + *pis_sd = is_sd; + + return 0; +} + +int last_stage_init(void) +{ + int ret, i; + const u8 *topology; + int module_count, is_sd; + + ret = mox_get_topology(&topology, &module_count, &is_sd); + if (ret) { + printf("Cannot read module topology!\n"); + return 0; + } + + printf("Found Turris Mox %s version\n", is_sd ? "SD" : "eMMC"); + printf("Module Topology:\n"); + for (i = 0; i < module_count; ++i) { + switch (topology[i]) { + case MOX_MODULE_SFP: + printf("% 4i: SFP Module\n", i + 1); + break; + case MOX_MODULE_PCI: + printf("% 4i: Mini-PCIe Module\n", i + 1); + break; + case MOX_MODULE_TOPAZ: + printf("% 4i: Topaz Switch Module (4-port)\n", i + 1); + break; + case MOX_MODULE_PERIDOT: + printf("% 4i: Peridot Switch Module (8-port)\n", i + 1); + break; + case MOX_MODULE_USB3: + printf("% 4i: USB 3.0 Module (4 ports)\n", i + 1); + break; + case MOX_MODULE_PASSPCI: + printf("% 4i: Passthrough Mini-PCIe Module\n", i + 1); + break; + default: + printf("% 4i: unknown (ID %i)\n", i + 1, topology[i]); + } + } + + printf("\n"); + + return 0; +} From 9433cd1109ae61b2676ed4832ae75da79ec9083d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 17 Dec 2018 16:10:02 +0100 Subject: [PATCH 03/15] arm: mvebu: turris_mox: Change SERDES map depending on module topology MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When SFP module is connected directly to CPU module we want the SGMII lane speed at 1.25 Gbps. This is a temporary solution till there is a comphy driver in the kernel capable of changing SGMII speed at runtime. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- board/CZ.NIC/turris_mox/turris_mox.c | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 415c462493..3c0ab58756 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -206,6 +207,38 @@ static int mox_get_topology(const u8 **ptopology, int *psize, int *pis_sd) return 0; } +int comphy_update_map(struct comphy_map *serdes_map, int count) +{ + int ret, i, size, sfpindex = -1, swindex = -1; + const u8 *topology; + + ret = mox_get_topology(&topology, &size, NULL); + if (ret) + return ret; + + for (i = 0; i < size; ++i) { + if (topology[i] == MOX_MODULE_SFP && sfpindex == -1) + sfpindex = i; + else if ((topology[i] == MOX_MODULE_TOPAZ || + topology[i] == MOX_MODULE_PERIDOT) && + swindex == -1) + swindex = i; + } + + if (sfpindex >= 0 && swindex >= 0) { + if (sfpindex < swindex) + serdes_map[0].speed = PHY_SPEED_1_25G; + else + serdes_map[0].speed = PHY_SPEED_3_125G; + } else if (sfpindex >= 0) { + serdes_map[0].speed = PHY_SPEED_1_25G; + } else if (swindex >= 0) { + serdes_map[0].speed = PHY_SPEED_3_125G; + } + + return 0; +} + int last_stage_init(void) { int ret, i; From 7dd7c2e796ca6481c9341cf9df0328bdb5bd9fd8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 17 Dec 2018 16:10:03 +0100 Subject: [PATCH 04/15] arm: mvebu: turris_mox: Check and configure modules MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Check if Mox modules are connected in supported mode, then configure the MDIO addresses of switch modules. Signed-off-by: Marek Behún Signed-off-by: Stefan Roese --- arch/arm/dts/armada-3720-turris-mox.dts | 11 ++ board/CZ.NIC/turris_mox/turris_mox.c | 234 +++++++++++++++++++++++- 2 files changed, 244 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts index 7babc16679..ff54ce5d0f 100644 --- a/arch/arm/dts/armada-3720-turris-mox.dts +++ b/arch/arm/dts/armada-3720-turris-mox.dts @@ -110,6 +110,17 @@ spi-max-frequency = <20000000>; m25p,fast-read; }; + + moxtet@1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cznic,moxtet"; + reg = <1>; + reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; + spi-max-frequency = <1000000>; + spi-cpol; + spi-cpha; + }; }; &uart0 { diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 3c0ab58756..4426ee3446 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -4,11 +4,13 @@ */ #include +#include #include #include #include #include #include +#include #include #include #include @@ -239,11 +241,138 @@ int comphy_update_map(struct comphy_map *serdes_map, int count) return 0; } +#define SW_SMI_CMD_R(d, r) (0x9800 | (((d) & 0x1f) << 5) | ((r) & 0x1f)) +#define SW_SMI_CMD_W(d, r) (0x9400 | (((d) & 0x1f) << 5) | ((r) & 0x1f)) + +static int sw_multi_read(struct mii_dev *bus, int sw, int dev, int reg) +{ + bus->write(bus, sw, 0, 0, SW_SMI_CMD_R(dev, reg)); + mdelay(5); + return bus->read(bus, sw, 0, 1); +} + +static void sw_multi_write(struct mii_dev *bus, int sw, int dev, int reg, + u16 val) +{ + bus->write(bus, sw, 0, 1, val); + bus->write(bus, sw, 0, 0, SW_SMI_CMD_W(dev, reg)); + mdelay(5); +} + +static int sw_scratch_read(struct mii_dev *bus, int sw, int reg) +{ + sw_multi_write(bus, sw, 0x1c, 0x1a, (reg & 0x7f) << 8); + return sw_multi_read(bus, sw, 0x1c, 0x1a) & 0xff; +} + +static void sw_led_write(struct mii_dev *bus, int sw, int port, int reg, + u16 val) +{ + sw_multi_write(bus, sw, port, 0x16, 0x8000 | ((reg & 7) << 12) + | (val & 0x7ff)); +} + +static void sw_blink_leds(struct mii_dev *bus, int peridot, int topaz) +{ + int i, p; + struct { + int port; + u16 val; + int wait; + } regs[] = { + { 2, 0xef, 1 }, { 2, 0xfe, 1 }, { 2, 0x33, 0 }, + { 4, 0xef, 1 }, { 4, 0xfe, 1 }, { 4, 0x33, 0 }, + { 3, 0xfe, 1 }, { 3, 0xef, 1 }, { 3, 0x33, 0 }, + { 1, 0xfe, 1 }, { 1, 0xef, 1 }, { 1, 0x33, 0 } + }; + + for (i = 0; i < 12; ++i) { + for (p = 0; p < peridot; ++p) { + sw_led_write(bus, 0x10 + p, regs[i].port, 0, + regs[i].val); + sw_led_write(bus, 0x10 + p, regs[i].port + 4, 0, + regs[i].val); + } + if (topaz) { + sw_led_write(bus, 0x2, 0x10 + regs[i].port, 0, + regs[i].val); + } + + if (regs[i].wait) + mdelay(75); + } +} + +static void check_switch_address(struct mii_dev *bus, int addr) +{ + if (sw_scratch_read(bus, addr, 0x70) >> 3 != addr) + printf("Check of switch MDIO address failed for 0x%02x\n", + addr); +} + +static int sfp, pci, topaz, peridot, usb, passpci; +static int sfp_pos, peridot_pos[3]; +static int module_count; + +static int configure_peridots(struct gpio_desc *reset_gpio) +{ + int i, ret; + u8 dout[MAX_MOX_MODULES]; + + memset(dout, 0, MAX_MOX_MODULES); + + /* set addresses of Peridot modules */ + for (i = 0; i < peridot; ++i) + dout[module_count - peridot_pos[i]] = (~i) & 3; + + /* + * if there is a SFP module connected to the last Peridot module, set + * the P10_SMODE to 1 for the Peridot module + */ + if (sfp) + dout[module_count - peridot_pos[i - 1]] |= 1 << 3; + + dm_gpio_set_value(reset_gpio, 1); + mdelay(10); + + ret = mox_do_spi(NULL, dout, module_count + 1); + + mdelay(10); + dm_gpio_set_value(reset_gpio, 0); + + mdelay(50); + + return ret; +} + +static int get_reset_gpio(struct gpio_desc *reset_gpio) +{ + int node; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "cznic,moxtet"); + if (node < 0) { + printf("Cannot find Moxtet bus device node!\n"); + return -1; + } + + gpio_request_by_name_nodev(offset_to_ofnode(node), "reset-gpios", 0, + reset_gpio, GPIOD_IS_OUT); + + if (!dm_gpio_is_valid(reset_gpio)) { + printf("Cannot find reset GPIO for Moxtet bus!\n"); + return -1; + } + + return 0; +} + int last_stage_init(void) { int ret, i; const u8 *topology; - int module_count, is_sd; + int is_sd; + struct mii_dev *bus; + struct gpio_desc reset_gpio = {}; ret = mox_get_topology(&topology, &module_count, &is_sd); if (ret) { @@ -278,6 +407,109 @@ int last_stage_init(void) } } + /* now check if modules are connected in supported mode */ + + for (i = 0; i < module_count; ++i) { + switch (topology[i]) { + case MOX_MODULE_SFP: + if (sfp) { + printf("Error: Only one SFP module is supported!\n"); + } else if (topaz) { + printf("Error: SFP module cannot be connected after Topaz Switch module!\n"); + } else { + sfp_pos = i; + ++sfp; + } + break; + case MOX_MODULE_PCI: + if (pci) { + printf("Error: Only one Mini-PCIe module is supported!\n"); + } else if (usb) { + printf("Error: Mini-PCIe module cannot come after USB 3.0 module!\n"); + } else if (i && (i != 1 || !passpci)) { + printf("Error: Mini-PCIe module should be the first connected module or come right after Passthrough Mini-PCIe module!\n"); + } else { + ++pci; + } + break; + case MOX_MODULE_TOPAZ: + if (topaz) { + printf("Error: Only one Topaz module is supported!\n"); + } else if (peridot >= 3) { + printf("Error: At most two Peridot modules can come before Topaz module!\n"); + } else { + ++topaz; + } + break; + case MOX_MODULE_PERIDOT: + if (sfp || topaz) { + printf("Error: Peridot module must come before SFP or Topaz module!\n"); + } else if (peridot >= 3) { + printf("Error: At most three Peridot modules are supported!\n"); + } else { + peridot_pos[peridot] = i; + ++peridot; + } + break; + case MOX_MODULE_USB3: + if (pci) { + printf("Error: USB 3.0 module cannot come after Mini-PCIe module!\n"); + } else if (usb) { + printf("Error: Only one USB 3.0 module is supported!\n"); + } else if (i && (i != 1 || !passpci)) { + printf("Error: USB 3.0 module should be the first connected module or come right after Passthrough Mini-PCIe module!\n"); + } else { + ++usb; + } + break; + case MOX_MODULE_PASSPCI: + if (passpci) { + printf("Error: Only one Passthrough Mini-PCIe module is supported!\n"); + } else if (i != 0) { + printf("Error: Passthrough Mini-PCIe module should be the first connected module!\n"); + } else { + ++passpci; + } + } + } + + /* now configure modules */ + + if (get_reset_gpio(&reset_gpio) < 0) + return 0; + + if (peridot > 0) { + if (configure_peridots(&reset_gpio) < 0) { + printf("Cannot configure Peridot modules!\n"); + peridot = 0; + } + } else { + dm_gpio_set_value(&reset_gpio, 1); + mdelay(50); + dm_gpio_set_value(&reset_gpio, 0); + mdelay(50); + } + + if (peridot || topaz) { + /* + * now check if the addresses are set by reading Scratch & Misc + * register 0x70 of Peridot (and potentially Topaz) modules + */ + + bus = miiphy_get_dev_by_name("neta@30000"); + if (!bus) { + printf("Cannot get MDIO bus device!\n"); + } else { + for (i = 0; i < peridot; ++i) + check_switch_address(bus, 0x10 + i); + + if (topaz) + check_switch_address(bus, 0x2); + + sw_blink_leds(bus, peridot, topaz); + } + } + printf("\n"); return 0; From 3dc2f4549c92981b38ec49717f984877e3c65868 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 17 Dec 2018 16:10:04 +0100 Subject: [PATCH 05/15] arm: mvebu: dts: Fix Turris Mox device tree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DTC issues a warning because #address-cells and #size-cells properties are not set in the mdio node. Also add ethernet1 alias. Also add RTC node. Also fix USB3 regulator startup delay time. Also fix PCI Express SERDES speed to 5 GHz (this is only cosmetic, the speed value is not used byt the comphy driver for PCI Express, but should be 5 GHz nonetheless). Signed-off-by: Marek Behún Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- arch/arm/dts/armada-3720-turris-mox.dts | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts index ff54ce5d0f..14bec0977e 100644 --- a/arch/arm/dts/armada-3720-turris-mox.dts +++ b/arch/arm/dts/armada-3720-turris-mox.dts @@ -24,6 +24,7 @@ aliases { ethernet0 = ð0; + ethernet1 = ð1; i2c0 = &i2c0; spi0 = &spi0; }; @@ -38,12 +39,16 @@ regulator-name = "usb3-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + startup-delay-us = <2000000>; shutdown-delay-us = <1000000>; gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; regulator-boot-on; }; mdio { + #address-cells = <1>; + #size-cells = <0>; + eth_phy1: ethernet-phy@1 { reg = <1>; }; @@ -59,7 +64,7 @@ phy1 { phy-type = ; - phy-speed = ; + phy-speed = ; }; phy2 { @@ -80,6 +85,11 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; status = "okay"; + + rtc@6f { + compatible = "microchip,mcp7941x"; + reg = <0x6f>; + }; }; &sdhci1 { From 6e8e1dcf7dc9e6c143fac601cc2d8d5180b67bba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 17 Dec 2018 16:10:05 +0100 Subject: [PATCH 06/15] arm: mvebu: turris_mox: Update defconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add gpio command to defconfig - this can be used to detect whether the button is pressed or light LEDs. Add DS1307 RTC driver and the date command. Add CONFIG_WATCHDOG, so that U-Boot calls watchdog_reset. Add CONFIG_MISC_INIT_R so that ethernet addresses are read from OTP before network controller is initialized. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- configs/turris_mox_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index c428bba5c9..d9b87ecb7c 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -13,7 +13,9 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_EARLY_INIT_R=y +CONFIG_MISC_INIT_R=y CONFIG_CMD_CLK=y +CONFIG_CMD_GPIO=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -24,6 +26,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y +CONFIG_CMD_DATE=y CONFIG_CMD_TIME=y CONFIG_CMD_MVEBU_BUBT=y CONFIG_CMD_BTRFS=y @@ -63,6 +66,8 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_MVEBU_A3700_UART=y CONFIG_MVEBU_A3700_SPI=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y @@ -72,6 +77,7 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_WATCHDOG=y CONFIG_WDT=y CONFIG_WDT_ARMADA_37XX=y CONFIG_SHA1=y From 7b03e9969c411fac5ebeb86adc306d2c25ca2170 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 17 Dec 2018 16:10:06 +0100 Subject: [PATCH 07/15] watchdog: armada_37xx: Fix compliance with kernel's driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Armada 37xx watchdog driver was recently accepted for mainline kernel by watchdog subsystem maintainer, but the driver works a little different than the one in U-Boot. This patch fixes this. In the previous implementation there was a tiny period of time when the watchdog was disabled and the system was vulnerables - this was during pinging, which was done by disabling, setting, and enabling the counter. Now pinging is done without disabling the watchdog. We use 2 counters: Counter 1 is the watchdog counter - on expiry, the system is reset. Counter 0 is used to reset Counter 1 to start counting from the set timeout again. So Counter 1 is set to be reset on Counter 0 expiry event event and pinging is done by forcing an immediate expiry event on Counter 0. Signed-off-by: Marek Behún Signed-off-by: Stefan Roese --- drivers/watchdog/armada-37xx-wdt.c | 111 ++++++++++++++++++----------- 1 file changed, 68 insertions(+), 43 deletions(-) diff --git a/drivers/watchdog/armada-37xx-wdt.c b/drivers/watchdog/armada-37xx-wdt.c index 0fa4fda4fc..91cd8a6e6a 100644 --- a/drivers/watchdog/armada-37xx-wdt.c +++ b/drivers/watchdog/armada-37xx-wdt.c @@ -22,42 +22,63 @@ struct a37xx_wdt { }; /* - * We use Counter 1 for watchdog timer, because so does Marvell's Linux by - * default. + * We use Counter 1 as watchdog timer, and Counter 0 for re-triggering Counter 1 */ -#define CNTR_CTRL 0x10 +#define CNTR_CTRL(id) ((id) * 0x10) #define CNTR_CTRL_ENABLE 0x0001 #define CNTR_CTRL_ACTIVE 0x0002 #define CNTR_CTRL_MODE_MASK 0x000c #define CNTR_CTRL_MODE_ONESHOT 0x0000 +#define CNTR_CTRL_MODE_HWSIG 0x000c +#define CNTR_CTRL_TRIG_SRC_MASK 0x00f0 +#define CNTR_CTRL_TRIG_SRC_PREV_CNTR 0x0050 #define CNTR_CTRL_PRESCALE_MASK 0xff00 #define CNTR_CTRL_PRESCALE_MIN 2 #define CNTR_CTRL_PRESCALE_SHIFT 8 -#define CNTR_COUNT_LOW 0x14 -#define CNTR_COUNT_HIGH 0x18 +#define CNTR_COUNT_LOW(id) (CNTR_CTRL(id) + 0x4) +#define CNTR_COUNT_HIGH(id) (CNTR_CTRL(id) + 0x8) -static void set_counter_value(struct a37xx_wdt *priv) +static void set_counter_value(struct a37xx_wdt *priv, int id, u64 val) { - writel(priv->timeout & 0xffffffff, priv->reg + CNTR_COUNT_LOW); - writel(priv->timeout >> 32, priv->reg + CNTR_COUNT_HIGH); + writel(val & 0xffffffff, priv->reg + CNTR_COUNT_LOW(id)); + writel(val >> 32, priv->reg + CNTR_COUNT_HIGH(id)); } -static void a37xx_wdt_enable(struct a37xx_wdt *priv) +static void counter_enable(struct a37xx_wdt *priv, int id) { - u32 reg = readl(priv->reg + CNTR_CTRL); - - reg |= CNTR_CTRL_ENABLE; - writel(reg, priv->reg + CNTR_CTRL); + setbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE); } -static void a37xx_wdt_disable(struct a37xx_wdt *priv) +static void counter_disable(struct a37xx_wdt *priv, int id) { - u32 reg = readl(priv->reg + CNTR_CTRL); + clrbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE); +} - reg &= ~CNTR_CTRL_ENABLE; - writel(reg, priv->reg + CNTR_CTRL); +static int init_counter(struct a37xx_wdt *priv, int id, u32 mode, u32 trig_src) +{ + u32 reg; + + reg = readl(priv->reg + CNTR_CTRL(id)); + if (reg & CNTR_CTRL_ACTIVE) + return -EBUSY; + + reg &= ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK | + CNTR_CTRL_TRIG_SRC_MASK); + + /* set mode */ + reg |= mode; + + /* set prescaler to the min value */ + reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT; + + /* set trigger source */ + reg |= trig_src; + + writel(reg, priv->reg + CNTR_CTRL(id)); + + return 0; } static int a37xx_wdt_reset(struct udevice *dev) @@ -67,9 +88,9 @@ static int a37xx_wdt_reset(struct udevice *dev) if (!priv->timeout) return -EINVAL; - a37xx_wdt_disable(priv); - set_counter_value(priv); - a37xx_wdt_enable(priv); + /* counter 1 is retriggered by forcing end count on counter 0 */ + counter_disable(priv, 0); + counter_enable(priv, 0); return 0; } @@ -78,10 +99,14 @@ static int a37xx_wdt_expire_now(struct udevice *dev, ulong flags) { struct a37xx_wdt *priv = dev_get_priv(dev); - a37xx_wdt_disable(priv); - priv->timeout = 0; - set_counter_value(priv); - a37xx_wdt_enable(priv); + /* first we set timeout to 0 */ + counter_disable(priv, 1); + set_counter_value(priv, 1, 0); + counter_enable(priv, 1); + + /* and then we start counter 1 by forcing end count on counter 0 */ + counter_disable(priv, 0); + counter_enable(priv, 0); return 0; } @@ -89,26 +114,25 @@ static int a37xx_wdt_expire_now(struct udevice *dev, ulong flags) static int a37xx_wdt_start(struct udevice *dev, u64 ms, ulong flags) { struct a37xx_wdt *priv = dev_get_priv(dev); - u32 reg; + int err; - reg = readl(priv->reg + CNTR_CTRL); + err = init_counter(priv, 0, CNTR_CTRL_MODE_ONESHOT, 0); + if (err < 0) + return err; - if (reg & CNTR_CTRL_ACTIVE) - return -EBUSY; - - /* set mode */ - reg = (reg & ~CNTR_CTRL_MODE_MASK) | CNTR_CTRL_MODE_ONESHOT; - - /* set prescaler to the min value */ - reg &= ~CNTR_CTRL_PRESCALE_MASK; - reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT; + err = init_counter(priv, 1, CNTR_CTRL_MODE_HWSIG, + CNTR_CTRL_TRIG_SRC_PREV_CNTR); + if (err < 0) + return err; priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN; - writel(reg, priv->reg + CNTR_CTRL); + set_counter_value(priv, 0, 0); + set_counter_value(priv, 1, priv->timeout); + counter_enable(priv, 1); - set_counter_value(priv); - a37xx_wdt_enable(priv); + /* we have to force end count on counter 0 to start counter 1 */ + counter_enable(priv, 0); return 0; } @@ -117,7 +141,9 @@ static int a37xx_wdt_stop(struct udevice *dev) { struct a37xx_wdt *priv = dev_get_priv(dev); - a37xx_wdt_disable(priv); + counter_disable(priv, 1); + counter_disable(priv, 0); + writel(0, priv->sel_reg); return 0; } @@ -139,11 +165,10 @@ static int a37xx_wdt_probe(struct udevice *dev) priv->clk_rate = (ulong)get_ref_clk() * 1000000; - a37xx_wdt_disable(priv); - /* - * We use timer 1 as watchdog timer (because Marvell's Linux uses that - * timer as default), therefore we only set bit TIMER1_IS_WCHDOG_TIMER. + * We use counter 1 as watchdog timer, therefore we only set bit + * TIMER1_IS_WCHDOG_TIMER. Counter 0 is only used to force re-trigger on + * counter 1. */ writel(1 << 1, priv->sel_reg); From da1f799700ba4fbc9f24bc2dd4871260d14768b9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 17 Dec 2018 16:10:07 +0100 Subject: [PATCH 08/15] MAINTAINERS: Add entry for CZ.NIC's Turris project MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add myself as the maintainer of CZ.NIC's Turris Omnia and Turris Mox projects. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 399a839e07..38a1bc68f5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -120,6 +120,14 @@ F: doc/README.bcm7xxx F: drivers/mmc/bcmstb_sdhci.c F: drivers/spi/bcmstb_spi.c +ARM/CZ.NIC TURRIS MOX SUPPORT +M: Marek Behun +S: Maintained +F: arch/arm/dts/armada-3720-turris-mox.dts +F: board/CZ.NIC/ +F: configs/turris_*_defconfig +F: include/configs/turris_*.h + ARM FREESCALE IMX M: Stefano Babic M: Fabio Estevam From c87b87006b0d1f42dd0b2f3a2c0a3048959489cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 17 Dec 2018 16:10:08 +0100 Subject: [PATCH 09/15] arm: mvebu: turris_mox: Read info (and ethaddrs) from OTP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for reading One-Time Programmable memory via mailbox, which communicates with CZ.NIC's firmware on the Secure Processor (Cortex-M3) of Armada 3720. Display product serial number and additional info, and also set MAC addresses. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- board/CZ.NIC/turris_mox/Makefile | 2 +- board/CZ.NIC/turris_mox/mox_sp.c | 136 +++++++++++++++++++++++++++ board/CZ.NIC/turris_mox/mox_sp.h | 15 +++ board/CZ.NIC/turris_mox/turris_mox.c | 55 ++++++++++- 4 files changed, 205 insertions(+), 3 deletions(-) create mode 100644 board/CZ.NIC/turris_mox/mox_sp.c create mode 100644 board/CZ.NIC/turris_mox/mox_sp.h diff --git a/board/CZ.NIC/turris_mox/Makefile b/board/CZ.NIC/turris_mox/Makefile index 619704288b..33a52b63d7 100644 --- a/board/CZ.NIC/turris_mox/Makefile +++ b/board/CZ.NIC/turris_mox/Makefile @@ -2,4 +2,4 @@ # # Copyright (C) 2018 Marek Behun -obj-y := turris_mox.o +obj-y := turris_mox.o mox_sp.o diff --git a/board/CZ.NIC/turris_mox/mox_sp.c b/board/CZ.NIC/turris_mox/mox_sp.c new file mode 100644 index 0000000000..0b29ffcc67 --- /dev/null +++ b/board/CZ.NIC/turris_mox/mox_sp.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Marek Behun + */ + +#include +#include + +#define RWTM_CMD_PARAM(i) (size_t)(0xd00b0000 + (i) * 4) +#define RWTM_CMD 0xd00b0040 +#define RWTM_CMD_RETSTATUS 0xd00b0080 +#define RWTM_CMD_STATUS(i) (size_t)(0xd00b0084 + (i) * 4) + +#define RWTM_HOST_INT_RESET 0xd00b00c8 +#define RWTM_HOST_INT_MASK 0xd00b00cc +#define SP_CMD_COMPLETE BIT(0) + +#define MBOX_STS_SUCCESS (0x0 << 30) +#define MBOX_STS_FAIL (0x1 << 30) +#define MBOX_STS_BADCMD (0x2 << 30) +#define MBOX_STS_LATER (0x3 << 30) +#define MBOX_STS_ERROR(s) ((s) & (3 << 30)) +#define MBOX_STS_VALUE(s) (((s) >> 10) & 0xfffff) +#define MBOX_STS_CMD(s) ((s) & 0x3ff) + +enum mbox_cmd { + MBOX_CMD_GET_RANDOM = 1, + MBOX_CMD_BOARD_INFO, + MBOX_CMD_ECDSA_PUB_KEY, + MBOX_CMD_HASH, + MBOX_CMD_SIGN, + MBOX_CMD_VERIFY, + + MBOX_CMD_OTP_READ, + MBOX_CMD_OTP_WRITE +}; + +static int mbox_do_cmd(enum mbox_cmd cmd, u32 *out, int nout) +{ + const int tries = 50; + int i; + u32 status; + + clrbits_le32(RWTM_HOST_INT_MASK, SP_CMD_COMPLETE); + + writel(cmd, RWTM_CMD); + + for (i = 0; i < tries; ++i) { + mdelay(10); + if (readl(RWTM_HOST_INT_RESET) & SP_CMD_COMPLETE) + break; + } + + if (i == tries) { + /* if timed out, don't read status */ + setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE); + return -ETIMEDOUT; + } + + for (i = 0; i < nout; ++i) + out[i] = readl(RWTM_CMD_STATUS(i)); + status = readl(RWTM_CMD_RETSTATUS); + + setbits_le32(RWTM_HOST_INT_RESET, SP_CMD_COMPLETE); + + if (MBOX_STS_CMD(status) != cmd) + return -EIO; + else if (MBOX_STS_ERROR(status) == MBOX_STS_FAIL) + return -(int)MBOX_STS_VALUE(status); + else if (MBOX_STS_ERROR(status) != MBOX_STS_SUCCESS) + return -EIO; + else + return MBOX_STS_VALUE(status); +} + +const char *mox_sp_get_ecdsa_public_key(void) +{ + static char public_key[135]; + u32 out[16]; + int res; + + if (public_key[0]) + return public_key; + + res = mbox_do_cmd(MBOX_CMD_ECDSA_PUB_KEY, out, 16); + if (res < 0) + return NULL; + + sprintf(public_key, + "%06x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x", + (u32)res, out[0], out[1], out[2], out[3], out[4], out[5], + out[6], out[7], out[8], out[9], out[10], out[11], out[12], + out[13], out[14], out[15]); + + return public_key; +} + +static inline void res_to_mac(u8 *mac, u32 t1, u32 t2) +{ + mac[0] = t1 >> 8; + mac[1] = t1; + mac[2] = t2 >> 24; + mac[3] = t2 >> 16; + mac[4] = t2 >> 8; + mac[5] = t2; +} + +int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv, int *ram) +{ + u32 out[8]; + int res; + + res = mbox_do_cmd(MBOX_CMD_BOARD_INFO, out, 8); + if (res < 0) + return res; + + if (sn) { + *sn = out[1]; + *sn <<= 32; + *sn |= out[0]; + } + + if (bv) + *bv = out[2]; + + if (ram) + *ram = out[3]; + + if (mac1) + res_to_mac(mac1, out[4], out[5]); + + if (mac2) + res_to_mac(mac2, out[6], out[7]); + + return 0; +} diff --git a/board/CZ.NIC/turris_mox/mox_sp.h b/board/CZ.NIC/turris_mox/mox_sp.h new file mode 100644 index 0000000000..49a4ed80ea --- /dev/null +++ b/board/CZ.NIC/turris_mox/mox_sp.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Marek Behun + */ + +#ifndef _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_ +#define _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_ + +#include + +const char *mox_sp_get_ecdsa_public_key(void); +int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv, + int *ram); + +#endif /* _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_ */ diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 4426ee3446..d16d6fd124 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -14,11 +14,14 @@ #include #include #include +#include #ifdef CONFIG_WDT_ARMADA_37XX #include #endif +#include "mox_sp.h" + #define MAX_MOX_MODULES 10 #define MOX_MODULE_SFP 0x1 @@ -366,6 +369,49 @@ static int get_reset_gpio(struct gpio_desc *reset_gpio) return 0; } +int misc_init_r(void) +{ + int ret; + u8 mac1[6], mac2[6]; + + ret = mbox_sp_get_board_info(NULL, mac1, mac2, NULL, NULL); + if (ret < 0) { + printf("Cannot read data from OTP!\n"); + return 0; + } + + if (is_valid_ethaddr(mac1) && !env_get("ethaddr")) + eth_env_set_enetaddr("ethaddr", mac1); + + if (is_valid_ethaddr(mac2) && !env_get("eth1addr")) + eth_env_set_enetaddr("eth1addr", mac2); + + return 0; +} + +static void mox_print_info(void) +{ + int ret, board_version, ram_size; + u64 serial_number; + const char *pub_key; + + ret = mbox_sp_get_board_info(&serial_number, NULL, NULL, &board_version, + &ram_size); + if (ret < 0) + return; + + printf("Turris Mox:\n"); + printf(" Board version: %i\n", board_version); + printf(" RAM size: %i MiB\n", ram_size); + printf(" Serial Number: %016llX\n", serial_number); + + pub_key = mox_sp_get_ecdsa_public_key(); + if (pub_key) + printf(" ECDSA Public Key: %s\n", pub_key); + else + printf("Cannot read ECDSA Public Key\n"); +} + int last_stage_init(void) { int ret, i; @@ -374,14 +420,19 @@ int last_stage_init(void) struct mii_dev *bus; struct gpio_desc reset_gpio = {}; + mox_print_info(); + ret = mox_get_topology(&topology, &module_count, &is_sd); if (ret) { printf("Cannot read module topology!\n"); return 0; } - printf("Found Turris Mox %s version\n", is_sd ? "SD" : "eMMC"); - printf("Module Topology:\n"); + printf(" SD/eMMC version: %s\n", is_sd ? "SD" : "eMMC"); + + if (module_count) + printf("Module Topology:\n"); + for (i = 0; i < module_count; ++i) { switch (topology[i]) { case MOX_MODULE_SFP: From 3b281aca41dbad65fc0ccc2bed5c2caf684210fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 17 Dec 2018 16:10:09 +0100 Subject: [PATCH 10/15] arm: mvebu: turris_mox: Support 1 GB version of Turris Mox MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use get_ram_size to determine if the RAM size on Turris Mox is 512 MiB or 1 GiB. Signed-off-by: Marek Behún Signed-off-by: Stefan Roese --- arch/arm/mach-mvebu/arm64-common.c | 4 ++-- board/CZ.NIC/turris_mox/turris_mox.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index 47bbf69944..aaf7b7c447 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -84,7 +84,7 @@ static void a8k_dram_init_banksize(void) } } -int dram_init_banksize(void) +__weak int dram_init_banksize(void) { if (CONFIG_IS_ENABLED(ARMADA_8K)) a8k_dram_init_banksize(); @@ -94,7 +94,7 @@ int dram_init_banksize(void) return 0; } -int dram_init(void) +__weak int dram_init(void) { if (CONFIG_IS_ENABLED(ARMADA_8K)) { gd->ram_size = a8k_dram_scan_ap_sz(); diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index d16d6fd124..65d50a92dd 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -41,6 +41,22 @@ DECLARE_GLOBAL_DATA_PTR; +int dram_init(void) +{ + gd->ram_base = 0; + gd->ram_size = (phys_size_t)get_ram_size(0, 0x40000000); + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = (phys_addr_t)0; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + #if defined(CONFIG_OF_BOARD_FIXUP) int board_fix_fdt(void *blob) { From 7a6f60d6fe6ec524afed8c8396847c4a0fdec9cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 17 Dec 2018 16:10:10 +0100 Subject: [PATCH 11/15] arm: mvebu: configs: turris_mox: Add 64 MiB of boot memory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is needed for some scenarios, such as booting large FIT image. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- include/configs/turris_mox.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index 0aebe2100b..82cdccecc1 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -8,6 +8,8 @@ #ifndef _CONFIG_TURRIS_MOX_H #define _CONFIG_TURRIS_MOX_H +#define CONFIG_SYS_BOOTM_LEN (64 << 20) + #define CONFIG_LAST_STAGE_INIT /* From cf63dad014bae080445bccbf9cecbe05f2cbed45 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 21 Dec 2018 17:30:46 +0100 Subject: [PATCH 12/15] arm64: dts: marvell: armada-ap806: reserve PSCI area The memory area [0x4000000-0x4200000[ is occupied by the PSCI firmware. Any attempt to access it from U-Boot leads to an immediate crash. So let's make the same memory reservation as the vendor device tree. Signed-off-by: Heinrich Schuchardt Signed-off-by: Stefan Roese --- arch/arm/dts/armada-ap806.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi index ebdee514c0..713c2dba74 100644 --- a/arch/arm/dts/armada-ap806.dtsi +++ b/arch/arm/dts/armada-ap806.dtsi @@ -64,6 +64,17 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + psci-area@4000000 { + reg = <0x0 0x4000000 0x0 0x200000>; + no-map; + }; + }; + ap806 { #address-cells = <2>; #size-cells = <2>; From 357766365d561b1dd36a073a757cca6e495f8bfd Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 26 Dec 2018 10:37:55 +0100 Subject: [PATCH 13/15] arm64: mvebu: defconfig: enable CONFIG_CMD_NVME An NVME drive may be installed on the MACCHIATObin board using the PCIe slot or on the Clearfog Pro using mini a PCI-e slot. With the configuration change it becomes usable. Signed-off-by: Heinrich Schuchardt Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- configs/clearfog_gt_8k_defconfig | 2 ++ configs/mvebu_db_armada8k_defconfig | 2 ++ configs/mvebu_mcbin-88f8040_defconfig | 2 ++ 3 files changed, 6 insertions(+) diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig index 42cdbfab61..bd96f87fe9 100644 --- a/configs/clearfog_gt_8k_defconfig +++ b/configs/clearfog_gt_8k_defconfig @@ -41,6 +41,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_CMD_NVME=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_XENON=y CONFIG_SPI_FLASH=y @@ -50,6 +51,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCIE_DW_MVEBU=y diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index 424d9765dc..c533d09a41 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -20,6 +20,7 @@ CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_NVME=y CONFIG_CMD_PCI=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -47,6 +48,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVPP2=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCIE_DW_MVEBU=y diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig index d671f201f6..4bed532ef9 100644 --- a/configs/mvebu_mcbin-88f8040_defconfig +++ b/configs/mvebu_mcbin-88f8040_defconfig @@ -20,6 +20,7 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_NVME=y CONFIG_CMD_PCI=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -51,6 +52,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_MVPP2=y +CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PCIE_DW_MVEBU=y From 0e62072968a2089529262dc6e37417b7a3c5ff03 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Wed, 2 Jan 2019 18:26:42 +0200 Subject: [PATCH 14/15] board: mvebu: drop unused ETH_PHY macro definitions These macros are not used anywhere in the boards code. Cc: Chris Packham Cc: Dirk Eibach Cc: Mario Six Cc: Dennis Gilmore Signed-off-by: Baruch Siach Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- board/Marvell/db-88f6820-amc/db-88f6820-amc.c | 4 ---- board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 4 ---- board/gdsys/a38x/controlcenterdc.c | 4 ---- board/kobol/helios4/helios4.c | 4 ---- board/solidrun/clearfog/clearfog.c | 4 ---- 5 files changed, 20 deletions(-) diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c index bc18fe6ddf..922576e9d5 100644 --- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c +++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c @@ -16,10 +16,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define ETH_PHY_CTRL_REG 0 -#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 -#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) - /* * Those values and defines are taken from the Marvell U-Boot version * "u-boot-2013.01-2016_T1.0.eng_drop_v10" diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index 9368bce26c..1a0746b9d3 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -16,10 +16,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define ETH_PHY_CTRL_REG 0 -#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 -#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) - /* * Those values and defines are taken from the Marvell U-Boot version * "u-boot-2013.01-2014_T3.0" diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c index 86051aedf8..9e448fcd10 100644 --- a/board/gdsys/a38x/controlcenterdc.c +++ b/board/gdsys/a38x/controlcenterdc.c @@ -22,10 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define ETH_PHY_CTRL_REG 0 -#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 -#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) - #define DB_GP_88F68XX_GPP_OUT_ENA_LOW 0x7fffffff #define DB_GP_88F68XX_GPP_OUT_ENA_MID 0xffffefff diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c index 8c0864bcdd..3c3592ecf5 100644 --- a/board/kobol/helios4/helios4.c +++ b/board/kobol/helios4/helios4.c @@ -17,10 +17,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define ETH_PHY_CTRL_REG 0 -#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 -#define ETH_PHY_CTRL_POWER_DOWN_MASK BIT(ETH_PHY_CTRL_POWER_DOWN_BIT) - /* * Those values and defines are taken from the Marvell U-Boot version * "u-boot-2013.01-15t1-helios4" as well as the upstream config for clearfog diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 1742aa8921..03724fee10 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -16,10 +16,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define ETH_PHY_CTRL_REG 0 -#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 -#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) - /* * Those values and defines are taken from the Marvell U-Boot version * "u-boot-2013.01-15t1-clearfog" From 0e31666dfa043ab71fb1fbbba4feacfe8af3e06b Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 10 Jan 2019 21:01:00 +1300 Subject: [PATCH 15/15] ARM: mvebu: add support for Allied Telesis x530 This is a range of stackable network switches. The SoC is Armada-385 and there are a number of variants with differing network port configurations. The DP variants are intended for a harsher operating environment so they use a different i2c mux and fit industrial-temp parts. Signed-off-by: Chris Packham Signed-off-by: Stefan Roese --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/armada-385-atl-x530-u-boot.dtsi | 13 + arch/arm/dts/armada-385-atl-x530.dts | 50 ++++ arch/arm/dts/armada-385-atl-x530.dtsi | 266 +++++++++++++++++++ arch/arm/dts/armada-385-atl-x530DP.dts | 51 ++++ arch/arm/dts/armada-385-atl-x530DP.dtsi | 149 +++++++++++ arch/arm/mach-mvebu/Kconfig | 7 + board/alliedtelesis/common/gpio_hog.c | 36 +++ board/alliedtelesis/common/gpio_hog.h | 13 + board/alliedtelesis/x530/MAINTAINERS | 12 + board/alliedtelesis/x530/Makefile | 9 + board/alliedtelesis/x530/kwbimage.cfg | 12 + board/alliedtelesis/x530/x530.c | 161 +++++++++++ configs/x530_defconfig | 71 +++++ include/configs/x530.h | 134 ++++++++++ 15 files changed, 987 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/armada-385-atl-x530-u-boot.dtsi create mode 100644 arch/arm/dts/armada-385-atl-x530.dts create mode 100644 arch/arm/dts/armada-385-atl-x530.dtsi create mode 100644 arch/arm/dts/armada-385-atl-x530DP.dts create mode 100644 arch/arm/dts/armada-385-atl-x530DP.dtsi create mode 100644 board/alliedtelesis/common/gpio_hog.c create mode 100644 board/alliedtelesis/common/gpio_hog.h create mode 100644 board/alliedtelesis/x530/MAINTAINERS create mode 100644 board/alliedtelesis/x530/Makefile create mode 100644 board/alliedtelesis/x530/kwbimage.cfg create mode 100644 board/alliedtelesis/x530/x530.c create mode 100644 configs/x530_defconfig create mode 100644 include/configs/x530.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b2ca87deef..ce5e845a2c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -109,7 +109,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-xp-maxbcm.dtb \ armada-xp-synology-ds414.dtb \ armada-xp-theadorable.dtb \ - armada-38x-controlcenterdc.dtb + armada-38x-controlcenterdc.dtb \ + armada-385-atl-x530.dtb \ + armada-385-atl-x530DP.dtb dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ uniphier-ld11-global.dtb \ diff --git a/arch/arm/dts/armada-385-atl-x530-u-boot.dtsi b/arch/arm/dts/armada-385-atl-x530-u-boot.dtsi new file mode 100644 index 0000000000..7074a73537 --- /dev/null +++ b/arch/arm/dts/armada-385-atl-x530-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 + +&spi1 { + u-boot,dm-pre-reloc; + + spi-flash@0 { + u-boot,dm-pre-reloc; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/armada-385-atl-x530.dts b/arch/arm/dts/armada-385-atl-x530.dts new file mode 100644 index 0000000000..0ebaa8bb34 --- /dev/null +++ b/arch/arm/dts/armada-385-atl-x530.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "armada-385-atl-x530.dtsi" +#include "armada-385-atl-x530-u-boot.dtsi" + +/ { + model = "Allied Telesis x530"; + compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380"; + + nand-protect { + compatible = "atl,nand-protect"; + protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + usb-enable { + compatible = "atl,usb-enable"; + enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>; + }; + + boot-board { + compatible = "atl,boot-board"; + present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>; + override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + + phy-reset { + compatible = "atl,phy-reset"; + reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>, + <&gpio1 21 GPIO_ACTIVE_HIGH>; + }; + + led-enable { + compatible = "atl,led-enable"; + enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; + }; + + led_7seg { + compatible = "atl,of-led-7seg"; + segment-gpios = < + &led_7seg_gpio 0 0 + &led_7seg_gpio 1 0 + &led_7seg_gpio 2 0 + &led_7seg_gpio 3 0 + &led_7seg_gpio 4 0 + &led_7seg_gpio 5 0 + &led_7seg_gpio 6 0 + &led_7seg_gpio 7 0>; + }; +}; diff --git a/arch/arm/dts/armada-385-atl-x530.dtsi b/arch/arm/dts/armada-385-atl-x530.dtsi new file mode 100644 index 0000000000..09a04bdcca --- /dev/null +++ b/arch/arm/dts/armada-385-atl-x530.dtsi @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include "armada-385.dtsi" + +/ { + model = "Allied Telesis x530"; + compatible = "alliedtelesis,x530", "marvell,armada385", "marvell,armada380"; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + aliases { + spi1 = &spi1; + i2c0 = &i2c0; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x40000000>; /* 1 GB */ + }; + + soc { + ranges = ; + + pcie-mem-aperture = <0xa0000000 0x40000000>; + }; + + eco-button-interrupt { + compatible = "atl,eco-button-interrupt"; + eco-button-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>; + }; + + board-reset { + compatible = "atl,phy_reset"; + /* Physical board layout of reset pin is active-low but for the + * current driver we have to set it to active-high here. + */ + phy-reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>, + <&gpio1 21 GPIO_ACTIVE_HIGH>; + }; + + phy-int { + compatible = "linux,uio-pdrv-genirq"; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_EDGE_BOTH>; + }; + + led-enable { + compatible = "atl,led-enable"; + led-enable-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; + + led_7seg { + compatible = "atl,of-led-7seg"; + segment-gpios = < + &led_7seg_gpio 0 0 + &led_7seg_gpio 1 0 + &led_7seg_gpio 2 0 + &led_7seg_gpio 3 0 + &led_7seg_gpio 4 0 + &led_7seg_gpio 5 0 + &led_7seg_gpio 6 0 + &led_7seg_gpio 7 0>; + }; + + poe { + compatible = "atl,periph-poe"; + poe-reset-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio0>; + interrupts = <20 IRQ_TYPE_EDGE_BOTH>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&devbus_cs1 { + compatible = "marvell,mvebu-devbus"; + status = "okay"; + + devbus,bus-width = <8>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + nvs@0 { + status = "okay"; + + compatible = "mtd-ram"; + reg = <0 0x00080000>; + bank-width = <1>; + label = "nvs"; + }; +}; + +&gpio0 { + poe-disable { + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "poe-disable"; + }; +}; + +&gpio1 { + poe-mezz-reset { + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "poe-mezz-reset"; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + mux@71 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9544"; + reg = <0x71>; + i2c-mux-idle-disconnect; + + i2c@0 { /* POE devices MUX */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + rng@3b { + compatible = "maxim,ds2476"; + reg = <0x3b>; + }; + + hwmon@2e { + compatible = "adi,adt7476"; + reg = <0x2e>; + }; + + hwmon@2d { + compatible = "adi,adt7476"; + reg = <0x2d>; + }; + + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + rtc@68 { + compatible = "dallas,ds1340"; + reg = <0x68>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + led_7seg_gpio: gpio@20 { + compatible = "nxp,pca9554"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; + + sfpgpio: gpio@27 { /* I2C to GPIO */ + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x27>; + interrupt-parent = <&gpio0>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + }; + + sfpmux: mux@77 { /* SFP I2C MUX */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9544"; + reg = <0x77>; + i2c-mux-idle-disconnect; + }; + }; + }; +}; + +&spi1 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x00100000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x00100000 0x00040000>; + label = "u-boot-env"; + }; + partition@unused { + reg = <0x00140000 0x00e80000>; + label = "unused"; + }; + partition@idprom { + reg = <0x00fc0000 0x00040000>; + label = "idprom"; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&refclk { + clock-frequency = <25000000>; +}; + +&nand_controller { /* 256 MB */ + status = "okay"; + num-cs = <1>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; +}; diff --git a/arch/arm/dts/armada-385-atl-x530DP.dts b/arch/arm/dts/armada-385-atl-x530DP.dts new file mode 100644 index 0000000000..2d38bf50b9 --- /dev/null +++ b/arch/arm/dts/armada-385-atl-x530DP.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "armada-385-atl-x530.dtsi" +#include "armada-385-atl-x530-u-boot.dtsi" +#include "armada-385-atl-x530DP.dtsi" + +/ { + model = "Allied Telesis x530DP"; + compatible = "alliedtelesis,x530DP", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380"; + + nand-protect { + compatible = "atl,nand-protect"; + protect-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + usb-enable { + compatible = "atl,usb-enable"; + enable-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>; + }; + + boot-board { + compatible = "atl,boot-board"; + present-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>; + override-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + + phy-reset { + compatible = "atl,phy-reset"; + reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>, + <&gpio1 21 GPIO_ACTIVE_HIGH>; + }; + + led-enable { + compatible = "atl,led-enable"; + enable-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; + }; + + led_7seg { + compatible = "atl,of-led-7seg"; + segment-gpios = < + &led_7seg_gpio 0 0 + &led_7seg_gpio 1 0 + &led_7seg_gpio 2 0 + &led_7seg_gpio 3 0 + &led_7seg_gpio 4 0 + &led_7seg_gpio 5 0 + &led_7seg_gpio 6 0 + &led_7seg_gpio 7 0>; + }; +}; diff --git a/arch/arm/dts/armada-385-atl-x530DP.dtsi b/arch/arm/dts/armada-385-atl-x530DP.dtsi new file mode 100644 index 0000000000..977eb4ee54 --- /dev/null +++ b/arch/arm/dts/armada-385-atl-x530DP.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 + +&i2c0 { + mux@71 { + compatible = "nxp,pca9548"; + + i2c@1 { + hwmon@2c { + compatible = "ti,lm87"; + reg = <0x2c>; + }; + + hwmon@2d { + compatible = "ti,lm87"; + reg = <0x2d>; + }; + + hwmon@2e { + pwm-polarity = <1>; + }; + }; + + psu_a_adapter: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + psu_b_adapter: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + misc_gpio: gpio@26 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x26>; + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + interrupt-controller; + #interrupt-cells = <2>; + + psu_bank2 { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "psu-bank2"; + }; + }; + }; + }; +}; + +/ { + psu_slot_a { + compatible = "atl,dts-overlay-gpio-psu-slot"; + slot-name = "PSU Bay A"; + board-index = <1>; + present-gpio = <&misc_gpio 1 GPIO_ACTIVE_LOW>; + output-ok-gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&misc_gpio>; + interrupts = <1 IRQ_TYPE_EDGE_BOTH>; + overlay = <&psu_a_overlay>; + }; + + psu_slot_b { + compatible = "atl,dts-overlay-gpio-psu-slot"; + slot-name = "PSU Bay B"; + board-index = <2>; + present-gpio = <&misc_gpio 2 GPIO_ACTIVE_LOW>; + output-ok-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&misc_gpio>; + interrupts = <2 IRQ_TYPE_EDGE_BOTH>; + overlay = <&psu_b_overlay>; + }; + + fan_slot_a { + compatible = "atl,fan05-slot"; + slot-name = "Fan Bay A"; + board-index = <3>; + present-gpio = <&misc_gpio 3 GPIO_ACTIVE_LOW>; + fault-gpio = <&misc_gpio 11 GPIO_ACTIVE_LOW>; + interrupt-parent = <&misc_gpio>; + interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + overlay = <&fan_a_overlay>; + }; +}; + +/ { + psu_a_overlay: psu_a { + fragment@0 { + target = <&psu_a_adapter>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + psu@51 { + compatible = "atl,atl-pwr-gen2"; + reg = <0x51>; + board-index = <1>; + }; + }; + }; + }; +}; + +/ { + psu_b_overlay: psu_b { + fragment@0 { + target = <&psu_b_adapter>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + psu@51 { + compatible = "atl,atl-pwr-gen2"; + reg = <0x51>; + board-index = <2>; + }; + }; + }; + }; +}; + +/ { + fan_a_overlay:fan_a { + fragment@1 { + target-path = "/"; + __overlay__ { + fan@1 { + compatible = "atl,fan05"; + board-index = <3>; + module-id-gpios = + <&misc_gpio 4 GPIO_ACTIVE_HIGH>, + <&misc_gpio 5 GPIO_ACTIVE_HIGH>, + <&misc_gpio 6 GPIO_ACTIVE_HIGH>; + }; + }; + }; + }; +}; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index d1f71338ac..7dda04e0e3 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -132,6 +132,10 @@ config TARGET_CONTROLCENTERDC bool "Support CONTROLCENTERDC" select 88F6820 +config TARGET_X530 + bool "Support Allied Telesis x530" + select 88F6820 + endchoice config SYS_BOARD @@ -149,6 +153,7 @@ config SYS_BOARD default "maxbcm" if TARGET_MAXBCM default "theadorable" if TARGET_THEADORABLE default "a38x" if TARGET_CONTROLCENTERDC + default "x530" if TARGET_X530 config SYS_CONFIG_NAME default "clearfog" if TARGET_CLEARFOG @@ -165,6 +170,7 @@ config SYS_CONFIG_NAME default "turris_omnia" if TARGET_TURRIS_OMNIA default "turris_mox" if TARGET_TURRIS_MOX default "controlcenterdc" if TARGET_CONTROLCENTERDC + default "x530" if TARGET_X530 config SYS_VENDOR default "Marvell" if TARGET_DB_MV784MP_GP @@ -179,6 +185,7 @@ config SYS_VENDOR default "CZ.NIC" if TARGET_TURRIS_OMNIA default "CZ.NIC" if TARGET_TURRIS_MOX default "gdsys" if TARGET_CONTROLCENTERDC + default "alliedtelesis" if TARGET_X530 config SYS_SOC default "mvebu" diff --git a/board/alliedtelesis/common/gpio_hog.c b/board/alliedtelesis/common/gpio_hog.c new file mode 100644 index 0000000000..1f87b3ac1b --- /dev/null +++ b/board/alliedtelesis/common/gpio_hog.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Allied Telesis Labs + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int gpio_hog_list(struct gpio_desc *gpiod, int max_count, + const char *node_name, const char *gpio_name, int value) +{ + int node; + int count; + int i; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, node_name); + if (node < 0) + return -ENODEV; + + if (!dm_gpio_is_valid(gpiod)) { + count = + gpio_request_list_by_name_nodev(offset_to_ofnode(node), + gpio_name, gpiod, max_count, + GPIOD_IS_OUT); + if (count < 0) + return count; + + for (i = 0; i < count; i++) + dm_gpio_set_value(&gpiod[i], value); + } + + return 0; +} diff --git a/board/alliedtelesis/common/gpio_hog.h b/board/alliedtelesis/common/gpio_hog.h new file mode 100644 index 0000000000..edb7443131 --- /dev/null +++ b/board/alliedtelesis/common/gpio_hog.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Allied Telesis Labs + */ + +int gpio_hog_list(struct gpio_desc *gpiod, int max_count, const char *node_name, + const char *gpio_name, int value); + +static inline int gpio_hog(struct gpio_desc *gpiod, const char *node_name, + const char *gpio_name, int value) +{ + return gpio_hog_list(gpiod, 1, node_name, gpio_name, value); +} diff --git a/board/alliedtelesis/x530/MAINTAINERS b/board/alliedtelesis/x530/MAINTAINERS new file mode 100644 index 0000000000..8d2d7271b9 --- /dev/null +++ b/board/alliedtelesis/x530/MAINTAINERS @@ -0,0 +1,12 @@ +x530 BOARD +M: Chris Packham +S: Maintained +F: board/alliedtelesis/x530/ +F: board/alliedtelesis/common/gpio_hog.c +F: board/alliedtelesis/common/gpio_hog.h +F: arch/arm/dts/armada-385-atl-x530.dts +F: arch/arm/dts/armada-385-atl-x530.dtsi +F: arch/arm/dts/armada-385-atl-x530DP.dts +F: arch/arm/dts/armada-385-atl-x530DP.dtsi +F: include/configs/x530.h +F: configs/x530_defconfig diff --git a/board/alliedtelesis/x530/Makefile b/board/alliedtelesis/x530/Makefile new file mode 100644 index 0000000000..97de1d463f --- /dev/null +++ b/board/alliedtelesis/x530/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017 Allied Telesis Labs +# + +obj-y := $(BOARD).o +ifndef CONFIG_SPL_BUILD +obj-y += ../common/gpio_hog.o +endif diff --git a/board/alliedtelesis/x530/kwbimage.cfg b/board/alliedtelesis/x530/kwbimage.cfg new file mode 100644 index 0000000000..f58d388825 --- /dev/null +++ b/board/alliedtelesis/x530/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2017 Allied Telesis Labs +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c new file mode 100644 index 0000000000..b34ae51345 --- /dev/null +++ b/board/alliedtelesis/x530/x530.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Allied Telesis Labs + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/gpio_hog.h" + +#include "../drivers/ddr/marvell/a38x/ddr3_init.h" +#include <../serdes/a38x/high_speed_env_spec.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400)) + +#define CONFIG_NVS_LOCATION 0xf4800000 +#define CONFIG_NVS_SIZE (512 << 10) + +static struct serdes_map board_serdes_map[] = { + {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, + {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, + {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0} +}; + +int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) +{ + *serdes_map_array = board_serdes_map; + *count = ARRAY_SIZE(board_serdes_map); + return 0; +} + +/* + * Define the DDR layout / topology here in the board file. This will + * be used by the DDR3 init code in the SPL U-Boot version to configure + * the DDR3 controller. + */ +static struct mv_ddr_topology_map board_topology_map = { + DEBUG_LEVEL_ERROR, + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ + { { { {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0} }, + SPEED_BIN_DDR_1866M, /* speed_bin */ + MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */ + MV_DDR_DIE_CAP_4GBIT, /* die capacity */ + MV_DDR_FREQ_933, /* frequency */ + 0, 0, /* cas_l cas_wl */ + MV_DDR_TEMP_LOW, /* temperature */ + MV_DDR_TIM_2T} }, /* timing */ + BUS_MASK_32BIT_ECC, /* subphys mask */ + MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + { {0} }, /* raw spd data */ + {0} /* timing parameters */ +}; + +struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) +{ + /* Return the board topology as defined in the board code */ + return &board_topology_map; +} + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x00001111, MVEBU_MPP_BASE + 0x00); + writel(0x00000000, MVEBU_MPP_BASE + 0x04); + writel(0x55000000, MVEBU_MPP_BASE + 0x08); + writel(0x55550550, MVEBU_MPP_BASE + 0x0c); + writel(0x55555555, MVEBU_MPP_BASE + 0x10); + writel(0x00100565, MVEBU_MPP_BASE + 0x14); + writel(0x40000000, MVEBU_MPP_BASE + 0x18); + writel(0x00004444, MVEBU_MPP_BASE + 0x1c); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + /* window for NVS */ + mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1); + + /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */ + writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8); + + return 0; +} + +static int led_7seg_init(unsigned int segments) +{ + int node; + int ret; + int i; + struct gpio_desc desc[8]; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, + "atl,of-led-7seg"); + if (node < 0) + return -ENODEV; + + ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node), + "segment-gpios", desc, + ARRAY_SIZE(desc), GPIOD_IS_OUT); + if (ret < 0) + return ret; + + for (i = 0; i < ARRAY_SIZE(desc); i++) { + ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i))); + if (ret) + return ret; + } + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {}, + led_en = {}; + + gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1); + gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1); + gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0); + gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1); + +#ifdef MTDPARTS_MTDOOPS + env_set("mtdoops", MTDPARTS_MTDOOPS); +#endif + + led_7seg_init(0xff); + + return 0; +} +#endif + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + puts("Board: " CONFIG_SYS_BOARD "\n"); + + return 0; +} +#endif diff --git a/configs/x530_defconfig b/configs/x530_defconfig new file mode 100644 index 0000000000..22482f8d39 --- /dev/null +++ b/configs/x530_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_TEXT_BASE=0x00800000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_X530=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SILENT_CONSOLE=y +CONFIG_SILENT_U_BOOT_ONLY=y +CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y +CONFIG_MISC_INIT_R=y +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_DEFAULT_DEVICE_TREE="armada-385-atl-x530" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_BLK=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +# CONFIG_MMC is not set +CONFIG_NAND=y +CONFIG_NAND_PXA3XX=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_MTD_UBI=y +CONFIG_PCI=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y diff --git a/include/configs/x530.h b/include/configs/x530.h new file mode 100644 index 0000000000..a1ef301d35 --- /dev/null +++ b/include/configs/x530.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Allied Telesis Labs + */ + +#ifndef _CONFIG_X530_H +#define _CONFIG_X530_H + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#if !defined(CONFIG_DM_SERIAL) +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE +#endif + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ + +/* + * Commands configuration + */ +#define CONFIG_CMD_PCI + +/* NAND */ +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define BBT_CUSTOM_SCAN +#define BBT_CUSTOM_SCAN_PAGE 0 +#define BBT_CUSTOM_SCAN_POSITION 2048 + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_SPEED 50000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 + +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)" +#define MTDPARTS_MTDOOPS "errlog" + +/* Partition support */ + +/* Additional FS support/configuration */ + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ +#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI_MVEBU +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* NAND */ +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_LZO +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS + +#define CONFIG_SYS_MALLOC_LEN (4 << 20) + +#include + +/* + * Other required minimal configurations + */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ + +#define CONFIG_SYS_ALT_MEMTEST + +/* Keep device tree and initrd in low memory so the kernel can access them */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +#define CONFIG_SYS_LOAD_ADDR 0x1000000 +#define CONFIG_UBI_PART user +#define CONFIG_UBIFS_VOLUME user + +/* SPL */ + +/* Defines for SPL */ +#define CONFIG_SPL_SIZE (140 << 10) +#define CONFIG_SPL_TEXT_BASE 0x40000030 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) + +/* SPL related SPI defines */ +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 +#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS + +#endif /* _CONFIG_X530_H */