nand: fsl_upm: convert to updated MTD NAND infrastructure
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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300253306a
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e1c3dbada3
2 changed files with 30 additions and 39 deletions
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@ -20,8 +20,6 @@
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#include <linux/mtd/fsl_upm.h>
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#include <nand.h>
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static int fsl_upm_in_pattern;
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static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
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{
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clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
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@ -51,49 +49,38 @@ static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd)
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}
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}
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static void nand_hwcontrol (struct mtd_info *mtd, int cmd)
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static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *chip = mtd->priv;
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struct fsl_upm_nand *fun = chip->priv;
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switch (cmd) {
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case NAND_CTL_SETCLE:
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fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
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fsl_upm_in_pattern++;
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break;
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case NAND_CTL_SETALE:
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fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
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fsl_upm_in_pattern++;
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break;
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case NAND_CTL_CLRCLE:
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case NAND_CTL_CLRALE:
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if (!(ctrl & fun->last_ctrl)) {
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fsl_upm_end_pattern(&fun->upm);
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fsl_upm_in_pattern--;
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break;
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if (cmd == NAND_CMD_NONE)
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return;
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fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
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}
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}
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static void nand_write_byte(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *chip = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_ALE)
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fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
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else if (ctrl & NAND_CLE)
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fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
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}
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if (fsl_upm_in_pattern) {
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struct fsl_upm_nand *fun = chip->priv;
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fsl_upm_run_pattern(&fun->upm, fun->width, cmd);
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fsl_upm_run_pattern(&fun->upm, fun->width, byte);
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/*
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* Some boards/chips needs this. At least on MPC8360E-RDK we
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* need it. Probably weird chip, because I don't see any need
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* for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
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* 0-2 unexpected busy states per block read.
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*/
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if (fun->wait_pattern) {
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while (!fun->dev_ready())
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debug("unexpected busy state\n");
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}
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} else {
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out_8(chip->IO_ADDR_W, byte);
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/*
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* Some boards/chips needs this. At least on MPC8360E-RDK we
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* need it. Probably weird chip, because I don't see any need
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* for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
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* 0-2 unexpected busy states per block read.
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*/
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if (fun->wait_pattern) {
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while (!fun->dev_ready())
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debug("unexpected busy state\n");
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}
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}
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@ -148,13 +135,14 @@ int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
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if (fun->width != 8 && fun->width != 16 && fun->width != 32)
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return -ENOSYS;
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fun->last_ctrl = NAND_CLE;
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chip->priv = fun;
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chip->chip_delay = fun->chip_delay;
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chip->eccmode = NAND_ECC_SOFT;
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chip->hwcontrol = nand_hwcontrol;
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chip->ecc.mode = NAND_ECC_SOFT;
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chip->cmd_ctrl = fun_cmd_ctrl;
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chip->read_byte = nand_read_byte;
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chip->read_buf = nand_read_buf;
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chip->write_byte = nand_write_byte;
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chip->write_buf = nand_write_buf;
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chip->verify_buf = nand_verify_buf;
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if (fun->dev_ready)
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@ -31,6 +31,9 @@ struct fsl_upm_nand {
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int wait_pattern;
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int (*dev_ready)(void);
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int chip_delay;
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/* no need to fill */
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int last_ctrl;
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};
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extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun);
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