pci: layerscape: add official ls1028a binding support
The official bindind of the PCIe controller of the ls1028a has the following compatible string: compatible = "fsl,ls1028a-pcie"; Additionally, the resource names and count are different. Update the driver to support this binding and change the entry in the ls1028a device tree. Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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2 changed files with 53 additions and 28 deletions
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@ -344,12 +344,10 @@
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};
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};
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pcie1: pcie@3400000 {
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pcie1: pcie@3400000 {
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compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
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compatible = "fsl,ls1028a-pcie";
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reg = <0x00 0x03400000 0x0 0x80000
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reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
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0x00 0x03480000 0x0 0x40000 /* lut registers */
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<0x80 0x00000000 0x0 0x00002000>; /* configuration space */
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0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
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reg-names = "regs", "config";
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0x80 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "ctrl", "config";
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#address-cells = <3>;
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#address-cells = <3>;
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#size-cells = <2>;
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#size-cells = <2>;
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device_type = "pci";
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device_type = "pci";
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@ -360,12 +358,10 @@
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};
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};
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pcie2: pcie@3500000 {
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pcie2: pcie@3500000 {
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compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
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compatible = "fsl,ls1028a-pcie";
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reg = <0x00 0x03500000 0x0 0x80000
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reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
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0x00 0x03580000 0x0 0x40000 /* lut registers */
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<0x88 0x00000000 0x0 0x00002000>; /* configuration space */
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0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
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reg-names = "regs", "config";
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0x88 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "ctrl", "config";
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#address-cells = <3>;
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#address-cells = <3>;
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#size-cells = <2>;
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#size-cells = <2>;
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device_type = "pci";
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device_type = "pci";
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@ -21,6 +21,12 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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struct ls_pcie_drvdata {
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u32 lut_offset;
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u32 ctrl_offset;
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bool big_endian;
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};
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static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
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static void ls_pcie_cfg0_set_busdev(struct ls_pcie_rc *pcie_rc, u32 busdev)
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{
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{
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struct ls_pcie *pcie = pcie_rc->pcie;
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struct ls_pcie *pcie = pcie_rc->pcie;
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@ -243,6 +249,7 @@ static void ls_pcie_setup_ctrl(struct ls_pcie_rc *pcie_rc)
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static int ls_pcie_probe(struct udevice *dev)
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static int ls_pcie_probe(struct udevice *dev)
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{
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{
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const struct ls_pcie_drvdata *drvdata = (void *)dev_get_driver_data(dev);
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struct ls_pcie_rc *pcie_rc = dev_get_priv(dev);
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struct ls_pcie_rc *pcie_rc = dev_get_priv(dev);
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const void *fdt = gd->fdt_blob;
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const void *fdt = gd->fdt_blob;
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int node = dev_of_offset(dev);
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int node = dev_of_offset(dev);
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@ -260,8 +267,12 @@ static int ls_pcie_probe(struct udevice *dev)
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pcie_rc->pcie = pcie;
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pcie_rc->pcie = pcie;
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/* try resource name of the official binding first */
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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"dbi", &pcie_rc->dbi_res);
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"regs", &pcie_rc->dbi_res);
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if (ret)
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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"dbi", &pcie_rc->dbi_res);
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if (ret) {
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if (ret) {
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printf("ls-pcie: resource \"dbi\" not found\n");
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printf("ls-pcie: resource \"dbi\" not found\n");
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return ret;
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return ret;
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@ -287,21 +298,29 @@ static int ls_pcie_probe(struct udevice *dev)
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if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
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if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
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return 0;
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return 0;
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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if (drvdata) {
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"lut", &pcie_rc->lut_res);
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pcie->lut = pcie->dbi + drvdata->lut_offset;
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if (!ret)
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} else {
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pcie->lut = map_physmem(pcie_rc->lut_res.start,
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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fdt_resource_size(&pcie_rc->lut_res),
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"lut", &pcie_rc->lut_res);
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MAP_NOCACHE);
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if (!ret)
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pcie->lut = map_physmem(pcie_rc->lut_res.start,
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fdt_resource_size(&pcie_rc->lut_res),
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MAP_NOCACHE);
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}
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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if (drvdata) {
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"ctrl", &pcie_rc->ctrl_res);
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pcie->ctrl = pcie->lut + drvdata->ctrl_offset;
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if (!ret)
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} else {
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pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start,
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ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
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fdt_resource_size(&pcie_rc->ctrl_res),
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"ctrl", &pcie_rc->ctrl_res);
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MAP_NOCACHE);
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if (!ret)
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if (!pcie->ctrl)
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pcie->ctrl = map_physmem(pcie_rc->ctrl_res.start,
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pcie->ctrl = pcie->lut;
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fdt_resource_size(&pcie_rc->ctrl_res),
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MAP_NOCACHE);
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if (!pcie->ctrl)
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pcie->ctrl = pcie->lut;
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}
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if (!pcie->ctrl) {
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if (!pcie->ctrl) {
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printf("%s: NOT find CTRL\n", dev->name);
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printf("%s: NOT find CTRL\n", dev->name);
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@ -343,7 +362,10 @@ static int ls_pcie_probe(struct udevice *dev)
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pcie_rc->cfg1 = pcie_rc->cfg0 +
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pcie_rc->cfg1 = pcie_rc->cfg0 +
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fdt_resource_size(&pcie_rc->cfg_res) / 2;
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fdt_resource_size(&pcie_rc->cfg_res) / 2;
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pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
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if (drvdata)
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pcie->big_endian = drvdata->big_endian;
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else
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pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
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debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
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debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
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dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
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dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
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@ -373,8 +395,15 @@ static const struct dm_pci_ops ls_pcie_ops = {
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.write_config = ls_pcie_write_config,
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.write_config = ls_pcie_write_config,
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};
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};
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static const struct ls_pcie_drvdata ls1028a_drvdata = {
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.lut_offset = 0x80000,
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.ctrl_offset = 0x40000,
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.big_endian = false,
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};
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static const struct udevice_id ls_pcie_ids[] = {
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static const struct udevice_id ls_pcie_ids[] = {
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{ .compatible = "fsl,ls-pcie" },
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{ .compatible = "fsl,ls-pcie" },
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{ .compatible = "fsl,ls1028a-pcie", .data = (ulong)&ls1028a_drvdata },
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{ }
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{ }
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};
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};
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