Difuse/u-boot
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

mips: start.S: Add Octeon boot header compatibility

Browse source 
Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC.
Here the only 2 instructions are allowed in the first few bytes of the
image. And these instructions need to be one branch and a nop. This
patch adds the necessary nop after the nop, to that the common MIPS
image is compatible with this Octeon header.

The tool to patch the Octeon boot header into the image will be send in
a follow-up patch.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Stefan Roese 2020-10-28 15:09:59 +01:00 committed by Daniel Schwierzeck
parent a7ab4b71d5
commit de24bc7e0e
1 changed files with 8 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
arch/mips/cpu/start.S
View file

@ -74,9 +74,14 @@
.endm
ENTRY(_start)
/* U-Boot entry point */
/*
* U-Boot entry point.
* Do not add instructions to the branch delay slot! Some SoC's
* like Octeon might patch the final U-Boot binary at this location
* with additional boot headers.
*/
b reset
mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
nop
#if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG)
/*
@ -123,6 +128,7 @@ ENTRY(_start)
#endif
reset:
mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
#if __mips_isa_rev >= 6
mfc0 t0, CP0_CONFIG, 5
and t0, t0, MIPS_CONF5_VP