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mx6: Fix calculation of emi_slow clock rate

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This is porting of Freescale's patch from version imx_v2009.08_3.0.35_4.0.0,
that fixes the obvious mistype of bits offset macro name (ACLK_EMI_PODF_OFFSET
was used instead of ACLK_EMI_SLOW_PODF_OFFSET).

Using the occasion, change the variable name 'emi_slow_pof' to more consistent
'emi_slow_podf'.

Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
This commit is contained in:
Andrew Gabbasov 2013-07-04 06:27:32 -05:00 committed by Stefano Babic
parent 68e1747f9c
commit d55e0dabd7
1 changed files with 4 additions and 4 deletions
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8
arch/arm/cpu/armv7/mx6/clock.c
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@ -228,13 +228,13 @@ static u32 get_axi_clk(void)
static u32 get_emi_slow_clk(void) static u32 get_emi_slow_clk(void)
{ {
u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0; u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
cscmr1 = __raw_readl(&imx_ccm->cscmr1); cscmr1 = __raw_readl(&imx_ccm->cscmr1);
emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK; emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET; emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK; emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET; emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
switch (emi_clk_sel) { switch (emi_clk_sel) {
case 0: case 0:
@ -251,7 +251,7 @@ static u32 get_emi_slow_clk(void)
break; break;
} }
return root_freq / (emi_slow_pof + 1); return root_freq / (emi_slow_podf + 1);
} }
#ifdef CONFIG_MX6SL #ifdef CONFIG_MX6SL